From c4063a4ce534be9d586a5dbbea6af10a316c0d70 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 13 Dec 2018 02:43:02 +0000 Subject: [PATCH] back.rtlil: give clocks and resets nicer names. --- nmigen/back/rtlil.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 808ae32..0bd69f3 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -400,6 +400,13 @@ def convert_fragment(builder, fragment, name, clock_domains): for signal in fragment.ports: xformer.add_port(signal) + # Make sure clocks and resets get sensible names, by eagerly converting them outside + # of any hierarchy. + for cd_name, _ in fragment.iter_sync(): + cd = clock_domains[cd_name] + xformer(cd.clk) + xformer(cd.reset) + for subfragment, sub_name in fragment.subfragments: sub_name, sub_port_map = \ convert_fragment(builder, subfragment, sub_name, clock_domains) -- 2.30.2