From c40f6020ab36d6594c626c533e1073a0c2a6f696 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Dec 2021 12:32:31 +0000 Subject: [PATCH] whoops wrong variable names --- src/soc/experiment/pimem.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index cb17807d..51a6abef 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -226,8 +226,8 @@ class PortInterfaceBase(Elaboratable): # TODO: construct an MSRspec here and pass it over in # self.set_rd_addr and set_wr_addr below rather than just pr pr = ~pi.priv_mode - dr = ~pi.virt_mode # not yet used - sf = self.mode_32bit # not yet used + dr = pi.virt_mode # not yet used + sf = pi.mode_32bit # not yet used # detect busy "edge" busy_delay = Signal() -- 2.30.2