From c413b537ad80d8392a19975561b18063992a1939 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 May 2019 14:03:37 +0100 Subject: [PATCH] move test_buf_pipe.py unit test, shuffle nmutil --- src/ieee754/add/concurrentunit.py | 6 +++--- src/ieee754/add/fadd_state.py | 2 +- src/ieee754/add/fmul.py | 2 +- src/ieee754/add/fpbase.py | 2 +- src/ieee754/add/nmigen_div_experiment.py | 2 +- src/ieee754/add/record_experiment.py | 2 +- src/ieee754/add/test_fsm_experiment.py | 4 ++-- src/ieee754/add/test_inout_mux_pipe.py | 6 +++--- src/ieee754/add/test_outmux_pipe.py | 4 ++-- src/ieee754/add/test_prioritymux_pipe.py | 4 ++-- src/ieee754/fpadd/addstages.py | 2 +- src/ieee754/fpadd/pipeline.py | 6 +++--- src/ieee754/fpadd/specialcases.py | 2 +- src/ieee754/fpadd/statemachine.py | 2 +- src/ieee754/fpcommon/getop.py | 8 ++++---- src/ieee754/fpcommon/normtopack.py | 2 +- src/ieee754/fpcommon/pack.py | 2 +- src/{ieee754/add => nmutil}/iocontrol.py | 2 +- src/nmutil/multipipe.py | 2 +- src/nmutil/nmoperator.py | 2 +- src/nmutil/pipeline.py | 6 +++--- src/{ieee754/add => nmutil}/queue.py | 0 src/nmutil/singlepipe.py | 8 ++++---- src/{ieee754/add => nmutil}/stageapi.py | 2 +- src/{ieee754/add => nmutil/test}/example_buf_pipe.py | 6 +++--- src/{ieee754/add => nmutil/test}/test_buf_pipe.py | 12 ++++++------ 26 files changed, 49 insertions(+), 49 deletions(-) rename src/{ieee754/add => nmutil}/iocontrol.py (99%) rename src/{ieee754/add => nmutil}/queue.py (100%) rename src/{ieee754/add => nmutil}/stageapi.py (99%) rename src/{ieee754/add => nmutil/test}/example_buf_pipe.py (94%) rename src/{ieee754/add => nmutil/test}/test_buf_pipe.py (99%) diff --git a/src/ieee754/add/concurrentunit.py b/src/ieee754/add/concurrentunit.py index dbe4a964..9419d528 100644 --- a/src/ieee754/add/concurrentunit.py +++ b/src/ieee754/add/concurrentunit.py @@ -6,9 +6,9 @@ from math import log from nmigen import Module from nmigen.cli import main, verilog -from singlepipe import PassThroughStage -from multipipe import CombMuxOutPipe -from multipipe import PriorityCombMuxInPipe +from nmutil.singlepipe import PassThroughStage +from nmutil.multipipe import CombMuxOutPipe +from nmutil.multipipe import PriorityCombMuxInPipe from ieee754.fpcommon.getop import FPADDBaseData from ieee754.fpcommon.denorm import FPSCData diff --git a/src/ieee754/add/fadd_state.py b/src/ieee754/add/fadd_state.py index 7ad88786..be4f7d57 100644 --- a/src/ieee754/add/fadd_state.py +++ b/src/ieee754/add/fadd_state.py @@ -7,7 +7,7 @@ from nmigen.cli import main, verilog from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase -from singlepipe import eq +from nmutil.singlepipe import eq class FPADD(FPBase): diff --git a/src/ieee754/add/fmul.py b/src/ieee754/add/fmul.py index a2ba41e7..abe6f613 100644 --- a/src/ieee754/add/fmul.py +++ b/src/ieee754/add/fmul.py @@ -3,7 +3,7 @@ from nmigen.cli import main, verilog from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState from fpcommon.getop import FPGetOp -from singlepipe import eq +from nmutil.singlepipe import eq class FPMUL(FPBase): diff --git a/src/ieee754/add/fpbase.py b/src/ieee754/add/fpbase.py index f4908592..dbd4da27 100644 --- a/src/ieee754/add/fpbase.py +++ b/src/ieee754/add/fpbase.py @@ -7,7 +7,7 @@ from math import log from operator import or_ from functools import reduce -from singlepipe import PrevControl, NextControl +from nmutil.singlepipe import PrevControl, NextControl from pipeline import ObjectProxy diff --git a/src/ieee754/add/nmigen_div_experiment.py b/src/ieee754/add/nmigen_div_experiment.py index a7e215cb..a19decd5 100644 --- a/src/ieee754/add/nmigen_div_experiment.py +++ b/src/ieee754/add/nmigen_div_experiment.py @@ -6,7 +6,7 @@ from nmigen import Module, Signal, Const, Cat from nmigen.cli import main, verilog from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState -from singlepipe import eq +from nmutil.singlepipe import eq class Div: def __init__(self, width): diff --git a/src/ieee754/add/record_experiment.py b/src/ieee754/add/record_experiment.py index 1789c3bd..3d486c7d 100644 --- a/src/ieee754/add/record_experiment.py +++ b/src/ieee754/add/record_experiment.py @@ -3,7 +3,7 @@ from nmigen.hdl.rec import Record, Layout, DIR_NONE from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from nmigen.compat.fhdl.bitcontainer import value_bits_sign -from singlepipe import cat, RecordObject +from nmutil.singlepipe import cat, RecordObject class RecordTest: diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py index 17cee24e..1a338f56 100644 --- a/src/ieee754/add/test_fsm_experiment.py +++ b/src/ieee754/add/test_fsm_experiment.py @@ -8,8 +8,8 @@ from nmigen.compat.sim import run_simulation from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState -from nmoperator import eq -from singlepipe import SimpleHandshake, ControlBase +from nmutil.nmoperator import eq +from nmutil.singlepipe import SimpleHandshake, ControlBase from test_buf_pipe import data_chain2, Test5 diff --git a/src/ieee754/add/test_inout_mux_pipe.py b/src/ieee754/add/test_inout_mux_pipe.py index 35abe2ea..221ece1d 100644 --- a/src/ieee754/add/test_inout_mux_pipe.py +++ b/src/ieee754/add/test_inout_mux_pipe.py @@ -11,9 +11,9 @@ from nmigen import Module, Signal, Cat, Value, Elaboratable from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from multipipe import CombMultiOutPipeline, CombMuxOutPipe -from multipipe import PriorityCombMuxInPipe -from singlepipe import SimpleHandshake, RecordObject, Object +from nmutil.multipipe import CombMultiOutPipeline, CombMuxOutPipe +from nmutil.multipipe import PriorityCombMuxInPipe +from nmutil.singlepipe import SimpleHandshake, RecordObject, Object class PassData2(RecordObject): diff --git a/src/ieee754/add/test_outmux_pipe.py b/src/ieee754/add/test_outmux_pipe.py index b674a870..768d9d9a 100644 --- a/src/ieee754/add/test_outmux_pipe.py +++ b/src/ieee754/add/test_outmux_pipe.py @@ -4,8 +4,8 @@ from nmigen import Module, Signal, Cat, Elaboratable from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from multipipe import CombMuxOutPipe -from singlepipe import SimpleHandshake, PassThroughHandshake, RecordObject +from nmutil.multipipe import CombMuxOutPipe +from nmutil.singlepipe import SimpleHandshake, PassThroughHandshake, RecordObject class PassInData(RecordObject): diff --git a/src/ieee754/add/test_prioritymux_pipe.py b/src/ieee754/add/test_prioritymux_pipe.py index 5f7891e8..ca7181d0 100644 --- a/src/ieee754/add/test_prioritymux_pipe.py +++ b/src/ieee754/add/test_prioritymux_pipe.py @@ -4,8 +4,8 @@ from nmigen import Module, Signal, Cat from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil -from singlepipe import PassThroughStage -from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe) +from nmutil.singlepipe import PassThroughStage +from nmutil.multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe) class PassData: diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py index 62452c37..b373f1e3 100644 --- a/src/ieee754/fpadd/addstages.py +++ b/src/ieee754/fpadd/addstages.py @@ -5,7 +5,7 @@ from nmigen import Module from nmigen.cli import main, verilog -from singlepipe import (StageChain, SimpleHandshake, +from nmutil.singlepipe import (StageChain, SimpleHandshake, PassThroughStage) from fpbase import FPState diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py index 5c4eed18..eea89355 100644 --- a/src/ieee754/fpadd/pipeline.py +++ b/src/ieee754/fpadd/pipeline.py @@ -5,9 +5,9 @@ from nmigen import Module from nmigen.cli import main, verilog -from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage) -from multipipe import CombMuxOutPipe -from multipipe import PriorityCombMuxInPipe +from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage) +from nmutil.multipipe import CombMuxOutPipe +from nmutil.multipipe import PriorityCombMuxInPipe from ieee754.fpcommon.getop import FPADDBaseData from ieee754.fpcommon.denorm import FPSCData diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py index 39254a74..978851ef 100644 --- a/src/ieee754/fpadd/specialcases.py +++ b/src/ieee754/fpadd/specialcases.py @@ -7,7 +7,7 @@ from nmigen.cli import main, verilog from math import log from fpbase import FPNumDecode -from singlepipe import SimpleHandshake, StageChain +from nmutil.singlepipe import SimpleHandshake, StageChain from fpbase import FPState, FPID from ieee754.fpcommon.getop import FPADDBaseData diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py index e7f298d3..5afe702e 100644 --- a/src/ieee754/fpadd/statemachine.py +++ b/src/ieee754/fpadd/statemachine.py @@ -8,7 +8,7 @@ from math import log from fpbase import FPOpIn, FPOpOut from fpbase import Trigger -from singlepipe import (StageChain, SimpleHandshake) +from nmutil.singlepipe import (StageChain, SimpleHandshake) from fpbase import FPState, FPID from ieee754.fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op) diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py index 1988997a..f772d904 100644 --- a/src/ieee754/fpcommon/getop.py +++ b/src/ieee754/fpcommon/getop.py @@ -9,13 +9,13 @@ from math import log from fpbase import FPNumIn, FPNumOut, FPOpIn, Overflow, FPBase, FPNumBase from fpbase import MultiShiftRMerge, Trigger -from singlepipe import (ControlBase, StageChain, SimpleHandshake, +from nmutil.singlepipe import (ControlBase, StageChain, SimpleHandshake, PassThroughStage, PrevControl) -from multipipe import CombMuxOutPipe -from multipipe import PriorityCombMuxInPipe +from nmutil.multipipe import CombMuxOutPipe +from nmutil.multipipe import PriorityCombMuxInPipe from fpbase import FPState -import nmoperator +from nmutil import nmoperator class FPGetOpMod(Elaboratable): diff --git a/src/ieee754/fpcommon/normtopack.py b/src/ieee754/fpcommon/normtopack.py index 7d871f42..ac97bf1c 100644 --- a/src/ieee754/fpcommon/normtopack.py +++ b/src/ieee754/fpcommon/normtopack.py @@ -4,7 +4,7 @@ #from nmigen.cli import main, verilog -from singlepipe import StageChain, SimpleHandshake +from nmutil.singlepipe import StageChain, SimpleHandshake from fpbase import FPState, FPID from .postcalc import FPAddStage1Data diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py index 18d6921d..7407cfb6 100644 --- a/src/ieee754/fpcommon/pack.py +++ b/src/ieee754/fpcommon/pack.py @@ -8,7 +8,7 @@ from nmigen.cli import main, verilog from fpbase import FPNumOut from fpbase import FPState from .roundz import FPRoundData -from singlepipe import Object +from nmutil.singlepipe import Object class FPPackData(Object): diff --git a/src/ieee754/add/iocontrol.py b/src/nmutil/iocontrol.py similarity index 99% rename from src/ieee754/add/iocontrol.py rename to src/nmutil/iocontrol.py index 3d823c9b..0e2810b5 100644 --- a/src/ieee754/add/iocontrol.py +++ b/src/nmutil/iocontrol.py @@ -86,7 +86,7 @@ from nmigen.hdl.rec import Record from collections.abc import Sequence, Iterable from collections import OrderedDict -import nmoperator +from nmutil import nmoperator class Object: diff --git a/src/nmutil/multipipe.py b/src/nmutil/multipipe.py index e24703f8..04ab6f7e 100644 --- a/src/nmutil/multipipe.py +++ b/src/nmutil/multipipe.py @@ -15,7 +15,7 @@ from nmigen import Signal, Cat, Const, Mux, Module, Array, Elaboratable from nmigen.cli import verilog, rtlil from nmigen.lib.coding import PriorityEncoder from nmigen.hdl.rec import Record, Layout -from stageapi import _spec +from nmutil.stageapi import _spec from collections.abc import Sequence diff --git a/src/nmutil/nmoperator.py b/src/nmutil/nmoperator.py index bd5e5544..bdf14572 100644 --- a/src/nmutil/nmoperator.py +++ b/src/nmutil/nmoperator.py @@ -18,7 +18,7 @@ from nmigen.hdl.rec import Record, Layout from abc import ABCMeta, abstractmethod from collections.abc import Sequence, Iterable from collections import OrderedDict -from queue import Queue +from nmutil.queue import Queue import inspect diff --git a/src/nmutil/pipeline.py b/src/nmutil/pipeline.py index afcee743..812b5278 100644 --- a/src/nmutil/pipeline.py +++ b/src/nmutil/pipeline.py @@ -8,9 +8,9 @@ from nmigen import tracer from nmigen.compat.fhdl.bitcontainer import value_bits_sign from contextlib import contextmanager -from nmoperator import eq -from singlepipe import StageCls, ControlBase, BufferedHandshake -from singlepipe import UnbufferedPipeline +from nmutil.nmoperator import eq +from nmutil.singlepipe import StageCls, ControlBase, BufferedHandshake +from nmutil.singlepipe import UnbufferedPipeline # The following example shows how pyrtl can be used to make some interesting diff --git a/src/ieee754/add/queue.py b/src/nmutil/queue.py similarity index 100% rename from src/ieee754/add/queue.py rename to src/nmutil/queue.py diff --git a/src/nmutil/singlepipe.py b/src/nmutil/singlepipe.py index 68b62e43..b9214bd5 100644 --- a/src/nmutil/singlepipe.py +++ b/src/nmutil/singlepipe.py @@ -132,12 +132,12 @@ from nmigen import Signal, Mux, Module, Elaboratable from nmigen.cli import verilog, rtlil from nmigen.hdl.rec import Record -from queue import Queue +from nmutil.queue import Queue import inspect -from iocontrol import (PrevControl, NextControl, Object, RecordObject) -from stageapi import (_spec, StageCls, Stage, StageChain, StageHelper) -import nmoperator +from nmutil.iocontrol import (PrevControl, NextControl, Object, RecordObject) +from nmutil.stageapi import (_spec, StageCls, Stage, StageChain, StageHelper) +from nmutil import nmoperator class RecordBasedStage(Stage): diff --git a/src/ieee754/add/stageapi.py b/src/nmutil/stageapi.py similarity index 99% rename from src/ieee754/add/stageapi.py rename to src/nmutil/stageapi.py index 9651bf79..33fd995d 100644 --- a/src/ieee754/add/stageapi.py +++ b/src/nmutil/stageapi.py @@ -80,7 +80,7 @@ from abc import ABCMeta, abstractmethod import inspect -import nmoperator +from nmutil import nmoperator def _spec(fn, name=None): diff --git a/src/ieee754/add/example_buf_pipe.py b/src/nmutil/test/example_buf_pipe.py similarity index 94% rename from src/ieee754/add/example_buf_pipe.py rename to src/nmutil/test/example_buf_pipe.py index 4bb7cdf1..61e9b134 100644 --- a/src/ieee754/add/example_buf_pipe.py +++ b/src/nmutil/test/example_buf_pipe.py @@ -1,9 +1,9 @@ """ Pipeline and BufferedHandshake examples """ -from nmoperator import eq -from iocontrol import (PrevControl, NextControl) -from singlepipe import (PrevControl, NextControl, ControlBase, +from nmutil.nmoperator import eq +from nmutil.iocontrol import (PrevControl, NextControl) +from nmutil.singlepipe import (PrevControl, NextControl, ControlBase, StageCls, Stage, StageChain, BufferedHandshake, UnbufferedPipeline) diff --git a/src/ieee754/add/test_buf_pipe.py b/src/nmutil/test/test_buf_pipe.py similarity index 99% rename from src/ieee754/add/test_buf_pipe.py rename to src/nmutil/test/test_buf_pipe.py index 37f2b31f..089163c5 100644 --- a/src/ieee754/add/test_buf_pipe.py +++ b/src/nmutil/test/test_buf_pipe.py @@ -24,12 +24,12 @@ from example_buf_pipe import ExamplePipeline, UnbufferedPipeline from example_buf_pipe import ExampleStageCls from example_buf_pipe import PrevControl, NextControl, BufferedHandshake from example_buf_pipe import StageChain, ControlBase, StageCls -from singlepipe import UnbufferedPipeline2 -from singlepipe import SimpleHandshake -from singlepipe import PassThroughHandshake -from singlepipe import PassThroughStage -from singlepipe import FIFOControl -from singlepipe import RecordObject +from nmutil.singlepipe import UnbufferedPipeline2 +from nmutil.singlepipe import SimpleHandshake +from nmutil.singlepipe import PassThroughHandshake +from nmutil.singlepipe import PassThroughStage +from nmutil.singlepipe import FIFOControl +from nmutil.singlepipe import RecordObject from random import randint, seed -- 2.30.2