From c41524681bf2dad22390fe2b1cfbdeac1576e1e5 Mon Sep 17 00:00:00 2001 From: Reuben Thomas Date: Thu, 24 Mar 2022 12:05:21 +0000 Subject: [PATCH] =?utf8?q?sim:=20fix=20=E2=80=9Calligned=E2=80=9D=20typos?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Change-Id: Ifd574e38524dd4f1cf0fc003e0c5c7499abc84a0 --- sim/common/sim-core.h | 4 ++-- sim/ppc/hw_init.c | 2 +- sim/ppc/std-config.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h index 5f152ee0552..df4e3e17a7b 100644 --- a/sim/common/sim-core.h +++ b/sim/common/sim-core.h @@ -248,7 +248,7 @@ extern void *sim_core_trans_addr order (including xor endian). Should the transfer fail, the operation shall abort (no return). - ALIGNED assumes yhat the specified ADDRESS is correctly alligned + ALIGNED assumes that the specified ADDRESS is correctly aligned for an N byte transfer (no alignment checks are made). Passing an incorrectly aligned ADDRESS is erroneous. @@ -256,7 +256,7 @@ extern void *sim_core_trans_addr of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being taken should the check fail. - MISSALIGNED transfers the data regardless. + MISALIGNED transfers the data regardless. Misaligned xor-endian accesses are broken into a sequence of transfers each <= WITH_XOR_ENDIAN bytes */ diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c index 3d58833bb3d..66f205851d5 100644 --- a/sim/ppc/hw_init.c +++ b/sim/ppc/hw_init.c @@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me, const unsigned sizeof_argv = sizeof_arguments(argv); const unsigned_word start_argv = start_envp - sizeof_argv; - /* link register save address - alligned to a 16byte boundary */ + /* link register save address - aligned to a 16byte boundary */ const unsigned_word top_of_stack = ((start_argv - 2 * sizeof(unsigned_word)) & ~0xf); diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h index 0619d1dff19..e02d5946a73 100644 --- a/sim/ppc/std-config.h +++ b/sim/ppc/std-config.h @@ -183,7 +183,7 @@ extern int current_environment; This model. Instead allows both little and big endian modes to either take exceptions or handle miss aligned transfers. - If 0 is specified then for big-endian mode miss alligned accesses + If 0 is specified then for big-endian mode miss aligned accesses are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the processor will fault on them (STRICT_ALIGNMENT). */ -- 2.30.2