From c42bce582a7987856f63165abddaf4cd48e3b448 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 23 May 2011 02:26:05 -0700 Subject: [PATCH] [sim,xcc] add rdcycle/rdtime/rdinstret --- riscv/insns/rdcycle.h | 2 +- riscv/insns/rdinstret.h | 2 +- riscv/insns/rdtime.h | 2 +- riscv/processor.cc | 4 ++-- riscv/processor.h | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/riscv/insns/rdcycle.h b/riscv/insns/rdcycle.h index 96f2a74..9b966a6 100644 --- a/riscv/insns/rdcycle.h +++ b/riscv/insns/rdcycle.h @@ -1 +1 @@ -throw trap_illegal_instruction; +RD = cycle; diff --git a/riscv/insns/rdinstret.h b/riscv/insns/rdinstret.h index 96f2a74..9b966a6 100644 --- a/riscv/insns/rdinstret.h +++ b/riscv/insns/rdinstret.h @@ -1 +1 @@ -throw trap_illegal_instruction; +RD = cycle; diff --git a/riscv/insns/rdtime.h b/riscv/insns/rdtime.h index 96f2a74..9b966a6 100644 --- a/riscv/insns/rdtime.h +++ b/riscv/insns/rdtime.h @@ -1 +1 @@ -throw trap_illegal_instruction; +RD = cycle; diff --git a/riscv/processor.cc b/riscv/processor.cc index 0bab83a..4e06da4 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -28,11 +28,10 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz) fromhost = 0; count = 0; compare = 0; + cycle = 0; set_sr(SR_S | SR_SX); // SX ignored if 64b mode not supported set_fsr(0); - memset(counters,0,sizeof(counters)); - // vector stuff vecbanks = 0xff; vecbanks_count = 8; @@ -175,6 +174,7 @@ void processor_t::step(size_t n, bool noisy) if(count++ == compare) cause |= 1 << (TIMER_IRQ+CAUSE_IP_SHIFT); + cycle++; } return; } diff --git a/riscv/processor.h b/riscv/processor.h index 7a09edf..1f458d5 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -51,7 +51,7 @@ private: mmu_t mmu; // counters - reg_t counters[32]; + reg_t cycle; // functions void set_sr(uint32_t val); -- 2.30.2