From c44e1bec6d2a549abb9d56c98e41c23bc698e12d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 3 Jan 2014 18:17:28 +0100 Subject: [PATCH] More freduce cleanups --- passes/sat/freduce.cc | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 23ab8a04a..44c095d28 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -52,6 +52,22 @@ struct equiv_bit_t } }; +struct CountBitUsage +{ + SigMap &sigmap; + std::map &cache; + + CountBitUsage(SigMap &sigmap, std::map &cache) : sigmap(sigmap), cache(cache) { } + + void operator()(RTLIL::SigSpec &sig) + { + std::vector vec = sigmap(sig).to_sigbit_vector(); + for (auto &bit : vec) { + log("%s %d\n", log_signal(bit), cache[bit]++); + } + } +}; + struct FindReducedInputs { SigMap &sigmap; @@ -478,6 +494,9 @@ struct FreduceWorker worker.analyze(equiv); } + std::map bitusage; + module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage)); + log(" Rewiring %d equivialent groups:\n", int(equiv.size())); int rewired_sigbits = 0; for (auto &grp : equiv) @@ -492,6 +511,11 @@ struct FreduceWorker continue; } + if (grp[i].bit.wire->port_id == 0 && bitusage[grp[i].bit] <= 1) { + log(" Skipping unused slave: %s\n", log_signal(grp[i].bit)); + continue; + } + log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit)); RTLIL::Cell *drv = drivers.at(grp[i].bit).first; -- 2.30.2