From c45a2145f5eaae53d48e3aa7e0f10f2c70f267b0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 6 May 2020 14:51:50 -0400 Subject: [PATCH] radeonsi: disable the L2 cache for CPU read mappings of buffers for faster copying over PCIe and no need to flush L2 Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_buffer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index a1805ddfc03..e64b51d8d0a 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -479,8 +479,9 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resour struct si_resource *staging; assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_TRANSFER_THREAD_SAFE))); - staging = si_resource(pipe_buffer_create(ctx->screen, 0, PIPE_USAGE_STAGING, - box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT))); + staging = si_aligned_buffer_create(ctx->screen, SI_RESOURCE_FLAG_UNCACHED, + PIPE_USAGE_STAGING, + box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT), 256); if (staging) { /* Copy the VRAM buffer to the staging buffer. */ si_sdma_copy_buffer(sctx, &staging->b.b, resource, box->x % SI_MAP_BUFFER_ALIGNMENT, -- 2.30.2