From c47427ce770a8b59c3e47a7e37fdbc30c959ab53 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 11 Oct 2020 16:01:58 +0100 Subject: [PATCH] add way to bypass PLL for ECP5 and sim --- src/soc/simple/issuer.py | 12 ++++++++++-- src/soc/simple/issuer_verilog.py | 1 + 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index aafae394..64350c96 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -447,15 +447,23 @@ class TestIssuerInternal(Elaboratable): class TestIssuer(Elaboratable): def __init__(self, pspec): self.ti = TestIssuerInternal(pspec) + self.pll = DummyPLL() self.clksel = ClockSelect() + # PLL direct clock or not + self.pll_en = hasattr(pspec, "use_pll") and pspec.pll_en + def elaborate(self, platform): m = Module() comb = m.d.comb - # TestIssuer runs at internal clock rate - m.submodules.ti = ti = DomainRenamer("intclk")(self.ti) + if self.pll_en: + # TestIssuer runs at internal clock rate + m.submodules.ti = ti = DomainRenamer("intclk")(self.ti) + else: + # TestIssuer runs at direct clock + m.submodules.ti = ti = self.ti # ClockSelect runs at PLL output internal clock rate m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel) m.submodules.pll = pll = self.pll diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 383afa0d..95eb748d 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -29,6 +29,7 @@ if __name__ == '__main__': #wb_data_wid=32, xics=True, #nocore=True, # to help test coriolis2 ioring + use_pll=False, # bypass PLL gpio=True, # for test purposes debug="jtag", # set to jtag or dmi units=units) -- 2.30.2