From c4834fb62c0a910a5b3623a853744c26b4ce1858 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 9 May 2022 14:40:46 +0100 Subject: [PATCH] update comments on sv.svstep --- src/openpower/sv/trans/svp64.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index dfe3ce18..11994cf8 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -209,9 +209,9 @@ class SVP64Asm: yield ".long 0x%x" % insn return - # this is a *32-bit-only* instruction. it updates SVSTATE. - # it is *not* a 64-bit-prefixed Vector instruction (no sv.svstep), - # it is a Vector *control* instruction. + # this is a 32-bit instruction. it updates SVSTATE. + # it *can* be SVP64-prefixed, to indicate that its registers + # are Vectorised. # note: EXT022 is the "sandbox" major opcode so it's fine to add # sigh have to do setvl here manually for now... -- 2.30.2