From c49fe862c6e2f543e6caa123dcb9bdc324abd84f Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Fri, 12 Jan 2024 22:24:22 +0300
Subject: [PATCH] oppc/code: simplify exprs and regs

---
 src/openpower/oppc/pc_code.py | 117 ++++++++++++++++------------------
 1 file changed, 56 insertions(+), 61 deletions(-)

diff --git a/src/openpower/oppc/pc_code.py b/src/openpower/oppc/pc_code.py
index b0bfaede..a4bbe665 100644
--- a/src/openpower/oppc/pc_code.py
+++ b/src/openpower/oppc/pc_code.py
@@ -47,15 +47,12 @@ class CodeVisitor(pc_util.Visitor):
         if isinstance(node.rvalue, (pc_ast.GPR, pc_ast.FPR)):
             self.__regfetch[str(node.rvalue)].append(node.rvalue)
 
-        if str(node.lvalue) in self.__decls:
-            stmt = " ".join([
-                str(self[node.lvalue]),
-                "=",
-                str(self[node.rvalue]),
-            ])
-            self[node].emit(stmt=f"{stmt};")
-        else:
-            raise ValueError(node)
+        stmt = " ".join([
+            str(self[node.lvalue]),
+            "=",
+            str(self[node.rvalue]),
+        ])
+        self[node].emit(stmt=f"{stmt};")
 
     @pc_util.Hook(pc_ast.BinaryExpr)
     def BinaryExpr(self, node):
@@ -64,62 +61,30 @@ class CodeVisitor(pc_util.Visitor):
             self.__regfetch[str(node.left)].append(node.left)
         if isinstance(node.right, (pc_ast.GPR, pc_ast.FPR)):
             self.__regfetch[str(node.right)].append(node.left)
-        if isinstance(node.left, (pc_ast.GPR, pc_ast.FPR)):
-            left = f"oppc_reg_fetch({str(self[node.left])})"
-        else:
-            left = str(self[node.left])
-        if isinstance(node.right, (pc_ast.GPR, pc_ast.FPR)):
-            right = f"oppc_reg_fetch({str(self[node.right])})"
-        else:
-            right = str(self[node.right])
-        if isinstance(node.op, (pc_ast.Add, pc_ast.Sub,
-                    pc_ast.Mul, pc_ast.Div, pc_ast.Mod,
-                    pc_ast.Lt, pc_ast.Le,
-                    pc_ast.Eq, pc_ast.NotEq,
-                    pc_ast.Ge, pc_ast.Gt,
-                    pc_ast.LShift, pc_ast.RShift,
-                    pc_ast.BitAnd, pc_ast.BitOr, pc_ast.BitXor,
-                )):
-            op = {
-                pc_ast.Not: "~",
-                pc_ast.Add: "+",
-                pc_ast.Sub: "-",
-                pc_ast.Mul: "*",
-                pc_ast.Div: "/",
-                pc_ast.Mod: "%",
-                pc_ast.Lt: "<",
-                pc_ast.Le: "<=",
-                pc_ast.Eq: "==",
-                pc_ast.NotEq: "!=",
-                pc_ast.Ge: ">=",
-                pc_ast.Gt: ">",
-                pc_ast.LShift: "<<",
-                pc_ast.RShift: "<<",
-                pc_ast.BitAnd: "&",
-                pc_ast.BitOr: "|",
-                pc_ast.BitXor: "^",
-            }[node.op.__class__]
-            stmt = " ".join([left, op, right])
-            self[node].emit(stmt=f"({stmt})")
-        else:
-            raise ValueError(node)
+        special = (
+            pc_ast.MulS,
+            pc_ast.MulU,
+            pc_ast.DivT,
+            pc_ast.Sqrt,
+            pc_ast.BitConcat
+        )
+        if isinstance(node.op, special):
+            raise NotImplementedError(node)
+        stmt = " ".join([
+            str(self[node.left]),
+            str(self[node.op]),
+            str(self[node.right]),
+        ])
+        self[node].emit(stmt=f"({stmt})")
 
     @pc_util.Hook(pc_ast.UnaryExpr)
     def UnaryExpr(self, node):
         yield node
-        if isinstance(node.value, (pc_ast.GPR, pc_ast.FPR)):
-            value = f"oppc_reg_fetch({str(self[node.value])})"
-        else:
-            value = f"({str(self[node.value])})"
-        if isinstance(node.op, (pc_ast.Not, pc_ast.Add, pc_ast.Sub)):
-            op = {
-                pc_ast.Not: "~",
-                pc_ast.Add: "+",
-                pc_ast.Sub: "-",
-            }[node.op.__class__]
-            self[node].emit(stmt="".join([op, value]))
-        else:
-            raise ValueError(node)
+        stmt = "".join([
+            str(self[node.op]),
+            f"({str(self[node.value])})",
+        ])
+        self[node].emit(stmt=stmt)
 
     @pc_util.Hook(
             pc_ast.Not, pc_ast.Add, pc_ast.Sub,
@@ -132,6 +97,26 @@ class CodeVisitor(pc_util.Visitor):
         )
     def Op(self, node):
         yield node
+        op = {
+            pc_ast.Not: "~",
+            pc_ast.Add: "+",
+            pc_ast.Sub: "-",
+            pc_ast.Mul: "*",
+            pc_ast.Div: "/",
+            pc_ast.Mod: "%",
+            pc_ast.Lt: "<",
+            pc_ast.Le: "<=",
+            pc_ast.Eq: "==",
+            pc_ast.NotEq: "!=",
+            pc_ast.Ge: ">=",
+            pc_ast.Gt: ">",
+            pc_ast.LShift: "<<",
+            pc_ast.RShift: "<<",
+            pc_ast.BitAnd: "&",
+            pc_ast.BitOr: "|",
+            pc_ast.BitXor: "^",
+        }[node.__class__]
+        self[node].emit(stmt=op)
 
     @pc_util.Hook(pc_ast.BinLiteral, pc_ast.DecLiteral, pc_ast.HexLiteral)
     def Integer(self, node):
@@ -146,6 +131,16 @@ class CodeVisitor(pc_util.Visitor):
             raise ValueError(node)
         self[node].emit(stmt=f"UINT64_C({hex(int(node, base))})")
 
+    @pc_util.Hook(pc_ast.GPR)
+    def GPR(self, node):
+        yield node
+        self[node].emit(stmt=f"ctx->gpr[OPPC_GPR_{str(node)}]")
+
+    @pc_util.Hook(pc_ast.FPR)
+    def FPR(self, node):
+        yield node
+        self[node].emit(stmt=f"ctx->fpr[OPPC_FPR_{str(node)}]")
+
     @pc_util.Hook(pc_ast.Call.Name)
     def CallName(self, node):
         yield node
-- 
2.30.2