From c4bdff672d08114bcdea3aa37a25bc9c34264b1c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 20 May 2020 14:50:39 +0100 Subject: [PATCH] output ilang for ALU to unique file --- src/soc/fu/alu/test/test_pipe_caller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 9a9e5571..935e272f 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -166,7 +166,7 @@ class ALUTestCase(FHDLTestCase): pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec)) alu = ALUBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) - with open("pipeline.il", "w") as f: + with open("alu_pipeline.il", "w") as f: f.write(vl) -- 2.30.2