From c50443ec48b0fece7e6cbc84d2792fad44f4f922 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 Apr 2022 13:53:24 +0100
Subject: [PATCH] accidentally added svfixedarith.mdwn to wiki rather than as
 an underlay in openpower-isa repo

---
 openpower/isa/svfixedarith.mdwn | 47 +++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 openpower/isa/svfixedarith.mdwn

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
new file mode 100644
index 00000000..ebef59ce
--- /dev/null
+++ b/openpower/isa/svfixedarith.mdwn
@@ -0,0 +1,47 @@
+# [DRAFT] Twin Multiply and Add Doubleword
+
+VA-Form
+
+* madded RT,RA,RB,RC
+
+Pseudo-code:
+
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
+    prod[0:127] <- (RA) * (RB)
+    sum[0:127] <- EXTZ(RC) + prod
+    RT <- sum[64:127]
+    RS <- sum[0:63]
+
+Special Registers Altered:
+
+    None
+
+# [DRAFT] Twin Divide Quad Unsigned
+
+VA-Form
+
+* divmod2du   RT,RA,RB,RC
+
+Pseudo-code:
+
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
+    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
+        dividend[0:(XLEN*2)-1] <- (RA) || (RC)
+        divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
+        result <- dividend / divisor
+        modulo <- dividend % divisor
+        RT <- result[XLEN:(XLEN*2)-1]
+        RS <- modulo[XLEN:(XLEN*2)-1]
+        overflow <- 0
+    else
+        overflow <- 1
+        RT <- [1]*XLEN
+        RS <- [0]*XLEN
+
+Special Registers Altered:
+
+    None
-- 
2.30.2