From c506c9752cc575936c5cfadcabd5729459d8f3da Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 29 Oct 2018 11:41:04 +0100 Subject: [PATCH] gen/fhdl/verilog: set direction to io signals --- litex/gen/fhdl/verilog.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index ec858b26..70a980fa 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -207,13 +207,16 @@ def _printheader(f, ios, name, ns, attr_translate, if attr: r += "\t" + attr if sig in inouts: + sig.direction = "inout" r += "\tinout " + _printsig(ns, sig) elif sig in targets: + sig.direction = "output" if sig in wires: r += "\toutput " + _printsig(ns, sig) else: r += "\toutput reg " + _printsig(ns, sig) else: + sig.direction = "input" r += "\tinput " + _printsig(ns, sig) r += "\n);\n\n" for sig in sorted(sigs - ios, key=lambda x: x.duid): -- 2.30.2