From c57aa545ca271fddc7d94f912ea64d3f769a0d31 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 9 Nov 2018 18:27:01 +0100 Subject: [PATCH] targets/ulx3s: get memtest working by disabling sdram refresh Will need to be fixed... --- litex/boards/targets/ulx3s.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index af1aa19e..8ff3777c 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -12,6 +12,7 @@ from litex.soc.integration.builder import * from litedram.modules import MT48LC16M16 from litedram.phy import GENSDRPHY +from litedram.core.controller import ControllerSettings class _CRG(Module): @@ -69,7 +70,9 @@ class BaseSoC(SoCSDRAM): sdram_module = MT48LC16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings, - sdram_module.timing_settings) + sdram_module.timing_settings, + controller_settings=ControllerSettings( + with_refresh=False)) # FIXME def main(): -- 2.30.2