From c59356d1de9646b73acc614fe853411770f83c9a Mon Sep 17 00:00:00 2001
From: Albert Ou <albert@sifive.com>
Date: Wed, 2 Aug 2017 13:50:00 -0700
Subject: [PATCH] spi: Fix invalid D channel response when flash interface is
 disabled

Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.

Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.
---
 src/main/scala/devices/spi/SPIFlash.scala | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/devices/spi/SPIFlash.scala b/src/main/scala/devices/spi/SPIFlash.scala
index b038482..17144b8 100644
--- a/src/main/scala/devices/spi/SPIFlash.scala
+++ b/src/main/scala/devices/spi/SPIFlash.scala
@@ -86,7 +86,7 @@ class SPIFlashMap(c: SPIFlashParamsBase) extends Module {
     }
   }
 
-  val (s_idle :: s_cmd :: s_addr :: s_pad :: s_data_pre :: s_data_post :: Nil) = Enum(UInt(), 6)
+  val (s_idle :: s_cmd :: s_addr :: s_pad :: s_data_pre :: s_data_post :: s_off :: Nil) = Enum(UInt(), 7)
   val state = Reg(init = s_idle)
 
   switch (state) {
@@ -105,10 +105,11 @@ class SPIFlashMap(c: SPIFlashParamsBase) extends Module {
           io.link.lock := Bool(false)
         }
       } .otherwise {
-        io.data.valid := io.addr.valid
-        io.addr.ready := io.data.ready
-        io.data.bits := UInt(0)
+        io.addr.ready := Bool(true)
         io.link.lock := Bool(false)
+        when (io.addr.valid) {
+          state := s_off
+        }
       }
     }
 
@@ -158,5 +159,13 @@ class SPIFlashMap(c: SPIFlashParamsBase) extends Module {
         state := s_idle
       }
     }
+
+    is (s_off) {
+      io.data.valid := Bool(true)
+      io.data.bits := UInt(0)
+      when (io.data.ready) {
+        state := s_idle
+      }
+    }
   }
 }
-- 
2.30.2