From c596f6aa4daf1397f498f22143f547ac0ae82da4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 May 2020 12:36:53 +0000 Subject: [PATCH] add test_fu_fu_matrix.il --- experiments8/test_fu_fu_matrix.il | 1787 +++++++++++++++++++++++------ 1 file changed, 1433 insertions(+), 354 deletions(-) diff --git a/experiments8/test_fu_fu_matrix.il b/experiments8/test_fu_fu_matrix.il index f3303c9..1a98cfb 100644 --- a/experiments8/test_fu_fu_matrix.il +++ b/experiments8/test_fu_fu_matrix.il @@ -3524,6 +3524,1181 @@ module \dm2 end end attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.dm3.src1_c" +module \src1_c$11 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \r_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 input 3 \s_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 output 4 \qlq_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_rd0_c + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $3 + connect \B \s_rd0_c + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518" + switch \rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \q_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_rd0_c + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $9 + connect \B \s_rd0_c + connect \Y $11 + end + process $group_1 + assign \q_rd0_c 4'0000 + assign \q_rd0_c $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \qn_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_rd0_c + connect \Y $13 + end + process $group_2 + assign \qn_rd0_c 4'0000 + assign \qn_rd0_c $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_rd0_c + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rd0_c 4'0000 + assign \qlq_rd0_c $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.dm3.src2_c" +module \src2_c$12 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \r_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 input 3 \s_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 output 4 \qlq_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_rd1_c + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $3 + connect \B \s_rd1_c + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518" + switch \rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \q_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_rd1_c + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $9 + connect \B \s_rd1_c + connect \Y $11 + end + process $group_1 + assign \q_rd1_c 4'0000 + assign \q_rd1_c $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \qn_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_rd1_c + connect \Y $13 + end + process $group_2 + assign \qn_rd1_c 4'0000 + assign \qn_rd1_c $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_rd1_c + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rd1_c 4'0000 + assign \qlq_rd1_c $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.dm3.src3_c" +module \src3_c$13 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \r_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 input 3 \s_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 output 4 \qlq_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_rd2_c + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $3 + connect \B \s_rd2_c + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518" + switch \rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \q_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_rd2_c + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $9 + connect \B \s_rd2_c + connect \Y $11 + end + process $group_1 + assign \q_rd2_c 4'0000 + assign \q_rd2_c $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \qn_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_rd2_c + connect \Y $13 + end + process $group_2 + assign \qn_rd2_c 4'0000 + assign \qn_rd2_c $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_rd2_c + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_rd2_c 4'0000 + assign \qlq_rd2_c $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.dm3.dst1_c" +module \dst1_c$14 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \r_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 input 3 \s_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 output 4 \qlq_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_wr0_c + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $3 + connect \B \s_wr0_c + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518" + switch \rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \q_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_wr0_c + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $9 + connect \B \s_wr0_c + connect \Y $11 + end + process $group_1 + assign \q_wr0_c 4'0000 + assign \q_wr0_c $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \qn_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_wr0_c + connect \Y $13 + end + process $group_2 + assign \qn_wr0_c 4'0000 + assign \qn_wr0_c $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_wr0_c + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_wr0_c 4'0000 + assign \qlq_wr0_c $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.dm3.dst2_c" +module \dst2_c$15 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 0 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 1 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \r_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 input 3 \s_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 output 4 \qlq_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $not $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_wr1_c + connect \Y $1 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $and $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $1 + connect \Y $3 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 $5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + cell $or $6 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $3 + connect \B \s_wr1_c + connect \Y $5 + end + process $group_0 + assign \q_int$next \q_int + assign \q_int$next $5 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:518" + switch \rst + case 1'1 + assign \q_int$next 4'0000 + end + sync init + update \q_int 4'0000 + sync posedge \clk + update \q_int \q_int$next + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 \q_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $not $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \r_wr1_c + connect \Y $7 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $and $10 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_int + connect \B $7 + connect \Y $9 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:71" + cell $or $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $9 + connect \B \s_wr1_c + connect \Y $11 + end + process $group_1 + assign \q_wr1_c 4'0000 + assign \q_wr1_c $11 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 \qn_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 $13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $14 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_wr1_c + connect \Y $13 + end + process $group_2 + assign \qn_wr1_c 4'0000 + assign \qn_wr1_c $13 + sync init + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \q_wr1_c + connect \B \q_int + connect \Y $15 + end + process $group_3 + assign \qlq_wr1_c 4'0000 + assign \qlq_wr1_c $15 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.dm3" +module \dm3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39" + wire width 4 output 0 \rd_wait_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40" + wire width 4 output 1 \wr_wait_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21" + wire width 4 input 2 \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36" + wire width 4 input 3 \go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27" + wire width 4 input 4 \gord1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27" + wire width 4 input 5 \gord2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27" + wire width 4 input 6 \gord3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31" + wire width 4 input 7 \gowr1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31" + wire width 4 input 8 \gowr2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19" + wire width 4 input 9 \rd_pend_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20" + wire width 4 input 10 \wr_pend_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 11 \rst + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526" + wire width 1 input 12 \clk + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src1_c_r_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 \src1_c_s_rd0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \src1_c_qlq_rd0_c + cell \src1_c$11 \src1_c + connect \rst \rst + connect \clk \clk + connect \r_rd0_c \src1_c_r_rd0_c + connect \s_rd0_c \src1_c_s_rd0_c + connect \qlq_rd0_c \src1_c_qlq_rd0_c + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src2_c_r_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 \src2_c_s_rd1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \src2_c_qlq_rd1_c + cell \src2_c$12 \src2_c + connect \rst \rst + connect \clk \clk + connect \r_rd1_c \src2_c_r_rd1_c + connect \s_rd1_c \src2_c_s_rd1_c + connect \qlq_rd1_c \src2_c_qlq_rd1_c + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \src3_c_r_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 \src3_c_s_rd2_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \src3_c_qlq_rd2_c + cell \src3_c$13 \src3_c + connect \rst \rst + connect \clk \clk + connect \r_rd2_c \src3_c_r_rd2_c + connect \s_rd2_c \src3_c_s_rd2_c + connect \qlq_rd2_c \src3_c_qlq_rd2_c + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \dst1_c_r_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 \dst1_c_s_wr0_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \dst1_c_qlq_wr0_c + cell \dst1_c$14 \dst1_c + connect \rst \rst + connect \clk \clk + connect \r_wr0_c \dst1_c_r_wr0_c + connect \s_wr0_c \dst1_c_s_wr0_c + connect \qlq_wr0_c \dst1_c_qlq_wr0_c + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 \dst2_c_r_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:57" + wire width 4 \dst2_c_s_wr1_c + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \dst2_c_qlq_wr1_c + cell \dst2_c$15 \dst2_c + connect \rst \rst + connect \clk \clk + connect \r_wr1_c \dst2_c_r_wr1_c + connect \s_wr1_c \dst2_c_s_wr1_c + connect \qlq_wr1_c \dst2_c_qlq_wr1_c + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61" + wire width 4 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61" + cell $or $2 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \gowr1_i + connect \B \go_die_i + connect \Y $1 + end + process $group_0 + assign \dst1_c_r_wr0_c 4'1111 + assign \dst1_c_r_wr0_c $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + wire width 5 $3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + wire width 4 $4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + cell $and $5 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \B \wr_pend_i + connect \Y $4 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + wire width 5 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + cell $and $7 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'101 + connect \A $4 + connect \B 4'0111 + connect \Y $6 + end + connect $3 $6 + process $group_1 + assign \dst1_c_s_wr0_c 4'0000 + assign \dst1_c_s_wr0_c $3 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61" + wire width 4 $8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:61" + cell $or $9 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \gowr2_i + connect \B \go_die_i + connect \Y $8 + end + process $group_2 + assign \dst2_c_r_wr1_c 4'1111 + assign \dst2_c_r_wr1_c $8 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + wire width 5 $10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + wire width 4 $11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + cell $and $12 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \B \wr_pend_i + connect \Y $11 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + wire width 5 $13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:62" + cell $and $14 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'101 + connect \A $11 + connect \B 4'0111 + connect \Y $13 + end + connect $10 $13 + process $group_3 + assign \dst2_c_s_wr1_c 4'0000 + assign \dst2_c_s_wr1_c $10 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66" + wire width 4 $15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66" + cell $or $16 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \gord1_i + connect \B \go_die_i + connect \Y $15 + end + process $group_4 + assign \src1_c_r_rd0_c 4'1111 + assign \src1_c_r_rd0_c $15 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 5 $17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 4 $18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + cell $and $19 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \B \rd_pend_i + connect \Y $18 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 5 $20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + cell $and $21 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'101 + connect \A $18 + connect \B 4'0111 + connect \Y $20 + end + connect $17 $20 + process $group_5 + assign \src1_c_s_rd0_c 4'0000 + assign \src1_c_s_rd0_c $17 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66" + wire width 4 $22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66" + cell $or $23 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \gord2_i + connect \B \go_die_i + connect \Y $22 + end + process $group_6 + assign \src2_c_r_rd1_c 4'1111 + assign \src2_c_r_rd1_c $22 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 5 $24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 4 $25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + cell $and $26 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \B \rd_pend_i + connect \Y $25 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 5 $27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + cell $and $28 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'101 + connect \A $25 + connect \B 4'0111 + connect \Y $27 + end + connect $24 $27 + process $group_7 + assign \src2_c_s_rd1_c 4'0000 + assign \src2_c_s_rd1_c $24 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66" + wire width 4 $29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:66" + cell $or $30 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \gord3_i + connect \B \go_die_i + connect \Y $29 + end + process $group_8 + assign \src3_c_r_rd2_c 4'1111 + assign \src3_c_r_rd2_c $29 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 5 $31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 4 $32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + cell $and $33 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \B \rd_pend_i + connect \Y $32 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + wire width 5 $34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:67" + cell $and $35 + parameter \A_SIGNED 1'1 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'1 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'101 + connect \A $32 + connect \B 4'0111 + connect \Y $34 + end + connect $31 $34 + process $group_9 + assign \src3_c_s_rd2_c 4'0000 + assign \src3_c_s_rd2_c $31 [3:0] + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + wire width 4 $36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + cell $or $37 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \src1_c_qlq_rd0_c + connect \B \src2_c_qlq_rd1_c + connect \Y $36 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + wire width 4 $38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + cell $or $39 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $36 + connect \B \src3_c_qlq_rd2_c + connect \Y $38 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + wire width 4 $40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + cell $not $41 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \Y $40 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + wire width 4 $42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:74" + cell $and $43 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $38 + connect \B $40 + connect \Y $42 + end + process $group_10 + assign \rd_wait_o 4'0000 + assign \rd_wait_o $42 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78" + wire width 4 $44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78" + cell $or $45 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \dst1_c_qlq_wr0_c + connect \B \dst2_c_qlq_wr1_c + connect \Y $44 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78" + wire width 4 $46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78" + cell $not $47 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A \issue_i + connect \Y $46 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78" + wire width 4 $48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:78" + cell $and $49 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \B_SIGNED 1'0 + parameter \B_WIDTH 3'100 + parameter \Y_WIDTH 3'100 + connect \A $44 + connect \B $46 + connect \Y $48 + end + process $group_11 + assign \wr_wait_o 4'0000 + assign \wr_wait_o $48 + sync init + end +end +attribute \generator "nMigen" attribute \nmigen.hierarchy "top.fur_x0" module \fur_x0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13" @@ -3531,9 +4706,9 @@ module \fur_x0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" wire width 1 output 1 \writable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" - wire width 3 input 2 \rd_pend_i + wire width 4 input 2 \rd_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" - wire width 3 input 3 \wr_pend_i + wire width 4 input 3 \wr_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" wire width 1 $1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" @@ -3541,7 +4716,7 @@ module \fur_x0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" cell $reduce_bool $3 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 + parameter \A_WIDTH 3'100 parameter \Y_WIDTH 1'1 connect \A \wr_pend_i connect \Y $2 @@ -3566,7 +4741,7 @@ module \fur_x0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" cell $reduce_bool $7 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 + parameter \A_WIDTH 3'100 parameter \Y_WIDTH 1'1 connect \A \rd_pend_i connect \Y $6 @@ -3593,9 +4768,71 @@ module \fur_x1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" wire width 1 output 1 \writable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" - wire width 3 input 2 \rd_pend_i + wire width 4 input 2 \rd_pend_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" + wire width 4 input 3 \wr_pend_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" + wire width 1 $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" + wire width 1 $2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" + cell $reduce_bool $3 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 1'1 + connect \A \wr_pend_i + connect \Y $2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" + cell $not $4 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $2 + connect \Y $1 + end + process $group_0 + assign \readable_o 1'0 + assign \readable_o $1 + sync init + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" + wire width 1 $5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" + wire width 1 $6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" + cell $reduce_bool $7 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 3'100 + parameter \Y_WIDTH 1'1 + connect \A \rd_pend_i + connect \Y $6 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" + cell $not $8 + parameter \A_SIGNED 1'0 + parameter \A_WIDTH 1'1 + parameter \Y_WIDTH 1'1 + connect \A $6 + connect \Y $5 + end + process $group_1 + assign \writable_o 1'0 + assign \writable_o $5 + sync init + end +end +attribute \generator "nMigen" +attribute \nmigen.hierarchy "top.fur_x2" +module \fur_x2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13" + wire width 1 output 0 \readable_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" + wire width 1 output 1 \writable_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" + wire width 4 input 2 \rd_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" - wire width 3 input 3 \wr_pend_i + wire width 4 input 3 \wr_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" wire width 1 $1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" @@ -3603,7 +4840,7 @@ module \fur_x1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" cell $reduce_bool $3 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 + parameter \A_WIDTH 3'100 parameter \Y_WIDTH 1'1 connect \A \wr_pend_i connect \Y $2 @@ -3628,7 +4865,7 @@ module \fur_x1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" cell $reduce_bool $7 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 + parameter \A_WIDTH 3'100 parameter \Y_WIDTH 1'1 connect \A \rd_pend_i connect \Y $6 @@ -3648,16 +4885,16 @@ module \fur_x1 end end attribute \generator "nMigen" -attribute \nmigen.hierarchy "top.fur_x2" -module \fur_x2 +attribute \nmigen.hierarchy "top.fur_x3" +module \fur_x3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13" wire width 1 output 0 \readable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" wire width 1 output 1 \writable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" - wire width 3 input 2 \rd_pend_i + wire width 4 input 2 \rd_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" - wire width 3 input 3 \wr_pend_i + wire width 4 input 3 \wr_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" wire width 1 $1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" @@ -3665,7 +4902,7 @@ module \fur_x2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:20" cell $reduce_bool $3 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 + parameter \A_WIDTH 3'100 parameter \Y_WIDTH 1'1 connect \A \wr_pend_i connect \Y $2 @@ -3690,7 +4927,7 @@ module \fur_x2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:23" cell $reduce_bool $7 parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 + parameter \A_WIDTH 3'100 parameter \Y_WIDTH 1'1 connect \A \rd_pend_i connect \Y $6 @@ -3714,23 +4951,23 @@ attribute \top 1 attribute \nmigen.hierarchy "top" module \top attribute \src "scoremulti/fu_fu_matrix.py:23" - wire width 3 input 0 \rd_pend_i + wire width 4 input 0 \rd_pend_i attribute \src "scoremulti/fu_fu_matrix.py:24" - wire width 3 input 1 \wr_pend_i + wire width 4 input 1 \wr_pend_i attribute \src "scoremulti/fu_fu_matrix.py:25" wire width 4 input 2 \issue_i attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 3 input 3 \gowr1_i + wire width 4 input 3 \gowr1_i attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 3 input 4 \gowr2_i + wire width 4 input 4 \gowr2_i attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 3 input 5 \gowr3_i + wire width 4 input 5 \gowr3_i attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 3 input 6 \gord1_i + wire width 4 input 6 \gord1_i attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 3 input 7 \gord2_i + wire width 4 input 7 \gord2_i attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 3 input 8 \gord3_i + wire width 4 input 8 \gord3_i attribute \src "scoremulti/fu_fu_matrix.py:42" wire width 4 output 9 \readable_o attribute \src "scoremulti/fu_fu_matrix.py:43" @@ -3850,14 +5087,51 @@ module \top connect \rst \rst connect \clk \clk end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:39" + wire width 4 \dm3_rd_wait_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:40" + wire width 4 \dm3_wr_wait_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:21" + wire width 4 \dm3_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:36" + wire width 4 \dm3_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27" + wire width 4 \dm3_gord1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27" + wire width 4 \dm3_gord2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:27" + wire width 4 \dm3_gord3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31" + wire width 4 \dm3_gowr1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:31" + wire width 4 \dm3_gowr2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:19" + wire width 4 \dm3_rd_pend_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoremulti/fu_dep_cell.py:20" + wire width 4 \dm3_wr_pend_i + cell \dm3 \dm3 + connect \rd_wait_o \dm3_rd_wait_o + connect \wr_wait_o \dm3_wr_wait_o + connect \issue_i \dm3_issue_i + connect \go_die_i \dm3_go_die_i + connect \gord1_i \dm3_gord1_i + connect \gord2_i \dm3_gord2_i + connect \gord3_i \dm3_gord3_i + connect \gowr1_i \dm3_gowr1_i + connect \gowr2_i \dm3_gowr2_i + connect \rd_pend_i \dm3_rd_pend_i + connect \wr_pend_i \dm3_wr_pend_i + connect \rst \rst + connect \clk \clk + end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13" wire width 1 \fur_x0_readable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" wire width 1 \fur_x0_writable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" - wire width 3 \fur_x0_rd_pend_i + wire width 4 \fur_x0_rd_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" - wire width 3 \fur_x0_wr_pend_i + wire width 4 \fur_x0_wr_pend_i cell \fur_x0 \fur_x0 connect \readable_o \fur_x0_readable_o connect \writable_o \fur_x0_writable_o @@ -3869,9 +5143,9 @@ module \top attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" wire width 1 \fur_x1_writable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" - wire width 3 \fur_x1_rd_pend_i + wire width 4 \fur_x1_rd_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" - wire width 3 \fur_x1_wr_pend_i + wire width 4 \fur_x1_wr_pend_i cell \fur_x1 \fur_x1 connect \readable_o \fur_x1_readable_o connect \writable_o \fur_x1_writable_o @@ -3883,446 +5157,251 @@ module \top attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" wire width 1 \fur_x2_writable_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" - wire width 3 \fur_x2_rd_pend_i + wire width 4 \fur_x2_rd_pend_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" - wire width 3 \fur_x2_wr_pend_i + wire width 4 \fur_x2_wr_pend_i cell \fur_x2 \fur_x2 connect \readable_o \fur_x2_readable_o connect \writable_o \fur_x2_writable_o connect \rd_pend_i \fur_x2_rd_pend_i connect \wr_pend_i \fur_x2_wr_pend_i end - attribute \src "scoremulti/fu_fu_matrix.py:75" - wire width 4 $1 - attribute \src "scoremulti/fu_fu_matrix.py:75" - cell $pos $2 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A { \fur_x2_readable_o \fur_x1_readable_o \fur_x0_readable_o } - connect \Y $1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:13" + wire width 1 \fur_x3_readable_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:14" + wire width 1 \fur_x3_writable_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:10" + wire width 4 \fur_x3_rd_pend_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/fu_picker_vec.py:11" + wire width 4 \fur_x3_wr_pend_i + cell \fur_x3 \fur_x3 + connect \readable_o \fur_x3_readable_o + connect \writable_o \fur_x3_writable_o + connect \rd_pend_i \fur_x3_rd_pend_i + connect \wr_pend_i \fur_x3_wr_pend_i end process $group_0 assign \readable_o 4'0000 - assign \readable_o $1 + assign \readable_o { \fur_x3_readable_o \fur_x2_readable_o \fur_x1_readable_o \fur_x0_readable_o } sync init end - attribute \src "scoremulti/fu_fu_matrix.py:76" - wire width 4 $3 - attribute \src "scoremulti/fu_fu_matrix.py:76" - cell $pos $4 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A { \fur_x2_writable_o \fur_x1_writable_o \fur_x0_writable_o } - connect \Y $3 - end process $group_1 assign \writable_o 4'0000 - assign \writable_o $3 + assign \writable_o { \fur_x3_writable_o \fur_x2_writable_o \fur_x1_writable_o \fur_x0_writable_o } sync init end process $group_2 - assign \fur_x0_rd_pend_i 3'000 - assign \fur_x0_rd_pend_i \dm0_rd_wait_o [2:0] + assign \fur_x0_rd_pend_i 4'0000 + assign \fur_x0_rd_pend_i \dm0_rd_wait_o sync init end process $group_3 - assign \fur_x0_wr_pend_i 3'000 - assign \fur_x0_wr_pend_i \dm0_wr_wait_o [2:0] + assign \fur_x0_wr_pend_i 4'0000 + assign \fur_x0_wr_pend_i \dm0_wr_wait_o sync init end process $group_4 - assign \fur_x1_rd_pend_i 3'000 - assign \fur_x1_rd_pend_i \dm1_rd_wait_o [2:0] + assign \fur_x1_rd_pend_i 4'0000 + assign \fur_x1_rd_pend_i \dm1_rd_wait_o sync init end process $group_5 - assign \fur_x1_wr_pend_i 3'000 - assign \fur_x1_wr_pend_i \dm1_wr_wait_o [2:0] + assign \fur_x1_wr_pend_i 4'0000 + assign \fur_x1_wr_pend_i \dm1_wr_wait_o sync init end process $group_6 - assign \fur_x2_rd_pend_i 3'000 - assign \fur_x2_rd_pend_i \dm2_rd_wait_o [2:0] + assign \fur_x2_rd_pend_i 4'0000 + assign \fur_x2_rd_pend_i \dm2_rd_wait_o sync init end process $group_7 - assign \fur_x2_wr_pend_i 3'000 - assign \fur_x2_wr_pend_i \dm2_wr_wait_o [2:0] + assign \fur_x2_wr_pend_i 4'0000 + assign \fur_x2_wr_pend_i \dm2_wr_wait_o sync init end process $group_8 + assign \fur_x3_rd_pend_i 4'0000 + assign \fur_x3_rd_pend_i \dm3_rd_wait_o + sync init + end + process $group_9 + assign \fur_x3_wr_pend_i 4'0000 + assign \fur_x3_wr_pend_i \dm3_wr_wait_o + sync init + end + process $group_10 assign \dm0_issue_i 4'0000 assign \dm1_issue_i 4'0000 assign \dm2_issue_i 4'0000 - assign { \dm2_issue_i [0] \dm1_issue_i [0] \dm0_issue_i [0] } \issue_i [2:0] - assign { \dm2_issue_i [1] \dm1_issue_i [1] \dm0_issue_i [1] } \issue_i [2:0] - assign { \dm2_issue_i [2] \dm1_issue_i [2] \dm0_issue_i [2] } \issue_i [2:0] - assign { \dm2_issue_i [3] \dm1_issue_i [3] \dm0_issue_i [3] } \issue_i [2:0] + assign \dm3_issue_i 4'0000 + assign { \dm3_issue_i [0] \dm2_issue_i [0] \dm1_issue_i [0] \dm0_issue_i [0] } \issue_i + assign { \dm3_issue_i [1] \dm2_issue_i [1] \dm1_issue_i [1] \dm0_issue_i [1] } \issue_i + assign { \dm3_issue_i [2] \dm2_issue_i [2] \dm1_issue_i [2] \dm0_issue_i [2] } \issue_i + assign { \dm3_issue_i [3] \dm2_issue_i [3] \dm1_issue_i [3] \dm0_issue_i [3] } \issue_i sync init end attribute \src "scoremulti/fu_fu_matrix.py:27" - wire width 4 $5 - attribute \src "scoremulti/fu_fu_matrix.py:27" - wire width 3 \go_die_i - attribute \src "scoremulti/fu_fu_matrix.py:27" - cell $pos $6 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \go_die_i - connect \Y $5 - end - process $group_11 + wire width 4 \go_die_i + process $group_14 assign \dm0_go_die_i 4'0000 - assign \dm0_go_die_i $5 + assign \dm0_go_die_i \go_die_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $7 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $8 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord1_i - connect \Y $7 - end - process $group_12 + process $group_15 assign \dm0_gord1_i 4'0000 - assign \dm0_gord1_i $7 + assign \dm0_gord1_i \gord1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $9 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $10 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord2_i - connect \Y $9 - end - process $group_13 + process $group_16 assign \dm0_gord2_i 4'0000 - assign \dm0_gord2_i $9 + assign \dm0_gord2_i \gord2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $11 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $12 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord3_i - connect \Y $11 - end - process $group_14 + process $group_17 assign \dm0_gord3_i 4'0000 - assign \dm0_gord3_i $11 + assign \dm0_gord3_i \gord3_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 4 $13 - attribute \src "scoremulti/fu_fu_matrix.py:36" - cell $pos $14 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gowr1_i - connect \Y $13 - end - process $group_15 + process $group_18 assign \dm0_gowr1_i 4'0000 - assign \dm0_gowr1_i $13 + assign \dm0_gowr1_i \gowr1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 4 $15 - attribute \src "scoremulti/fu_fu_matrix.py:36" - cell $pos $16 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gowr2_i - connect \Y $15 - end - process $group_16 + process $group_19 assign \dm0_gowr2_i 4'0000 - assign \dm0_gowr2_i $15 + assign \dm0_gowr2_i \gowr2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:27" - wire width 4 $17 - attribute \src "scoremulti/fu_fu_matrix.py:27" - cell $pos $18 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \go_die_i - connect \Y $17 - end - process $group_17 + process $group_20 assign \dm1_go_die_i 4'0000 - assign \dm1_go_die_i $17 + assign \dm1_go_die_i \go_die_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $19 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $20 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord1_i - connect \Y $19 - end - process $group_18 + process $group_21 assign \dm1_gord1_i 4'0000 - assign \dm1_gord1_i $19 + assign \dm1_gord1_i \gord1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $21 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $22 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord2_i - connect \Y $21 - end - process $group_19 + process $group_22 assign \dm1_gord2_i 4'0000 - assign \dm1_gord2_i $21 + assign \dm1_gord2_i \gord2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $23 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $24 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord3_i - connect \Y $23 - end - process $group_20 + process $group_23 assign \dm1_gord3_i 4'0000 - assign \dm1_gord3_i $23 + assign \dm1_gord3_i \gord3_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 4 $25 - attribute \src "scoremulti/fu_fu_matrix.py:36" - cell $pos $26 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gowr1_i - connect \Y $25 - end - process $group_21 + process $group_24 assign \dm1_gowr1_i 4'0000 - assign \dm1_gowr1_i $25 + assign \dm1_gowr1_i \gowr1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 4 $27 - attribute \src "scoremulti/fu_fu_matrix.py:36" - cell $pos $28 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gowr2_i - connect \Y $27 - end - process $group_22 + process $group_25 assign \dm1_gowr2_i 4'0000 - assign \dm1_gowr2_i $27 + assign \dm1_gowr2_i \gowr2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:27" - wire width 4 $29 - attribute \src "scoremulti/fu_fu_matrix.py:27" - cell $pos $30 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \go_die_i - connect \Y $29 - end - process $group_23 + process $group_26 assign \dm2_go_die_i 4'0000 - assign \dm2_go_die_i $29 + assign \dm2_go_die_i \go_die_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $31 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $32 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord1_i - connect \Y $31 - end - process $group_24 + process $group_27 assign \dm2_gord1_i 4'0000 - assign \dm2_gord1_i $31 + assign \dm2_gord1_i \gord1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $33 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $34 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord2_i - connect \Y $33 - end - process $group_25 + process $group_28 assign \dm2_gord2_i 4'0000 - assign \dm2_gord2_i $33 + assign \dm2_gord2_i \gord2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:32" - wire width 4 $35 - attribute \src "scoremulti/fu_fu_matrix.py:32" - cell $pos $36 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gord3_i - connect \Y $35 - end - process $group_26 + process $group_29 assign \dm2_gord3_i 4'0000 - assign \dm2_gord3_i $35 + assign \dm2_gord3_i \gord3_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 4 $37 - attribute \src "scoremulti/fu_fu_matrix.py:36" - cell $pos $38 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gowr1_i - connect \Y $37 - end - process $group_27 + process $group_30 assign \dm2_gowr1_i 4'0000 - assign \dm2_gowr1_i $37 + assign \dm2_gowr1_i \gowr1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:36" - wire width 4 $39 - attribute \src "scoremulti/fu_fu_matrix.py:36" - cell $pos $40 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \gowr2_i - connect \Y $39 - end - process $group_28 + process $group_31 assign \dm2_gowr2_i 4'0000 - assign \dm2_gowr2_i $39 + assign \dm2_gowr2_i \gowr2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:23" - wire width 4 $41 - attribute \src "scoremulti/fu_fu_matrix.py:23" - cell $pos $42 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \rd_pend_i - connect \Y $41 + process $group_32 + assign \dm3_go_die_i 4'0000 + assign \dm3_go_die_i \go_die_i + sync init end - process $group_29 - assign \dm0_rd_pend_i 4'0000 - assign \dm0_rd_pend_i $41 + process $group_33 + assign \dm3_gord1_i 4'0000 + assign \dm3_gord1_i \gord1_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:24" - wire width 4 $43 - attribute \src "scoremulti/fu_fu_matrix.py:24" - cell $pos $44 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \wr_pend_i - connect \Y $43 + process $group_34 + assign \dm3_gord2_i 4'0000 + assign \dm3_gord2_i \gord2_i + sync init end - process $group_30 - assign \dm0_wr_pend_i 4'0000 - assign \dm0_wr_pend_i $43 + process $group_35 + assign \dm3_gord3_i 4'0000 + assign \dm3_gord3_i \gord3_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:23" - wire width 4 $45 - attribute \src "scoremulti/fu_fu_matrix.py:23" - cell $pos $46 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \rd_pend_i - connect \Y $45 + process $group_36 + assign \dm3_gowr1_i 4'0000 + assign \dm3_gowr1_i \gowr1_i + sync init end - process $group_31 - assign \dm1_rd_pend_i 4'0000 - assign \dm1_rd_pend_i $45 + process $group_37 + assign \dm3_gowr2_i 4'0000 + assign \dm3_gowr2_i \gowr2_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:24" - wire width 4 $47 - attribute \src "scoremulti/fu_fu_matrix.py:24" - cell $pos $48 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \wr_pend_i - connect \Y $47 + process $group_38 + assign \dm0_rd_pend_i 4'0000 + assign \dm0_rd_pend_i \rd_pend_i + sync init end - process $group_32 - assign \dm1_wr_pend_i 4'0000 - assign \dm1_wr_pend_i $47 + process $group_39 + assign \dm0_wr_pend_i 4'0000 + assign \dm0_wr_pend_i \wr_pend_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:23" - wire width 4 $49 - attribute \src "scoremulti/fu_fu_matrix.py:23" - cell $pos $50 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \rd_pend_i - connect \Y $49 + process $group_40 + assign \dm1_rd_pend_i 4'0000 + assign \dm1_rd_pend_i \rd_pend_i + sync init end - process $group_33 - assign \dm2_rd_pend_i 4'0000 - assign \dm2_rd_pend_i $49 + process $group_41 + assign \dm1_wr_pend_i 4'0000 + assign \dm1_wr_pend_i \wr_pend_i sync init end - attribute \src "scoremulti/fu_fu_matrix.py:24" - wire width 4 $51 - attribute \src "scoremulti/fu_fu_matrix.py:24" - cell $pos $52 - parameter \A_SIGNED 1'0 - parameter \A_WIDTH 2'11 - parameter \Y_WIDTH 3'100 - connect \A \wr_pend_i - connect \Y $51 + process $group_42 + assign \dm2_rd_pend_i 4'0000 + assign \dm2_rd_pend_i \rd_pend_i + sync init end - process $group_34 + process $group_43 assign \dm2_wr_pend_i 4'0000 - assign \dm2_wr_pend_i $51 + assign \dm2_wr_pend_i \wr_pend_i + sync init + end + process $group_44 + assign \dm3_rd_pend_i 4'0000 + assign \dm3_rd_pend_i \rd_pend_i + sync init + end + process $group_45 + assign \dm3_wr_pend_i 4'0000 + assign \dm3_wr_pend_i \wr_pend_i sync init end - connect \go_die_i 3'000 + connect \go_die_i 4'0000 end -- 2.30.2