From c5bc59159fde31efc60641827db4e80bdeb9a48f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 14 Feb 2022 14:03:11 +0000 Subject: [PATCH] add external cpu --- Makefile | 1 + src/ls2.py | 30 ++++++++++++++++++++++-------- verilator/microwatt-verilator.cpp | 4 ++-- 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index c60893b..7baa465 100644 --- a/Makefile +++ b/Makefile @@ -60,6 +60,7 @@ microwatt-verilator: ls2.v \ --assert \ --top-module top \ --cc ls2.v \ + --cc ../soc/src/soc/external_core_top.v \ --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \ -o $@ -I../uart16550/rtl/verilog \ -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT \ diff --git a/src/ls2.py b/src/ls2.py index b93e290..23a1d77 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -12,6 +12,7 @@ from nmigen.cli import verilog from nmigen.lib.cdc import ResetSynchronizer from nmigen_soc import wishbone, memory from nmigen_soc.memory import MemoryMap + from nmigen_stdio.serial import AsyncSerial from lambdasoc.cpu.minerva import MinervaCPU @@ -21,6 +22,8 @@ from lambdasoc.periph.timer import TimerPeripheral from lambdasoc.periph import Peripheral from lambdasoc.soc.base import SoC from soc.bus.uart_16550 import UART16550 # opencores 16550 uart +from soc.bus.external_core import ExternalCore # external libresoc/microwatt +from soc.bus.wb_downconvert import WishboneDownConvert from gram.core import gramCore from gram.phy.ecp5ddrphy import ECP5DDRPHY @@ -62,12 +65,19 @@ class DDR3SoC(SoC, Elaboratable): # set up clock request generator self.crg = ECPIX5CRG() - # set up CPU, and interrupt interface - if False: - self.cpu = MinervaCPU(reset_address=0) - self._arbiter.add(self.cpu.ibus) # I-Cache Master - self._arbiter.add(self.cpu.dbus) # D-Cache Master. TODO JTAG master - self.intc = GenericInterruptController(width=len(self.cpu.ip)) + # set up CPU, with 64-to-32-bit downconverters + self.cpu = ExternalCore(name="ext_core") + cvtdbus = wishbone.Interface(addr_width=30, data_width=32, + features={'stall'}, granularity=8) + cvtibus = wishbone.Interface(addr_width=30, data_width=32, + features={'stall'}, granularity=8) + self.dbusdowncvt = WishboneDownConvert(self.cpu.dbus, cvtdbus) + self.ibusdowncvt = WishboneDownConvert(self.cpu.ibus, cvtibus) + self._arbiter.add(cvtibus) # I-Cache Master + self._arbiter.add(cvtdbus) # D-Cache Master. TODO JTAG master + + # CPU interrupt controller + self.intc = GenericInterruptController(width=len(self.cpu.irq)) # SRAM (but actually a ROM, for firmware), at address 0x0 if fw_addr is not None: @@ -137,6 +147,10 @@ class DDR3SoC(SoC, Elaboratable): m.submodules.ddrphy = self.ddrphy m.submodules.dramcore = self.dramcore m.submodules.drambone = self.drambone + if hasattr(self, "cpu"): + m.submodules.extcore = self.cpu + m.submodules.dbuscvt = self.dbusdowncvt + m.submodules.ibuscvt = self.ibusdowncvt # add blinky lights so we know FPGA is alive if platform is not None: @@ -146,9 +160,9 @@ class DDR3SoC(SoC, Elaboratable): # to the decoder (addressing wishbone slaves) comb += self._arbiter.bus.connect(self._decoder.bus) - if False: + if hasattr(self, "cpu"): # wire up the CPU interrupts - comb += self.cpu.ip.eq(self.intc.ip) + comb += self.cpu.irq.eq(self.intc.ip) # add uart16550 verilog source. assumes a directory # structure where ls2 has been checked out in a common diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp index 1bf1dde..cf85222 100644 --- a/verilator/microwatt-verilator.cpp +++ b/verilator/microwatt-verilator.cpp @@ -65,10 +65,10 @@ int main(int argc, char **argv) #endif // Reset - top->rst = 0; + top->rst = 1; for (unsigned long i = 0; i < 5; i++) tick(top); - top->rst = 1; + top->rst = 0; while(!Verilated::gotFinish()) { tick(top); -- 2.30.2