From c5ca14debbb217b519b0485ce088bce340418e80 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 4 May 2020 18:28:56 +0100
Subject: [PATCH]

---
 3d_gpu/architecture/memory_and_cache.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn
index 19695e3d9..a9f0910f9 100644
--- a/3d_gpu/architecture/memory_and_cache.mdwn
+++ b/3d_gpu/architecture/memory_and_cache.mdwn
@@ -70,6 +70,10 @@ ST:
 * in: st_data
 * in: go_st (raised for 1 cycle, must complete)
 
+Source: PortInterface
+
+* <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/l0_cache.py;h=22168267b64d557ff3cc61c597505188bc2985db;hb=HEAD>
+
 ## Alternative Design Idea
 
 [[alternative-design-idea]]
-- 
2.30.2