From c5dd5a0cc4a601ab68832049fa7ae9c0b501812f Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 15:57:12 +0100
Subject: [PATCH]

---
 openpower/sv/vector_ops.mdwn | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index f61d11864..86f219a10 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -52,7 +52,7 @@ Idea 1: implement this as a Triangular Schedule, Vertical-First Mode,
 secpnd on src2.
 
 Idea 2: implement using outer loop on varying setvl Horizontal-First
-with `1<<r3` predicate mask for src2 as scalar, creates CR field vector, transfer into INT with mfcrweird then OR into
+with `1<<r3` predicate mask for src2 as scalar, creates CR field vector, transfer into INT with mfcrweird then OR into the
 result.
 
     li r3, 1
@@ -62,9 +62,16 @@ result.
         sv.addi/sm=1<<r3 t0, src1.v, 0 # copy src1[i]
         sv.cmpi src2.v, t0 # compare src2 vector to scalar
         mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
+        srr t1, t1, i # shift up by i before ORing
         or result, result, t1
         srr r3, r3, 1 # shift r3 predicate up by one
 
+See [[sv/cr_int_predication]] for full details on the crweird instructions:
+the primary important aspect here is that a Vector of CR Field's EQ bits is
+transferred into a single GPR.  The secondary important aspect is that VL
+is being adjusted in each loop, testing successively more of the input
+vector against a given scalar, each time.
+
 To investigate:
 
 * <https://stackoverflow.com/questions/39266476/how-to-speed-up-this-histogram-of-lut-lookups>
-- 
2.30.2