From c5e68f0aea252654ca196574b5396a23036f3f2d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Jun 2020 00:35:48 +0100 Subject: [PATCH] more whitespace cleanup --- nmigen_soc/csr/bus.py | 4 +- nmigen_soc/csr/wishbone.py | 8 +-- nmigen_soc/test/test_csr_bus.py | 6 +- nmigen_soc/wishbone/bus.py | 98 ++++++++++++++++++++------------- nmigen_soc/wishbone/sram.py | 3 +- 5 files changed, 73 insertions(+), 46 deletions(-) diff --git a/nmigen_soc/csr/bus.py b/nmigen_soc/csr/bus.py index 624c011..b865a01 100644 --- a/nmigen_soc/csr/bus.py +++ b/nmigen_soc/csr/bus.py @@ -147,8 +147,8 @@ class Interface(Record): def __init__(self, *, addr_width, data_width, alignment=0, name=None): if not isinstance(addr_width, int) or addr_width <= 0: - raise ValueError("Address width must be a positive integer, not {!r}" - .format(addr_width)) + raise ValueError("Address width must be a positive integer, " + "not {!r}" .format(addr_width)) if not isinstance(data_width, int) or data_width <= 0: raise ValueError("Data width must be a positive integer, not {!r}" .format(data_width)) diff --git a/nmigen_soc/csr/wishbone.py b/nmigen_soc/csr/wishbone.py index 9e89f49..a1767fc 100644 --- a/nmigen_soc/csr/wishbone.py +++ b/nmigen_soc/csr/wishbone.py @@ -38,11 +38,11 @@ class WishboneCSRBridge(Elaboratable): def __init__(self, csr_bus, *, data_width=None): if not isinstance(csr_bus, CSRInterface): - raise ValueError("CSR bus must be an instance of CSRInterface, not {!r}" - .format(csr_bus)) + raise ValueError("CSR bus must be an instance of CSRInterface, " + "not {!r}" .format(csr_bus)) if csr_bus.data_width not in (8, 16, 32, 64): - raise ValueError("CSR bus data width must be one of 8, 16, 32, 64, not {!r}" - .format(csr_bus.data_width)) + raise ValueError("CSR bus data width must be one of 8, 16, 32, 64, " + "not {!r}" .format(csr_bus.data_width)) if data_width is None: data_width = csr_bus.data_width diff --git a/nmigen_soc/test/test_csr_bus.py b/nmigen_soc/test/test_csr_bus.py index 83e9b7c..3d530c1 100644 --- a/nmigen_soc/test/test_csr_bus.py +++ b/nmigen_soc/test/test_csr_bus.py @@ -56,7 +56,8 @@ class ElementTestCase(unittest.TestCase): def test_access_wrong(self): with self.assertRaisesRegex(ValueError, - r"Access mode must be one of \"r\", \"w\", or \"rw\", not 'wo'"): + r"Access mode must be one of \"r\", \"w\", " + r"or \"rw\", not 'wo'"): Element(1, "wo") @@ -271,7 +272,8 @@ class DecoderTestCase(unittest.TestCase): def test_add_wrong_sub_bus(self): with self.assertRaisesRegex(TypeError, - r"Subordinate bus must be an instance of csr\.Interface, not 1"): + r"Subordinate bus must be an instance of " + r"csr\.Interface, not 1"): self.dut.add(1) def test_add_wrong_data_width(self): diff --git a/nmigen_soc/wishbone/bus.py b/nmigen_soc/wishbone/bus.py index 77421eb..ad6d2d3 100644 --- a/nmigen_soc/wishbone/bus.py +++ b/nmigen_soc/wishbone/bus.py @@ -108,28 +108,32 @@ class Interface(Record): or ``BTE_I`` (target). """ - def __init__(self, *, addr_width, data_width, granularity=None, features=frozenset(), + def __init__(self, *, addr_width, data_width, granularity=None, + features=None, alignment=0, name=None): + if features is None: + features = frozenset() if not isinstance(addr_width, int) or addr_width < 0: - raise ValueError("Address width must be a non-negative integer, not {!r}" - .format(addr_width)) + raise ValueError("Address width must be a non-negative integer, " + "not {!r}" .format(addr_width)) if data_width not in (8, 16, 32, 64): raise ValueError("Data width must be one of 8, 16, 32, 64, not {!r}" .format(data_width)) if granularity is None: granularity = data_width elif granularity not in (8, 16, 32, 64): - raise ValueError("Granularity must be one of 8, 16, 32, 64, not {!r}" - .format(granularity)) + raise ValueError("Granularity must be one of 8, 16, 32, 64, " + "not {!r}" .format(granularity)) if granularity > data_width: - raise ValueError("Granularity {} may not be greater than data width {}" - .format(granularity, data_width)) + raise ValueError("Granularity {} may not be greater than data " + "width {}" .format(granularity, data_width)) self.addr_width = addr_width self.data_width = data_width self.granularity = granularity granularity_bits = log2_int(data_width // granularity) self._alignment = alignment - self.memory_map = MemoryMap(addr_width=max(1, addr_width + granularity_bits), + self.memory_map = MemoryMap(addr_width=max(1, addr_width + + granularity_bits), data_width=data_width >> granularity_bits, alignment=alignment) @@ -165,7 +169,8 @@ class Interface(Record): @classmethod def from_pure_record(cls, record): - """Instantiate a :class:`wishbone.Interface` from a simple :class:`Record` + """Instantiate a :class:`wishbone.Interface` + from a simple :class:`Record` """ if not isinstance(record, Record): raise TypeError("{!r} is not a Record" @@ -174,10 +179,12 @@ class Interface(Record): if len(record.dat_w) != len(record.dat_r): raise AttributeError("Record {!r} has {}-bit long \"dat_w\" " "but {}-bit long \"dat_r\"" - .format(record, len(record.dat_w), len(record.dat_r))) + .format(record, len(record.dat_w), + len(record.dat_r))) data_width = len(record.dat_w) if data_width % len(record.sel) != 0: - raise AttributeError("Record {!r} has invalid granularity value because " + raise AttributeError("Record {!r} has invalid granularity " + "value because " "its data width is {}-bit long but " "its \"sel\" is {}-bit long" .format(record, data_width, len(record.sel))) @@ -248,27 +255,35 @@ class Decoder(Elaboratable): See :meth:`MemoryMap.add_resource` for details. """ if not isinstance(sub_bus, Interface): - raise TypeError("Subordinate bus must be an instance of wishbone.Interface, not {!r}" - .format(sub_bus)) + raise TypeError("Subordinate bus must be an instance of " + "wishbone.Interface, not {!r}" .format(sub_bus)) if sub_bus.granularity > self.bus.granularity: - raise ValueError("Subordinate bus has granularity {}, which is greater than the " + raise ValueError("Subordinate bus has granularity {}, " + "which is greater than the " "decoder granularity {}" .format(sub_bus.granularity, self.bus.granularity)) if not sparse: if sub_bus.data_width != self.bus.data_width: - raise ValueError("Subordinate bus has data width {}, which is not the same as " - "decoder data width {} (required for dense address translation)" - .format(sub_bus.data_width, self.bus.data_width)) + raise ValueError("Subordinate bus has data width {}, " + "which is not the same as " + "decoder data width {} " + "(required for dense address translation)" + .format(sub_bus.data_width, + self.bus.data_width)) else: if sub_bus.granularity != sub_bus.data_width: - raise ValueError("Subordinate bus has data width {}, which is not the same as " - "subordinate bus granularity {} (required for sparse address " + raise ValueError("Subordinate bus has data width {}, " + "which is not the same as " + "subordinate bus granularity {} " + "(required for sparse address " "translation)" - .format(sub_bus.data_width, sub_bus.granularity)) + .format(sub_bus.data_width, + sub_bus.granularity)) for opt_output in {"err", "rty", "stall"}: if hasattr(sub_bus, opt_output) and not hasattr( self.bus, opt_output): - raise ValueError("Subordinate bus has optional output {!r}, but the decoder " + raise ValueError("Subordinate bus has optional output " + "{!r}, but the decoder " "does not have a corresponding input" .format(opt_output)) @@ -300,12 +315,15 @@ class Decoder(Elaboratable): m.d.comb += sub_bus.lock.eq(getattr(self.bus, "lock", 0)) if hasattr(sub_bus, "cti"): m.d.comb += sub_bus.cti.eq(getattr(self.bus, - "cti", CycleType.CLASSIC)) + "cti", + CycleType.CLASSIC)) if hasattr(sub_bus, "bte"): m.d.comb += sub_bus.bte.eq(getattr(self.bus, - "bte", BurstTypeExt.LINEAR)) + "bte", + BurstTypeExt.LINEAR)) - with m.Case(sub_pat[:-log2_int(self.bus.data_width // self.bus.granularity)]): + with m.Case(sub_pat[:-log2_int(self.bus.data_width // + self.bus.granularity)]): m.d.comb += [ sub_bus.cyc.eq(self.bus.cyc), self.bus.dat_r.eq(sub_bus.dat_r), @@ -373,24 +391,28 @@ class Arbiter(Elaboratable): be greater than or equal to the granularity of the arbiter. """ if not isinstance(itor_bus, Interface): - raise TypeError("Initiator bus must be an instance of wishbone.Interface, not {!r}" - .format(itor_bus)) + raise TypeError("Initiator bus must be an instance of " + "wishbone.Interface, not {!r}".format(itor_bus)) if itor_bus.addr_width != self.bus.addr_width: - raise ValueError("Initiator bus has address width {}, which is not the same as " + raise ValueError("Initiator bus has address width {}, " + "which is not the same as " "arbiter address width {}" .format(itor_bus.addr_width, self.bus.addr_width)) if itor_bus.granularity < self.bus.granularity: - raise ValueError("Initiator bus has granularity {}, which is lesser than the " + raise ValueError("Initiator bus has granularity {}, " + "which is lesser than the " "arbiter granularity {}" .format(itor_bus.granularity, self.bus.granularity)) if itor_bus.data_width != self.bus.data_width: - raise ValueError("Initiator bus has data width {}, which is not the same as " + raise ValueError("Initiator bus has data width {}, " + "which is not the same as " "arbiter data width {}" .format(itor_bus.data_width, self.bus.data_width)) for opt_output in {"lock", "cti", "bte"}: if hasattr(itor_bus, opt_output) and not hasattr( self.bus, opt_output): - raise ValueError("Initiator bus has optional output {!r}, but the arbiter " + raise ValueError("Initiator bus has optional output {!r}, " + "but the arbiter " "does not have a corresponding input" .format(opt_output)) @@ -474,8 +496,8 @@ class InterconnectShared(Elaboratable): This instantiates the following components: (1) An arbiter (:class:`Arbiter`) controlling access of multiple MASTERs to the shared bus; and - (2) A decoder (:class:`Decoder`) specifying which targeted SLAVE is to be accessed - using address translation on the shared bus. + (2) A decoder (:class:`Decoder`) specifying which targeted SLAVE is + to be accessed using address translation on the shared bus. See Section 8.2.3 of Wishbone B4 for implemenation specifications. @@ -541,7 +563,8 @@ class InterconnectShared(Elaboratable): if name in kwargs: arbiter_kwargs[name] = kwargs[name] self.arbiter = Arbiter( - addr_width=self.addr_width, data_width=self.data_width, **arbiter_kwargs + addr_width=self.addr_width, data_width=self.data_width, + **arbiter_kwargs ) self.arbiter.bus.name = "arbiter_shared" for itor_bus in self._itors: @@ -551,9 +574,9 @@ class InterconnectShared(Elaboratable): for name in ["granularity", "features", "alignment"]: if name in kwargs: decoder_kwargs[name] = kwargs[name] - self.decoder = Decoder( - addr_width=self.addr_width, data_width=self.data_width, **decoder_kwargs - ) + self.decoder = Decoder(addr_width=self.addr_width, + data_width=self.data_width, + **decoder_kwargs) self.decoder.bus.name = "decoder_shared" for item in self._targets: if isinstance(item, Interface): @@ -562,7 +585,8 @@ class InterconnectShared(Elaboratable): self.decoder.add(item[0], addr=item[1]) else: raise TypeError("Target must be a Wishbone interface, " - "or a (Wishbone interface, start address) tuple, not {!r}" + "or a (Wishbone interface, " + "start address) tuple, not {!r}" .format(item)) def elaborate(self, platform): diff --git a/nmigen_soc/wishbone/sram.py b/nmigen_soc/wishbone/sram.py index c5a139d..ac5f12b 100644 --- a/nmigen_soc/wishbone/sram.py +++ b/nmigen_soc/wishbone/sram.py @@ -53,7 +53,8 @@ class SRAM(Elaboratable): self.memory = memory self.read_only = read_only if bus is None: - bus = Interface(addr_width=log2_int(self.memory.depth, need_pow2=False), + bus = Interface(addr_width=log2_int(self.memory.depth, + need_pow2=False), data_width=self.memory.width, granularity=granularity, features=features, -- 2.30.2