From c61230d443402a96e8145e702e711050fa1d4b8b Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 18 Sep 2022 14:22:29 +0100 Subject: [PATCH] --- openpower/sv/normal.mdwn | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index a5a271aae..34c1024ba 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -47,9 +47,7 @@ The Mode table for Arithmetic and Logical operations | 0-1 | 2 | 3 4 | description | | --- | --- |---------|-------------------------- | | 00 | 0 | dz sz | simple mode | -| 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 | -| 00 | 1 | SVM 0 | subvector reduce mode, SUBVL>1 | -| 00 | 1 | / 1 | reserved | +| 00 | 1 | 0 RG | scalar reduce mode (mapreduce) | | 01 | inv | CR-bit | Rc=1: ffirst CR sel | | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz | | 10 | N | dz sz | sat mode: N=0/1 u/s | @@ -63,7 +61,6 @@ Fields: * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) * **RG** inverts the Vector Loop order (VL-1 downto 0) rather than the normal 0..VL-1 -* **SVM** sets "subvector" reduce mode * **N** sets signed/unsigned saturation. * **RC1** as if Rc=1, stores CRs *but not the result* * **VLi** VL inclusive: in fail-first mode, the truncation of -- 2.30.2