From c632ea3b5094f5c43b679504402e0b17d7799497 Mon Sep 17 00:00:00 2001 From: Cole Poirier Date: Mon, 10 Aug 2020 09:10:51 -0700 Subject: [PATCH] Fix bug 450 comment 7 --- src/soc/experiment/mmu.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index d5cba5a2..e4779962 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -572,7 +572,7 @@ class AddrShifter(Elaboratable): # -- rts == radix tree size, # address bits being translated # rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5)); # rts == radix tree size, number of address bits being translated - comb += rts.eq((0 & pgtbl[61:63] & pgtbl[5:8]).as_unsigned()) + comb += rts.eq(((Cat(Const(0b0, 1) , Cat(pgtbl[61:63], pgtbl[5:8]))).as_unsigned()) # -- mbits == # address bits to index top level of tree # mbits := unsigned('0' & pgtbl(4 downto 0)); -- 2.30.2