From c663a3680b13422c568e3dc438e7b971b81a71c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 12:44:34 -0700 Subject: [PATCH] Remove stat --- tests/xilinx/mul_unsigned.ys | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 30c034afe..77990bd68 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -4,7 +4,6 @@ hierarchy -top mul_unsigned equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module -stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE -- 2.30.2