From c66bd3a38a109a6aaeb8649218610b71d155431c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Apr 2019 10:23:24 +0100
Subject: [PATCH] add new Elaboratable

---
 src/add/fadd_state.py            |  2 +-
 src/add/fmul.py                  |  2 +-
 src/add/function_unit.py         |  2 +-
 src/add/nmigen_div_experiment.py |  2 +-
 src/add/pipeline_example.py      |  8 ++++----
 src/add/queue.py                 |  4 ++--
 src/add/record_experiment.py     |  4 ++--
 src/add/rstation_row.py          |  2 +-
 src/add/singlepipe.py            | 22 +++++++++++-----------
 src/add/test_buf_pipe.py         | 26 +++++++++++++-------------
 src/add/test_div64.py            |  2 +-
 src/add/test_fpnum.py            |  2 +-
 src/add/test_multishift.py       |  8 ++++----
 13 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/src/add/fadd_state.py b/src/add/fadd_state.py
index 79a8723d..7ad88786 100644
--- a/src/add/fadd_state.py
+++ b/src/add/fadd_state.py
@@ -21,7 +21,7 @@ class FPADD(FPBase):
         self.in_b  = FPOp(width)
         self.out_z = FPOp(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPAdd
         """
         m = Module()
diff --git a/src/add/fmul.py b/src/add/fmul.py
index 31095134..a2ba41e7 100644
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -22,7 +22,7 @@ class FPMUL(FPBase):
         self.states.append(state)
         return state
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPMUL
         """
         m = Module()
diff --git a/src/add/function_unit.py b/src/add/function_unit.py
index 933a7fc4..108c84f3 100644
--- a/src/add/function_unit.py
+++ b/src/add/function_unit.py
@@ -25,7 +25,7 @@ class FunctionUnit:
             fus.append(rs)
         self.fus = Array(fus)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for ReservationStationRow
         """
         m = Module()
diff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py
index 5dccecb5..94ebc2fd 100644
--- a/src/add/nmigen_div_experiment.py
+++ b/src/add/nmigen_div_experiment.py
@@ -43,7 +43,7 @@ class FPDIV(FPBase):
         self.states.append(state)
         return state
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for FPDiv
         """
         m = Module()
diff --git a/src/add/pipeline_example.py b/src/add/pipeline_example.py
index c8d4c900..799caf6d 100644
--- a/src/add/pipeline_example.py
+++ b/src/add/pipeline_example.py
@@ -79,7 +79,7 @@ class PipeModule:
         self.m = Module()
         self.p = ObjectBasedPipelineExample(self.m)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         return self.m
 
 
@@ -88,7 +88,7 @@ class PipelineStageExample:
     def __init__(self):
         self._loopback = Signal(4, name="loopback")
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
 
@@ -116,7 +116,7 @@ class PipelineStageObjectExample:
     def __init__(self):
         self.loopback = Signal(4)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
 
@@ -165,7 +165,7 @@ class PipelineStageObjectExample2:
     def __init__(self):
         self._loopback = Signal(4)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
 
diff --git a/src/add/queue.py b/src/add/queue.py
index e52ab5e9..43dfa2ce 100644
--- a/src/add/queue.py
+++ b/src/add/queue.py
@@ -23,7 +23,7 @@
 # TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
 # MODIFICATIONS.
 
-from nmigen import Module, Signal, Memory, Mux
+from nmigen import Module, Signal, Memory, Mux, Elaboratable
 from nmigen.tools import bits_for
 from nmigen.cli import main
 from nmigen.lib.fifo import FIFOInterface
@@ -31,7 +31,7 @@ from nmigen.lib.fifo import FIFOInterface
 # translated from https://github.com/freechipsproject/chisel3/blob/a4a29e29c3f1eed18f851dcf10bdc845571dfcb6/src/main/scala/chisel3/util/Decoupled.scala#L185   # noqa
 
 
-class Queue(FIFOInterface):
+class Queue(FIFOInterface, Elaboratable):
     def __init__(self, width, depth, fwft=True, pipe=False):
         """ Queue (FIFO) with pipe mode and first-write fall-through capability
 
diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index 2cbc637a..1789c3bd 100644
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -1,4 +1,4 @@
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
 from nmigen.hdl.rec import Record, Layout, DIR_NONE
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
@@ -51,7 +51,7 @@ def testbench(dut):
 
 
 
-class RecordTest2:
+class RecordTest2(Elaboratable):
 
     def __init__(self):
         self.r1 = RecordObject()
diff --git a/src/add/rstation_row.py b/src/add/rstation_row.py
index 09f4991e..aeb58732 100644
--- a/src/add/rstation_row.py
+++ b/src/add/rstation_row.py
@@ -20,7 +20,7 @@ class ReservationStationRow:
         self.id_wid = id_wid
         self.out_z = Signal(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
         """ creates the HDL code-fragment for ReservationStationRow
         """
         m = Module()
diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 9b65f090..c6a2bd75 100644
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -168,7 +168,7 @@
     https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
 """
 
-from nmigen import Signal, Cat, Const, Mux, Module, Value
+from nmigen import Signal, Cat, Const, Mux, Module, Value, Elaboratable
 from nmigen.cli import verilog, rtlil
 from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
 from nmigen.hdl.ast import ArrayProxy
@@ -253,7 +253,7 @@ class RecordObject(Record):
         return list(self)
 
 
-class PrevControl:
+class PrevControl(Elaboratable):
     """ contains signals that come *from* the previous stage (both in and out)
         * i_valid: previous stage indicating all incoming data is valid.
                    may be a multi-bit signal, where all bits are required
@@ -332,7 +332,7 @@ class PrevControl:
         return list(self)
 
 
-class NextControl:
+class NextControl(Elaboratable):
     """ contains the signals that go *to* the next stage (both in and out)
         * o_valid: output indicating to next stage that data is valid
         * i_ready: input from next stage indicating that it can accept data
@@ -650,7 +650,7 @@ class StageChain(StageCls):
         return self.o # conform to Stage API: return last-loop output
 
 
-class ControlBase:
+class ControlBase(Elaboratable):
     """ Common functions for Pipeline API
     """
     def __init__(self, stage=None, in_multi=None, stage_ctl=False):
@@ -759,7 +759,7 @@ class ControlBase:
     def ports(self):
         return list(self)
 
-    def _elaborate(self, platform):
+    def elaborate(self, platform):
         """ handles case where stage has dynamic ready/valid functions
         """
         m = Module()
@@ -813,7 +813,7 @@ class BufferedHandshake(ControlBase):
     """
 
     def elaborate(self, platform):
-        self.m = ControlBase._elaborate(self, platform)
+        self.m = ControlBase.elaborate(self, platform)
 
         result = self.stage.ospec()
         r_data = self.stage.ospec()
@@ -908,7 +908,7 @@ class SimpleHandshake(ControlBase):
     """
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         r_busy = Signal()
         result = self.stage.ospec()
@@ -1016,7 +1016,7 @@ class UnbufferedPipeline(ControlBase):
     """
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         data_valid = Signal() # is data valid or not
         r_data = self.stage.ospec() # output type
@@ -1102,7 +1102,7 @@ class UnbufferedPipeline2(ControlBase):
     """
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         buf_full = Signal() # is data valid or not
         buf = self.stage.ospec() # output type
@@ -1168,7 +1168,7 @@ class PassThroughHandshake(ControlBase):
     """
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         r_data = self.stage.ospec() # output type
 
@@ -1240,7 +1240,7 @@ class FIFOControl(ControlBase):
         ControlBase.__init__(self, stage, in_multi, stage_ctl)
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         # make a FIFO with a signal of equal width to the o_data.
         (fwidth, _) = shape(self.n.o_data)
diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index ee1734e8..2ea1678b 100644
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -14,7 +14,7 @@
 
 """
 
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
 from nmigen.hdl.rec import Record
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
@@ -297,7 +297,7 @@ class ExampleBufPipe2(ControlBase):
     """
 
     def elaborate(self, platform):
-        m = Module()
+        m = ControlBase.elaborate(self, platform)
 
         pipe1 = ExampleBufPipe()
         pipe2 = ExampleBufPipe()
@@ -342,7 +342,7 @@ def resultfn_9(o_data, expected, i, o):
 # Test 6 and 10
 ######################################################################
 
-class SetLessThan:
+class SetLessThan(Elaboratable):
     def __init__(self, width, signed):
         self.m = Module()
         self.src1 = Signal((width, signed), name="src1")
@@ -377,7 +377,7 @@ class LTStage(StageCls):
         return self.o
 
 
-class LTStageDerived(SetLessThan, StageCls):
+class LTStageDerived(SetLessThan, StageCls, Elaboratable):
     """ special version of a nmigen module where the module is also a stage
 
         shows that you don't actually need to combinatorially connect
@@ -591,7 +591,7 @@ def data_2op():
 # Test 12
 ######################################################################
 
-class ExampleStageDelayCls(StageCls):
+class ExampleStageDelayCls(StageCls, Elaboratable):
     """ an example of how to use the buffered pipeline, in a static class
         fashion
     """
@@ -691,7 +691,7 @@ class ExampleBufModeAdd1Pipe(SimpleHandshake):
 class ExampleBufModeUnBufPipe(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         pipe1 = ExampleBufModeAdd1Pipe()
         pipe2 = ExampleBufAdd1Pipe()
@@ -748,7 +748,7 @@ class ExamplePassAdd1Pipe(PassThroughHandshake):
 class ExampleBufPassThruPipe(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         # XXX currently fails: any other permutation works fine.
         # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
@@ -785,7 +785,7 @@ class FIFOTest16(FIFOControl):
 class ExampleFIFOPassThruPipe1(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         pipe1 = FIFOTest16()
         pipe2 = ExamplePassAdd1Pipe()
@@ -852,7 +852,7 @@ class FIFOTestRecordControl(FIFOControl):
 class ExampleFIFORecordObjectPipe(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         pipe1 = FIFOTestRecordControl()
         pipe2 = ExampleRecordHandshakeAddClass()
@@ -891,7 +891,7 @@ class FIFOTestAdd16(FIFOControl):
 class ExampleFIFOAdd2Pipe(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         pipe1 = FIFOTestAdd16()
         pipe2 = FIFOTestAdd16()
@@ -925,7 +925,7 @@ class FIFOTest2x16(FIFOControl):
 class ExampleBufPassThruPipe2(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         # XXX currently fails: any other permutation works fine.
         # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
@@ -953,7 +953,7 @@ class ExampleBufPipe3(ControlBase):
     """
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         pipe1 = ExampleBufDelayedPipe()
         pipe2 = ExampleBufPipe()
@@ -987,7 +987,7 @@ class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
 class ExampleBufUnBufPipe(ControlBase):
 
     def elaborate(self, platform):
-        m = ControlBase._elaborate(self, platform)
+        m = ControlBase.elaborate(self, platform)
 
         # XXX currently fails: any other permutation works fine.
         # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
diff --git a/src/add/test_div64.py b/src/add/test_div64.py
index bc5bd47e..5a9daf23 100644
--- a/src/add/test_div64.py
+++ b/src/add/test_div64.py
@@ -9,7 +9,7 @@ class ORGate:
         self.b = Signal()
         self.x = Signal()
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
         m.d.comb += self.x.eq(self.a | self.b)
diff --git a/src/add/test_fpnum.py b/src/add/test_fpnum.py
index 20036586..6d9ecd10 100644
--- a/src/add/test_fpnum.py
+++ b/src/add/test_fpnum.py
@@ -9,7 +9,7 @@ class FPNumModShiftMulti:
         self.a = FPNum(width)
         self.ediff = Signal((self.a.e_width, True))
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
         #m.d.sync += self.a.decode(self.a.v)
diff --git a/src/add/test_multishift.py b/src/add/test_multishift.py
index 2aa6ba33..651e5018 100644
--- a/src/add/test_multishift.py
+++ b/src/add/test_multishift.py
@@ -11,7 +11,7 @@ class MultiShiftModL:
         self.b = Signal(self.ms.smax)
         self.x = Signal(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
         m.d.comb += self.x.eq(self.ms.lshift(self.a, self.b))
@@ -25,7 +25,7 @@ class MultiShiftModR:
         self.b = Signal(self.ms.smax)
         self.x = Signal(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
         m.d.comb += self.x.eq(self.ms.rshift(self.a, self.b))
@@ -39,7 +39,7 @@ class MultiShiftModRMod:
         self.b = Signal(self.ms.smax)
         self.x = Signal(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
         m.submodules += self.ms
@@ -56,7 +56,7 @@ class MultiShiftRMergeMod:
         self.b = Signal(self.ms.smax)
         self.x = Signal(width)
 
-    def get_fragment(self, platform=None):
+    def elaborate(self, platform=None):
 
         m = Module()
         m.submodules += self.ms
-- 
2.30.2