From c680acac84cda72c69294a777ac91719b5876678 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Dec 2021 15:49:25 +0000
Subject: [PATCH] add mmu.bin test2 to much simpler test_loadstore1.py this
 eliminates TestIssuer (and the MMU FSM-based FU) from enquiries into a VM
 lookup bug where virtual address is being treated as the real

---
 src/soc/experiment/test/pagetables.py         |  4 +-
 src/soc/experiment/test/test_loadstore1.py    | 53 ++++++++++++++++---
 .../simple/test/test_issuer_mmu_microwatt.py  |  4 +-
 3 files changed, 51 insertions(+), 10 deletions(-)

diff --git a/src/soc/experiment/test/pagetables.py b/src/soc/experiment/test/pagetables.py
index 42a75850..885c0744 100644
--- a/src/soc/experiment/test/pagetables.py
+++ b/src/soc/experiment/test/pagetables.py
@@ -49,8 +49,8 @@ test2 = {
 }
 
 
-# microwatt mmu.bin first part of test 3. PRTBL must be set to 0x12000, PID to 1
-microwatt_test3 = {
+# microwatt mmu.bin first part of test 2. PRTBL must be set to 0x12000, PID to 1
+microwatt_test2 = {
              0x10000: 0x0930010000000080, # leaf node
              0x12010: 0x0a00010000000000, # page table
              0x8108: 0x0000000badc0ffee,  # memory to be looked up
diff --git a/src/soc/experiment/test/test_loadstore1.py b/src/soc/experiment/test/test_loadstore1.py
index 5dc70423..7d258a4e 100644
--- a/src/soc/experiment/test/test_loadstore1.py
+++ b/src/soc/experiment/test/test_loadstore1.py
@@ -492,6 +492,30 @@ def _test_loadstore1_invalid(dut, mem):
     wbget.stop = True
 
 
+def _test_loadstore1_microwatt_mmu_bin_test2(dut, mem):
+    mmu = dut.submodules.mmu
+    pi = dut.submodules.ldst.pi
+    ldst = dut.submodules.ldst # to get at DAR (NOT part of PortInterface)
+    wbget.stop = False
+
+    yield mmu.rin.prtbl.eq(0x12000) # set process table
+    yield mmu.rin.pid.eq(0x1)       # set PID=1
+    yield
+
+    addr = 0x124108
+    msr = MSRSpec(pr=1, dr=1, sf=1)
+
+    print("=== alignment error (ld) ===")
+
+    ld_data, exctype, exc = yield from pi_ld(pi, addr, 8, msr=msr)
+    print("ld_data after mmu.bin test2")
+    print(ld_data)
+    assert ld_data == 0x0000000badc0ffee
+    assert exctype is None
+
+    wbget.stop = True
+
+
 def _test_loadstore1(dut, mem):
     mmu = dut.submodules.mmu
     pi = dut.submodules.ldst.pi
@@ -824,6 +848,22 @@ def test_loadstore1():
         sim.run()
 
 
+def test_loadstore1_microwatt_mmu_bin_test2():
+
+    m, cmpi = setup_mmu()
+
+    mem = pagetables.microwatt_test2
+
+    # nmigen Simulation
+    sim = Simulator(m)
+    sim.add_clock(1e-6)
+
+    sim.add_sync_process(wrap(_test_loadstore1_microwatt_mmu_bin_test2(m, mem)))
+    sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
+    with sim.write_vcd('test_loadstore1.vcd'):
+        sim.run()
+
+
 def test_loadstore1_invalid():
 
     m, cmpi = setup_mmu()
@@ -888,9 +928,10 @@ def test_loadstore1_ifetch_multi():
         sim.run()
 
 if __name__ == '__main__':
-    test_loadstore1()
-    test_loadstore1_invalid()
-    test_loadstore1_ifetch() #FIXME
-    test_loadstore1_ifetch_invalid()
-    test_loadstore1_ifetch_unit_iface() # guess: should be working
-    test_loadstore1_ifetch_multi()
+    #test_loadstore1()
+    test_loadstore1_microwatt_mmu_bin_test2()
+    #test_loadstore1_invalid()
+    #test_loadstore1_ifetch() #FIXME
+    #test_loadstore1_ifetch_invalid()
+    #test_loadstore1_ifetch_unit_iface() # guess: should be working
+    #test_loadstore1_ifetch_multi()
diff --git a/src/soc/simple/test/test_issuer_mmu_microwatt.py b/src/soc/simple/test/test_issuer_mmu_microwatt.py
index c13529ab..69fe9ffe 100644
--- a/src/soc/simple/test/test_issuer_mmu_microwatt.py
+++ b/src/soc/simple/test/test_issuer_mmu_microwatt.py
@@ -51,7 +51,7 @@ class MMUTestCase(TestAccumulatorBase):
         initial_regs[2] = 0x124108
 
         # memory same as microwatt test
-        initial_mem = pagetables.microwatt_test3
+        initial_mem = pagetables.microwatt_test2
 
         # set virtual and non-privileged
         # msr: 8000000000000011
@@ -87,7 +87,7 @@ if __name__ == "__main__":
     # MMU/DCache integration tests
     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
                               microwatt_mmu=True,
-                              rom=pagetables.microwatt_test3))
+                              rom=pagetables.microwatt_test2))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)
-- 
2.30.2