From c68d55676810abd5c63277fecef2f1686ba38bf7 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 5 Sep 2017 17:51:40 -0700
Subject: [PATCH] ShiftRegInit: use the rocket-chip version since it is there
 now

---
 src/main/scala/devices/i2c/I2CPins.scala              | 7 +++----
 src/main/scala/devices/mockaon/MockAONPeriphery.scala | 3 ++-
 src/main/scala/devices/spi/SPIPhysical.scala          | 6 +++---
 src/main/scala/devices/uart/UARTPeriphery.scala       | 4 ++--
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index bae0bc6..1a02a59 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -3,9 +3,8 @@ package sifive.blocks.devices.i2c
 
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.ShiftRegInit
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
-
 
 class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
 
@@ -19,11 +18,11 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe
-      i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
+      i2c.scl.in := ShiftRegInit(scl.i.ival, syncStages, init = Bool(true))
 
       sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
       sda.o.oe := i2c.sda.oe
-      i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+      i2c.sda.in := ShiftRegInit(sda.i.ival, syncStages, init = Bool(true))
     }
   }
 }
diff --git a/src/main/scala/devices/mockaon/MockAONPeriphery.scala b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index 3f0d326..b20bee2 100644
--- a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@ -3,6 +3,7 @@ package sifive.blocks.devices.mockaon
 
 import Chisel._
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SynchronizerShiftReg
 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
 import freechips.rocketchip.devices.debug.HasPeripheryDebug
 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
@@ -43,7 +44,7 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
   outer.aon.module.reset := Bool(true)
 
   // Synchronize the external toggle into the clint
-  val rtc_sync = ShiftRegister(outer.aon.module.io.rtc.asUInt.toBool, 3)
+  val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
   val rtc_last = Reg(init = Bool(false), next=rtc_sync)
   val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
 
diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala
index a9ce076..25ad882 100644
--- a/src/main/scala/devices/spi/SPIPhysical.scala
+++ b/src/main/scala/devices/spi/SPIPhysical.scala
@@ -2,7 +2,7 @@
 package sifive.blocks.devices.spi
 
 import Chisel._
-import sifive.blocks.util.ShiftRegisterInit
+import freechipchips.rocketchip.util.ShiftRegInit
 
 class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
   val fn = Bits(width = 1)
@@ -39,8 +39,8 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
   val last = Wire(init = Bool(false))
   // Delayed versions
   val setup_d = Reg(next = setup)
-  val sample_d = ShiftRegisterInit(sample, c.sampleDelay, Bool(false))
-  val last_d = ShiftRegisterInit(last, c.sampleDelay, Bool(false))
+  val sample_d = ShiftRegInit(sample, c.sampleDelay, init = Bool(false))
+  val last_d = ShiftRegInit(last, c.sampleDelay, init = Bool(false))
 
   val scnt = Reg(init = UInt(0, c.countBits))
   val tcnt = Reg(io.ctrl.sck.div)
diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index 00e5fdd..4a517cb 100644
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -4,10 +4,10 @@ package sifive.blocks.devices.uart
 import Chisel._
 import chisel3.experimental.{withClockAndReset}
 import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.ShiftRegInit
 import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
 import sifive.blocks.devices.pinctrl.{Pin}
-import sifive.blocks.util.ShiftRegisterInit
 
 case object PeripheryUARTKey extends Field[Seq[UARTParams]]
 
@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()
-      uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+      uart.rxd := ShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
     }
   }
 }
-- 
2.30.2