From c69c416d28015e496045d1b4529c465fbaad42e2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 28 Dec 2013 11:54:40 +0100
Subject: [PATCH] Added $bu0 cell (for easy correct $eq/$ne mapping)

---
 kernel/calc.cc              |  8 ++++++++
 kernel/celltypes.h          |  2 ++
 kernel/rtlil.cc             |  2 +-
 kernel/rtlil.h              |  1 +
 passes/techmap/simplemap.cc | 13 +++++++++++++
 techlibs/common/stdcells.v  | 14 ++++++++++----
 6 files changed, 35 insertions(+), 5 deletions(-)

diff --git a/kernel/calc.cc b/kernel/calc.cc
index fc978c11a..a56db93aa 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -543,6 +543,14 @@ RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, boo
 	return arg1_ext;
 }
 
+RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
+{
+	RTLIL::Const arg1_ext = arg1;
+	extend_u0(arg1_ext, result_len, signed1);
+
+	return arg1_ext;
+}
+
 RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 {
 	RTLIL::Const arg1_ext = arg1;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 29eb490f8..2f311c826 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -60,6 +60,7 @@ struct CellTypes
 	{
 		cell_types.insert("$not");
 		cell_types.insert("$pos");
+		cell_types.insert("$bu0");
 		cell_types.insert("$neg");
 		cell_types.insert("$and");
 		cell_types.insert("$or");
@@ -250,6 +251,7 @@ struct CellTypes
 		HANDLE_CELL_TYPE(mod)
 		HANDLE_CELL_TYPE(pow)
 		HANDLE_CELL_TYPE(pos)
+		HANDLE_CELL_TYPE(bu0)
 		HANDLE_CELL_TYPE(neg)
 #undef HANDLE_CELL_TYPE
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 47dc098a4..b8c9e21ac 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -370,7 +370,7 @@ namespace {
 
 		void check()
 		{
-			if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$neg") {
+			if (cell->type == "$not" || cell->type == "$pos" || cell->type == "$bu0" || cell->type == "$neg") {
 				param("\\A_SIGNED");
 				port("\\A", param("\\A_WIDTH"));
 				port("\\Y", param("\\Y_WIDTH"));
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 91dd9d44c..8e3b78eef 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -187,6 +187,7 @@ namespace RTLIL
 	RTLIL::Const const_pow         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
 
 	RTLIL::Const const_pos         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
+	RTLIL::Const const_bu0         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
 	RTLIL::Const const_neg         (const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len);
 };
 
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index fbd86d591..6b25eb9b1 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -60,6 +60,18 @@ static void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
 	module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
 }
 
+static void simplemap_bu0(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	int width = cell->parameters.at("\\Y_WIDTH").as_int();
+
+	RTLIL::SigSpec sig_a = cell->connections.at("\\A");
+	sig_a.extend_u0(width, cell->parameters.at("\\A_SIGNED").as_bool());
+
+	RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
+
+	module->connections.push_back(RTLIL::SigSig(sig_y, sig_a));
+}
+
 static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	int width = cell->parameters.at("\\Y_WIDTH").as_int();
@@ -454,6 +466,7 @@ void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::
 {
 	mappers["$not"]         = simplemap_not;
 	mappers["$pos"]         = simplemap_pos;
+	mappers["$bu0"]         = simplemap_bu0;
 	mappers["$and"]         = simplemap_bitop;
 	mappers["$or"]          = simplemap_bitop;
 	mappers["$xor"]         = simplemap_bitop;
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index c7efa240e..5482d3804 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -44,6 +44,12 @@ endmodule
 
 // --------------------------------------------------------
 
+(* techmap_simplemap *)
+module \$bu0 ;
+endmodule
+
+// --------------------------------------------------------
+
 module \$neg (A, Y);
 
 parameter A_SIGNED = 0;
@@ -538,8 +544,8 @@ output [Y_WIDTH-1:0] Y;
 
 wire carry, carry_sign;
 wire [WIDTH-1:0] A_buf, B_buf;
-\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
-\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
+\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
+\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 
 assign Y = ~|(A_buf ^ B_buf);
 
@@ -563,8 +569,8 @@ output [Y_WIDTH-1:0] Y;
 
 wire carry, carry_sign;
 wire [WIDTH-1:0] A_buf, B_buf;
-\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
-\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
+\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
+\$bu0 #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
 
 assign Y = |(A_buf ^ B_buf);
 
-- 
2.30.2