From c6ad07b572b06e2606e404738284e01c3c791dd5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 25 May 2021 12:31:31 +0100 Subject: [PATCH] rename PLL signals --- src/soc/clock/dummypll.py | 2 +- src/soc/simple/issuer.py | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py index fd437ef1..bd876593 100644 --- a/src/soc/clock/dummypll.py +++ b/src/soc/clock/dummypll.py @@ -21,7 +21,7 @@ class DummyPLL(Elaboratable): pll = Instance("pll", i_ref=self.clk_24_i, i_a0=self.clk_sel_i[0], i_a1=self.clk_sel_i[1], - o_out=self.clk_pll_o, + o_out_v=self.clk_pll_o, o_div_out_test=self.pll_test_o, o_vco_test_ana=self.pll_vco_o, ) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 4e919520..85e3cbd5 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -1233,6 +1233,7 @@ class TestIssuer(Elaboratable): self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll if self.pll_en: self.pll_test_o = Signal(reset_less=True) + self.pll_vco_o = Signal(reset_less=True) self.clk_sel_i = Signal(reset_less=True) def elaborate(self, platform): @@ -1259,8 +1260,9 @@ class TestIssuer(Elaboratable): # wire up external 24mhz to PLL comb += pll.clk_24_i.eq(ClockSignal()) - # output 18 mhz PLL test signal + # output 18 mhz PLL test signal, and analog oscillator out comb += self.pll_test_o.eq(pll.pll_test_o) + comb += self.pll_vco_o.eq(pll.pll_vco_o) # input to pll clock selection comb += pll.clk_sel_i.eq(self.clk_sel_i) @@ -1290,7 +1292,7 @@ class TestIssuer(Elaboratable): if self.pll_en: ports.append(self.clk_sel_i) ports.append(self.pll_test_o) - ports.append(self.pll.pll_vco_o) + ports.append(self.pll_vco_o) return ports -- 2.30.2