From c6beaa06b12bd67fcd28999ef7cfe716195f351f Mon Sep 17 00:00:00 2001
From: klehman <klehman9@comcast.net>
Date: Fri, 1 Oct 2021 18:01:47 -0400
Subject: [PATCH] fix for self.rom core

---
 src/openpower/test/runner.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index bb43c558..a6ecd9f0 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -402,7 +402,7 @@ class TestRunnerBase(FHDLTestCase):
         # optionally, if a wishbone-based ROM is passed in, run that as an
         # extra emulated process
         if self.rom is not None:
-            dcache = core.fus.fus["mmu0"].alu.dcache
+            dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
             default_mem = self.rom
             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 
-- 
2.30.2