From c6cbaa42b808001834185718eece53d66b8877c8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 8 Mar 2020 18:29:23 +0000 Subject: [PATCH] likewise comment out CR from decode, it is from the CR SPR regfile --- src/decoder/power_decoder2.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/decoder/power_decoder2.py b/src/decoder/power_decoder2.py index c7140a6e..1e56fe59 100644 --- a/src/decoder/power_decoder2.py +++ b/src/decoder/power_decoder2.py @@ -279,7 +279,7 @@ class Decode2ToExecute1Type: self.read_data1 = Signal(64, reset_less=True) self.read_data2 = Signal(64, reset_less=True) self.read_data3 = Signal(64, reset_less=True) - self.cr = Signal(32, reset_less=True) + #self.cr = Signal(32, reset_less=True) # NO: this is from the CR SPR #self.xerc = XerBits() # NO: this is from the XER SPR self.lk = Signal(reset_less=True) self.rc = Signal(reset_less=True) @@ -302,7 +302,8 @@ class Decode2ToExecute1Type: return [self.valid, self.insn_type, self.nia, self.write_reg, self.read_reg1, self.read_reg2, self.read_reg3, self.read_data1, self.read_data2, self.read_data3, - self.cr, self.lk, self.rc, self.oe, + #self.cr, + self.lk, self.rc, self.oe, self.invert_a, self.invert_out, self.input_carry, self.output_carry, self.input_cr, self.output_cr, -- 2.30.2