From c6cede244b431c167ac0213d89ad2bd7a0abbd96 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Wed, 10 Feb 2016 04:08:27 -0500 Subject: [PATCH] stats: Update stats to reflect changes to cache and crossbar --- .../ref/alpha/linux/tsunami-minor/stats.txt | 1409 ++-- .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 3912 +++++----- .../ref/alpha/linux/tsunami-o3/stats.txt | 1903 +++-- .../linux/tsunami-switcheroo-full/stats.txt | 2179 +++--- .../arm/linux/realview-minor-dual/stats.txt | 4577 ++++++------ .../ref/arm/linux/realview-minor/stats.txt | 1750 +++-- .../arm/linux/realview-o3-checker/stats.txt | 1963 ++--- .../ref/arm/linux/realview-o3-dual/stats.txt | 5899 ++++++++------- .../ref/arm/linux/realview-o3/stats.txt | 1941 ++--- .../linux/realview-switcheroo-full/stats.txt | 4525 ++++++------ .../linux/realview-switcheroo-o3/stats.txt | 3781 +++++----- .../arm/linux/realview64-minor-dual/stats.txt | 5186 ++++++------- .../ref/arm/linux/realview64-minor/stats.txt | 2063 +++--- .../arm/linux/realview64-o3-checker/stats.txt | 2870 ++++---- .../arm/linux/realview64-o3-dual/stats.txt | 6513 +++++++++-------- .../ref/arm/linux/realview64-o3/stats.txt | 2770 +++---- .../stats.txt | 924 +-- .../realview64-simple-atomic-dual/stats.txt | 2256 +++--- .../linux/realview64-simple-atomic/stats.txt | 924 +-- .../realview64-simple-timing-dual/stats.txt | 5290 ++++++------- .../linux/realview64-simple-timing/stats.txt | 2134 +++--- .../realview64-switcheroo-atomic/stats.txt | 1422 ++-- .../realview64-switcheroo-full/stats.txt | 5128 +++++++------ .../linux/realview64-switcheroo-o3/stats.txt | 4357 +++++------ .../realview64-switcheroo-timing/stats.txt | 3175 ++++---- .../ref/x86/linux/pc-o3-timing/stats.txt | 2533 ++++--- .../stats.txt | 330 +- .../x86/linux/pc-switcheroo-full/stats.txt | 3257 +++++---- .../ref/arm/linux/minor-timing/stats.txt | 24 +- .../10.mcf/ref/arm/linux/o3-timing/stats.txt | 1350 ++-- .../ref/sparc/linux/simple-timing/stats.txt | 16 +- .../10.mcf/ref/x86/linux/o3-timing/stats.txt | 34 +- .../ref/alpha/tru64/minor-timing/stats.txt | 16 +- .../ref/arm/linux/minor-timing/stats.txt | 26 +- .../ref/arm/linux/o3-timing/stats.txt | 1567 ++-- .../ref/arm/linux/simple-timing/stats.txt | 24 +- .../ref/x86/linux/o3-timing/stats.txt | 1583 ++-- .../ref/arm/linux/minor-timing/stats.txt | 24 +- .../30.eon/ref/arm/linux/o3-timing/stats.txt | 297 +- .../ref/arm/linux/simple-timing/stats.txt | 24 +- .../ref/alpha/tru64/minor-timing/stats.txt | 16 +- .../ref/alpha/tru64/o3-timing/stats.txt | 16 +- .../ref/arm/linux/minor-timing/stats.txt | 30 +- .../ref/arm/linux/o3-timing/stats.txt | 1355 ++-- .../ref/arm/linux/simple-timing/stats.txt | 24 +- .../ref/alpha/tru64/minor-timing/stats.txt | 12 +- .../ref/alpha/tru64/o3-timing/stats.txt | 12 +- .../ref/arm/linux/minor-timing/stats.txt | 30 +- .../ref/arm/linux/o3-timing/stats.txt | 1661 +++-- .../ref/alpha/tru64/minor-timing/stats.txt | 12 +- .../ref/alpha/tru64/o3-timing/stats.txt | 12 +- .../ref/arm/linux/minor-timing/stats.txt | 18 +- .../ref/arm/linux/o3-timing/stats.txt | 1645 +++-- .../ref/arm/linux/simple-timing/stats.txt | 16 +- .../ref/arm/linux/minor-timing/stats.txt | 24 +- .../ref/arm/linux/o3-timing/stats.txt | 24 +- .../ref/x86/linux/o3-timing/stats.txt | 1393 ++-- .../tsunami-simple-atomic-dual/stats.txt | 834 +-- .../linux/tsunami-simple-atomic/stats.txt | 466 +- .../tsunami-simple-timing-dual/stats.txt | 2356 +++--- .../linux/tsunami-simple-timing/stats.txt | 1044 ++- .../stats.txt | 538 +- .../realview-simple-atomic-dual/stats.txt | 1630 ++--- .../linux/realview-simple-atomic/stats.txt | 538 +- .../realview-simple-timing-dual/stats.txt | 4619 ++++++------ .../linux/realview-simple-timing/stats.txt | 1420 ++-- .../realview-switcheroo-atomic/stats.txt | 1116 +-- .../realview-switcheroo-timing/stats.txt | 2353 +++--- .../ref/x86/linux/pc-simple-atomic/stats.txt | 562 +- .../ref/x86/linux/pc-simple-timing/stats.txt | 1646 +++-- .../stats.txt | 10 +- .../stats.txt | 10 +- .../simple-timing-ruby-MOESI_hammer/stats.txt | 10 +- .../alpha/linux/simple-timing-ruby/stats.txt | 10 +- .../stats.txt | 10 +- .../stats.txt | 10 +- .../simple-timing-ruby-MOESI_hammer/stats.txt | 10 +- .../alpha/tru64/simple-timing-ruby/stats.txt | 10 +- .../ref/arm/linux/minor-timing/stats.txt | 20 +- .../ref/arm/linux/o3-timing-checker/stats.txt | 19 +- .../ref/arm/linux/o3-timing/stats.txt | 24 +- .../ref/arm/linux/simple-timing/stats.txt | 19 +- .../learning-gem5-p1-two-level/stats.txt | 16 +- .../learning-gem5-p1-two-level/stats.txt | 16 +- .../ref/arm/linux/simple-timing/stats.txt | 24 +- .../ref/sparc/linux/o3-timing-mp/stats.txt | 3813 +++++----- .../sparc/linux/simple-atomic-mp/stats.txt | 62 +- .../sparc/linux/simple-timing-mp/stats.txt | 2071 +++--- .../memtest-ruby-MESI_Two_Level/stats.txt | 6 +- .../linux/memtest-ruby-MOESI_hammer/stats.txt | 6 +- .../ref/alpha/linux/memtest-ruby/stats.txt | 6 +- .../ref/null/none/memtest-filter/stats.txt | 3433 +++++---- .../ref/null/none/memtest/stats.txt | 3436 ++++----- .../ref/arm/linux/simple-timing/stats.txt | 24 +- .../ref/sparc/linux/simple-timing/stats.txt | 24 +- .../rubytest-ruby-MESI_Two_Level/stats.txt | 6 +- .../stats.txt | 6 +- .../rubytest-ruby-MOESI_hammer/stats.txt | 6 +- .../ref/alpha/linux/rubytest-ruby/stats.txt | 6 +- .../ref/arm/linux/simple-timing/stats.txt | 24 +- 100 files changed, 64269 insertions(+), 64256 deletions(-) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index c02ff892c..fcaff51da 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.906049 # Number of seconds simulated -sim_ticks 1906048606500 # Number of ticks simulated -final_tick 1906048606500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.906052 # Number of seconds simulated +sim_ticks 1906052165500 # Number of ticks simulated +final_tick 1906052165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 268534 # Simulator instruction rate (inst/s) -host_op_rate 268534 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9116285517 # Simulator tick rate (ticks/s) -host_mem_usage 332204 # Number of bytes of host memory used -host_seconds 209.08 # Real time elapsed on the host -sim_insts 56145568 # Number of instructions simulated -sim_ops 56145568 # Number of ops (including micro ops) simulated +host_inst_rate 263346 # Simulator instruction rate (inst/s) +host_op_rate 263346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8940174363 # Simulator tick rate (ticks/s) +host_mem_usage 335264 # Number of bytes of host memory used +host_seconds 213.20 # Real time elapsed on the host +sim_insts 56145499 # Number of instructions simulated +sim_ops 56145499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1044672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24858752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858688 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25904384 # Number of bytes read from this memory +system.physmem.bytes_read::total 25904320 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1044672 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1044672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7563136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7563136 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7563072 # Number of bytes written to this memory +system.physmem.bytes_written::total 7563072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 16323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388417 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404756 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118174 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118174 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 548083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13042035 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404755 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 548082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13041977 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13590621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 548083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 548083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3967966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3967966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3967966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 548083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13042035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13590562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 548082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 548082 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3967925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3967925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3967925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 548082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13041977 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17558587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404756 # Number of read requests accepted -system.physmem.writeReqs 118174 # Number of write requests accepted -system.physmem.readBursts 404756 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118174 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25897280 # Total number of bytes read from DRAM +system.physmem.bw_total::total 17558487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404755 # Number of read requests accepted +system.physmem.writeReqs 118173 # Number of write requests accepted +system.physmem.readBursts 404755 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25897216 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7561536 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25904384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7563136 # Total written bytes from the system interface side +system.physmem.bytesWritten 7561728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25904320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563072 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303809 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25477 # Per bank write bursts system.physmem.perBankRdBursts::1 25704 # Per bank write bursts system.physmem.perBankRdBursts::2 25816 # Per bank write bursts -system.physmem.perBankRdBursts::3 25780 # Per bank write bursts +system.physmem.perBankRdBursts::3 25781 # Per bank write bursts system.physmem.perBankRdBursts::4 25083 # Per bank write bursts -system.physmem.perBankRdBursts::5 25011 # Per bank write bursts +system.physmem.perBankRdBursts::5 25010 # Per bank write bursts system.physmem.perBankRdBursts::6 24709 # Per bank write bursts system.physmem.perBankRdBursts::7 24576 # Per bank write bursts -system.physmem.perBankRdBursts::8 25197 # Per bank write bursts +system.physmem.perBankRdBursts::8 25196 # Per bank write bursts system.physmem.perBankRdBursts::9 25297 # Per bank write bursts system.physmem.perBankRdBursts::10 25389 # Per bank write bursts system.physmem.perBankRdBursts::11 25021 # Per bank write bursts -system.physmem.perBankRdBursts::12 24535 # Per bank write bursts +system.physmem.perBankRdBursts::12 24534 # Per bank write bursts system.physmem.perBankRdBursts::13 25530 # Per bank write bursts system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25725 # Per bank write bursts +system.physmem.perBankRdBursts::15 25726 # Per bank write bursts system.physmem.perBankWrBursts::0 7822 # Per bank write bursts system.physmem.perBankWrBursts::1 7672 # Per bank write bursts system.physmem.perBankWrBursts::2 8075 # Per bank write bursts -system.physmem.perBankWrBursts::3 7744 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts system.physmem.perBankWrBursts::4 7196 # Per bank write bursts system.physmem.perBankWrBursts::5 7016 # Per bank write bursts system.physmem.perBankWrBursts::6 6702 # Per bank write bursts system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7310 # Per bank write bursts +system.physmem.perBankWrBursts::8 7309 # Per bank write bursts system.physmem.perBankWrBursts::9 6908 # Per bank write bursts -system.physmem.perBankWrBursts::10 7272 # Per bank write bursts +system.physmem.perBankWrBursts::10 7271 # Per bank write bursts system.physmem.perBankWrBursts::11 7002 # Per bank write bursts system.physmem.perBankWrBursts::12 7086 # Per bank write bursts system.physmem.perBankWrBursts::13 7981 # Per bank write bursts system.physmem.perBankWrBursts::14 7993 # Per bank write bursts -system.physmem.perBankWrBursts::15 7943 # Per bank write bursts +system.physmem.perBankWrBursts::15 7947 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1906039923500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1906043365500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404756 # Read request sizes (log2) +system.physmem.readPktSize::6 404755 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118174 # Write request sizes (log2) +system.physmem.writePktSize::6 118173 # Write request sizes (log2) system.physmem.rdQLenPdf::0 402408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2161 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -148,124 +148,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 519.546832 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 318.268868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 407.153797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14837 23.04% 23.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11098 17.23% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4944 7.68% 47.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3257 5.06% 53.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2526 3.92% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1968 3.06% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4176 6.48% 66.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1357 2.11% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20237 31.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64400 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5302 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.317050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2899.726540 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5299 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 519.089377 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 317.985274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 407.069012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14849 23.04% 23.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11122 17.25% 40.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4951 7.68% 47.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3330 5.17% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2494 3.87% 57.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1955 3.03% 60.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4176 6.48% 66.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1342 2.08% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20238 31.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64457 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.462207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2902.463532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5289 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5302 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.283855 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.156721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4666 88.00% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 22 0.41% 88.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 20 0.38% 88.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 187 3.53% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.11% 92.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.47% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.81% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 93.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.15% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.34% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 6 0.11% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 18 0.34% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.47% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 27 0.51% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 172 3.24% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 7 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 8 0.15% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5302 # Writes before turning the bus around for reads -system.physmem.totQLat 2637486000 # Total ticks spent queuing -system.physmem.totMemAccLat 10224579750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6518.02 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5292 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.326531 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.072850 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.540172 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4687 88.57% 88.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 34 0.64% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 32 0.60% 89.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 42 0.79% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 211 3.99% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 13 0.25% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 25 0.47% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 188 3.55% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 3 0.06% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 3 0.06% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 3 0.06% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 11 0.21% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 9 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 5 0.09% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5292 # Writes before turning the bus around for reads +system.physmem.totQLat 2635925000 # Total ticks spent queuing +system.physmem.totMemAccLat 10223000000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2023220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6514.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25268.02 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25264.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.59 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.97 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.59 # Average system read bandwidth in MiByte/s @@ -275,71 +263,71 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.35 # Average write queue length when enqueuing -system.physmem.readRowHits 362820 # Number of row buffer hits during reads -system.physmem.writeRowHits 95574 # Number of row buffer hits during writes +system.physmem.avgWrQLen 26.36 # Average write queue length when enqueuing +system.physmem.readRowHits 362809 # Number of row buffer hits during reads +system.physmem.writeRowHits 95530 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.88 # Row buffer hit rate for writes -system.physmem.avgGap 3644923.65 # Average gap between requests -system.physmem.pageHitRate 87.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 237573000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 129628125 # Energy for precharge commands per rank (pJ) +system.physmem.writeRowHitRate 80.84 # Row buffer hit rate for writes +system.physmem.avgGap 3644944.17 # Average gap between requests +system.physmem.pageHitRate 87.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238124880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 129929250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1576816800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 380077920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 67955758245 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1084015546500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1278788854350 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.912874 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1803098707000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63646960000 # Time in different power states +system.physmem_0.writeEnergy 380084400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 67910384250 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1084060020000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1278789321900 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.910378 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1803172860750 # Time in different power states +system.physmem_0.memoryStateTime::REF 63647220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 39297448000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 39230820500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 249291000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136021875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579414200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 385527600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124493453760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68412640320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1083614781000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1278871129755 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.956034 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1802432810250 # Time in different power states -system.physmem_1.memoryStateTime::REF 63646960000 # Time in different power states +system.physmem_1.actEnergy 249170040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135955875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579406400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 385540560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124493962320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68468592375 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1083570372000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1278882999570 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.959521 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1802360809750 # Time in different power states +system.physmem_1.memoryStateTime::REF 63647220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 39963358500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 40042885250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15009028 # Number of BP lookups -system.cpu.branchPred.condPredicted 13018563 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 370758 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9666577 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5199223 # Number of BTB hits +system.cpu.branchPred.lookups 15006509 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016597 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 371031 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9764467 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5201318 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.785564 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807911 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31459 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.267813 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31462 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9243045 # DTB read hits -system.cpu.dtb.read_misses 17179 # DTB read misses +system.cpu.dtb.read_hits 9242631 # DTB read hits +system.cpu.dtb.read_misses 17134 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 765860 # DTB read accesses -system.cpu.dtb.write_hits 6388437 # DTB write hits +system.cpu.dtb.read_accesses 765515 # DTB read accesses +system.cpu.dtb.write_hits 6388389 # DTB write hits system.cpu.dtb.write_misses 2336 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298458 # DTB write accesses -system.cpu.dtb.data_hits 15631482 # DTB hits -system.cpu.dtb.data_misses 19515 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064318 # DTB accesses -system.cpu.itb.fetch_hits 4012772 # ITB hits -system.cpu.itb.fetch_misses 6839 # ITB misses -system.cpu.itb.fetch_acv 666 # ITB acv -system.cpu.itb.fetch_accesses 4019611 # ITB accesses +system.cpu.dtb.write_acv 160 # DTB write access violations +system.cpu.dtb.write_accesses 298460 # DTB write accesses +system.cpu.dtb.data_hits 15631020 # DTB hits +system.cpu.dtb.data_misses 19470 # DTB misses +system.cpu.dtb.data_acv 371 # DTB access violations +system.cpu.dtb.data_accesses 1063975 # DTB accesses +system.cpu.itb.fetch_hits 4014011 # ITB hits +system.cpu.itb.fetch_misses 6826 # ITB misses +system.cpu.itb.fetch_acv 642 # ITB acv +system.cpu.itb.fetch_accesses 4020837 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -352,39 +340,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 221706697 # number of cpu cycles simulated +system.cpu.numCycles 221712638 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56145568 # Number of instructions committed -system.cpu.committedOps 56145568 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2506376 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5532 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3590390516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.948784 # CPI: cycles per instruction -system.cpu.ipc 0.253243 # IPC: instructions per cycle +system.cpu.committedInsts 56145499 # Number of instructions committed +system.cpu.committedOps 56145499 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2504937 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5531 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3590391693 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.948894 # CPI: cycles per instruction +system.cpu.ipc 0.253235 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211538 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211539 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74805 40.93% 40.93% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 133 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1904 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105906 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182748 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105907 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182749 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73438 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 133 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1904 1.28% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73439 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148914 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837271633000 96.39% 96.39% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 83690500 0.00% 96.40% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 707098000 0.04% 96.43% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 67985179000 3.57% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1906047600500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1837274169000 96.39% 96.39% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 83596500 0.00% 96.40% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 707455500 0.04% 96.43% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 67985922500 3.57% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1906051143500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693436 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814860 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814855 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -423,7 +411,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175581 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175582 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6807 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -432,103 +420,103 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192472 # number of callpals executed +system.cpu.kern.callpal::total 192473 # number of callpals executed system.cpu.kern.mode_switch::kernel 5876 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu.kern.mode_switch::user 1738 # number of protection mode switches system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1906 -system.cpu.kern.mode_good::user 1737 +system.cpu.kern.mode_good::kernel 1907 +system.cpu.kern.mode_good::user 1738 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.324370 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.324541 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 38721238500 2.03% 2.03% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4530290000 0.24% 2.27% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1862796062000 97.73% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.392872 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 38725166000 2.03% 2.03% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4529345500 0.24% 2.27% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1862796622000 97.73% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 84511215 # Number of cycles that the object actually ticked -system.cpu.idleCycles 137195482 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 84517271 # Number of cycles that the object actually ticked +system.cpu.idleCycles 137195367 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1395430 # number of replacements system.cpu.dcache.tags.tagsinuse 511.976766 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13774781 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 13774435 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1395942 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.867732 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.867484 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 123981500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.976766 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63671171 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63671171 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7816045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7816045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182827 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182827 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63669791 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63669791 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815717 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815717 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576828 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576828 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182828 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182828 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199029 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199029 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13392891 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13392891 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13392891 # number of overall hits -system.cpu.dcache.overall_hits::total 13392891 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201631 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201631 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 575205 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 575205 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17224 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17224 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1776836 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1776836 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1776836 # number of overall misses -system.cpu.dcache.overall_misses::total 1776836 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 46974912500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 46974912500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33956321000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33956321000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 234952500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 80931233500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 80931233500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 80931233500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 80931233500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9017676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9017676 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152051 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152051 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200051 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200051 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13392545 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392545 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392545 # number of overall hits +system.cpu.dcache.overall_hits::total 13392545 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201618 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201618 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 575220 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 575220 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17222 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17222 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1776838 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1776838 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1776838 # number of overall misses +system.cpu.dcache.overall_misses::total 1776838 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 46968047500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 46968047500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33964546500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33964546500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 234897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 234897500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 80932594000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 80932594000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 80932594000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 80932594000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9017335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9017335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152048 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152048 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200050 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200050 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199029 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199029 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15169727 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15169727 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15169727 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15169727 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093498 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093498 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086098 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086098 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117130 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117130 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117130 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117130 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39092.627021 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39092.627021 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59033.424605 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59033.424605 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13640.995123 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45547.947869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45547.947869 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45547.947869 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 15169383 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15169383 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15169383 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15169383 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133256 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133256 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093501 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093501 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086088 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117133 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117133 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117133 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117133 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39087.336824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39087.336824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59046.184938 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59046.184938 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13639.385669 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13639.385669 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45548.662287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45548.662287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45548.662287 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,84 +525,84 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838232 # number of writebacks -system.cpu.dcache.writebacks::total 838232 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127276 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127276 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270800 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 270800 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838230 # number of writebacks +system.cpu.dcache.writebacks::total 838230 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127262 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127262 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270814 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270814 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 398076 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 398076 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 398076 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 398076 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074355 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074355 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304405 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304405 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17221 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17221 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378760 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378760 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378760 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378760 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074356 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074356 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304406 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304406 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17219 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378762 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378762 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378762 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378762 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43817391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43817391500 # number of ReadReq MSHR miss cycles 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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529366500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2162508500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3691875000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3691875000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119139 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119139 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43812536500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43812536500 # number of ReadReq MSHR miss cycles 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average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12627.954242 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44307.833488 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44307.833488 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220560.498990 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220560.498990 # average ReadReq mshr uncacheable latency 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system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76662 # number of writebacks -system.cpu.l2cache.writebacks::total 76662 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116659 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116659 # number of ReadExReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 76661 # number of writebacks +system.cpu.l2cache.writebacks::total 76661 # number of writebacks +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116656 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116656 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 16324 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadCleanReq_mshr_misses::total 16324 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272207 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272207 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 272208 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 272208 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 16324 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388866 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405190 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388864 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405188 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 16324 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388866 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405190 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388864 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405188 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6934 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6934 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9624 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9624 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16558 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16558 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1285500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13671016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13671016000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1979440000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1979440000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30960462500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30960462500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1979440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44631478500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46610918500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1979440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44631478500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46610918500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442671000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442671000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051831500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818182 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383225 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011173 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249378 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249378 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141825 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011173 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141825 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71416.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117187.838058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117187.838058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121259.495222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121259.495222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113738.671305 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113738.671305 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121259.495222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114773.414235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115034.720748 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.542544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.542544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213199.449293 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211046.171035 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211046.171035 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1175000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1175000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13674958500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13674958500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1978293000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1978293000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30955575000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30955575000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1978293000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44630533500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46608826500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1978293000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44630533500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46608826500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1442672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1442672500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2051806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2051806000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3494478500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3494478500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383211 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383211 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011172 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249379 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249379 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141820 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011172 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278564 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141820 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69117.647059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69117.647059 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117224.647682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117224.647682 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121189.230581 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121189.230581 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113720.298448 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113720.298448 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121189.230581 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 114771.574381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115030.125522 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208057.758869 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208057.758869 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213196.799667 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213196.799667 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211044.721585 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211044.721585 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5712890 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856017 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1248 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5713060 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2856101 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1990 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1247 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1247 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2559702 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2559783 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9624 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 956425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1459802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 818923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 22 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091718 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 956411 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1460482 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 820279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1461167 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1091716 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4381906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4219310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8601216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186932672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041565 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 329974237 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 423215 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3296619 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001032 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.032108 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4382756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4220664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8603420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 186981696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143041437 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 330023133 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 423201 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3296691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001034 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.032145 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3293217 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3402 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3293281 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3410 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3296619 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5168164000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3296691 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5168333000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2191892463 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2192017465 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2105680997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2105681496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -983,39 +971,39 @@ system.iobus.pkt_size_system.bridge.master::total 44381 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705989 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5423500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5419000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 784500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 786000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 186500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 186000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14813500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14810500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2308500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5938000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5936500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 98500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215092991 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215720167 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23492000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.290814 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.290842 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1748612865000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.290814 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080676 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080676 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1748612862000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.290842 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080678 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080678 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1029,14 +1017,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21944383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21944383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429292608 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5429292608 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21944383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21944383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21944383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21944383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21917383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21917383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244742784 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244742784 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21917383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21917383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21917383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21917383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1053,19 +1041,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126846.144509 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126846.144509 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130662.606084 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130662.606084 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 126846.144509 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 126846.144509 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 126846.144509 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 77 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126690.075145 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 126690.075145 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126221.187524 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126221.187524 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 126690.075145 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 126690.075145 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.833333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1079,14 +1067,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13294383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13294383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351692608 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351692608 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13294383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13294383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13294383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13294383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13267383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13267383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165341974 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13267383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13267383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13267383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13267383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1095,63 +1083,62 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76846.144509 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80662.606084 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80662.606084 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76846.144509 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76846.144509 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76690.075145 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.848816 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76690.075145 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76690.075145 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6934 # Transaction distribution system.membus.trans_dist::ReadResp 295622 # Transaction distribution system.membus.trans_dist::WriteReq 9624 # Transaction distribution system.membus.trans_dist::WriteResp 9624 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118174 # Transaction distribution -system.membus.trans_dist::CleanEvict 262081 # Transaction distribution -system.membus.trans_dist::UpgradeReq 178 # Transaction distribution -system.membus.trans_dist::UpgradeResp 178 # Transaction distribution -system.membus.trans_dist::ReadExReq 116499 # Transaction distribution -system.membus.trans_dist::ReadExResp 116499 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288704 # Transaction distribution -system.membus.trans_dist::BadAddressError 16 # Transaction distribution +system.membus.trans_dist::WritebackDirty 118173 # Transaction distribution +system.membus.trans_dist::CleanEvict 262241 # Transaction distribution +system.membus.trans_dist::UpgradeReq 175 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 116498 # Transaction distribution +system.membus.trans_dist::ReadExResp 116498 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 288705 # Transaction distribution +system.membus.trans_dist::BadAddressError 17 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33116 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148839 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181987 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1306804 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148657 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181807 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1265232 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44381 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809792 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854173 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30809664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30854045 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33511901 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33511773 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 843925 # Request fanout histogram +system.membus.snoop_fanout::samples 843910 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 843925 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 843910 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 843925 # Request fanout histogram -system.membus.reqLayer0.occupancy 29573500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 843910 # Request fanout histogram +system.membus.reqLayer0.occupancy 29565500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319381154 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1319337462 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160244574 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2159897250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69858432 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 123211008..1b3e8deca 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.922762 # Number of seconds simulated -sim_ticks 1922761887500 # Number of ticks simulated -final_tick 1922761887500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.924156 # Number of seconds simulated +sim_ticks 1924156135000 # Number of ticks simulated +final_tick 1924156135000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136693 # Simulator instruction rate (inst/s) -host_op_rate 136693 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4632993573 # Simulator tick rate (ticks/s) -host_mem_usage 339884 # Number of bytes of host memory used -host_seconds 415.02 # Real time elapsed on the host -sim_insts 56729467 # Number of instructions simulated -sim_ops 56729467 # Number of ops (including micro ops) simulated +host_inst_rate 131013 # Simulator instruction rate (inst/s) +host_op_rate 131013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4442767791 # Simulator tick rate (ticks/s) +host_mem_usage 340636 # Number of bytes of host memory used +host_seconds 433.10 # Real time elapsed on the host +sim_insts 56741431 # Number of instructions simulated +sim_ops 56741431 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 869760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24778624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 103040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 515712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 858624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24610432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 114304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 675520 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26268096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 869760 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 103040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 972800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7882944 # Number of bytes written to this memory -system.physmem.bytes_written::total 7882944 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8058 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26259840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 858624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 114304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 972928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7862976 # Number of bytes written to this memory +system.physmem.bytes_written::total 7862976 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 384538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10555 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410439 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123171 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 452349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12886996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 268214 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 410310 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122859 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122859 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 446234 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12790247 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 59405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 351073 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13661648 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 452349 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53590 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4099803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4099803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4099803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 452349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12886996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53590 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 268214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13647458 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 446234 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 59405 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505639 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4086454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4086454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4086454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 446234 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12790247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 59405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 351073 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17761450 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410439 # Number of read requests accepted -system.physmem.writeReqs 123171 # Number of write requests accepted -system.physmem.readBursts 410439 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123171 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26260800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue -system.physmem.bytesWritten 7881088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26268096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7882944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17733912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410310 # Number of read requests accepted +system.physmem.writeReqs 122859 # Number of write requests accepted +system.physmem.readBursts 410310 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122859 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26253184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 7861568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26259840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7862976 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 309493 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25497 # Per bank write bursts -system.physmem.perBankRdBursts::1 25956 # Per bank write bursts -system.physmem.perBankRdBursts::2 26004 # Per bank write bursts -system.physmem.perBankRdBursts::3 25724 # Per bank write bursts -system.physmem.perBankRdBursts::4 25504 # Per bank write bursts -system.physmem.perBankRdBursts::5 25939 # Per bank write bursts -system.physmem.perBankRdBursts::6 25634 # Per bank write bursts -system.physmem.perBankRdBursts::7 25247 # Per bank write bursts -system.physmem.perBankRdBursts::8 25446 # Per bank write bursts -system.physmem.perBankRdBursts::9 25836 # Per bank write bursts -system.physmem.perBankRdBursts::10 25660 # Per bank write bursts -system.physmem.perBankRdBursts::11 25037 # Per bank write bursts -system.physmem.perBankRdBursts::12 26054 # Per bank write bursts -system.physmem.perBankRdBursts::13 25864 # Per bank write bursts -system.physmem.perBankRdBursts::14 25329 # Per bank write bursts -system.physmem.perBankRdBursts::15 25594 # Per bank write bursts -system.physmem.perBankWrBursts::0 8072 # Per bank write bursts -system.physmem.perBankWrBursts::1 8040 # Per bank write bursts -system.physmem.perBankWrBursts::2 8032 # Per bank write bursts -system.physmem.perBankWrBursts::3 7672 # Per bank write bursts -system.physmem.perBankWrBursts::4 7388 # Per bank write bursts -system.physmem.perBankWrBursts::5 7843 # Per bank write bursts -system.physmem.perBankWrBursts::6 7702 # Per bank write bursts -system.physmem.perBankWrBursts::7 7083 # Per bank write bursts -system.physmem.perBankWrBursts::8 7329 # Per bank write bursts -system.physmem.perBankWrBursts::9 7600 # Per bank write bursts -system.physmem.perBankWrBursts::10 7538 # Per bank write bursts -system.physmem.perBankWrBursts::11 7420 # Per bank write bursts -system.physmem.perBankWrBursts::12 7961 # Per bank write bursts -system.physmem.perBankWrBursts::13 8153 # Per bank write bursts -system.physmem.perBankWrBursts::14 7615 # Per bank write bursts -system.physmem.perBankWrBursts::15 7694 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26222 # Per bank write bursts +system.physmem.perBankRdBursts::1 25818 # Per bank write bursts +system.physmem.perBankRdBursts::2 25998 # Per bank write bursts +system.physmem.perBankRdBursts::3 25425 # Per bank write bursts +system.physmem.perBankRdBursts::4 25236 # Per bank write bursts +system.physmem.perBankRdBursts::5 25660 # Per bank write bursts +system.physmem.perBankRdBursts::6 25903 # Per bank write bursts +system.physmem.perBankRdBursts::7 25509 # Per bank write bursts +system.physmem.perBankRdBursts::8 25730 # Per bank write bursts +system.physmem.perBankRdBursts::9 25899 # Per bank write bursts +system.physmem.perBankRdBursts::10 25820 # Per bank write bursts +system.physmem.perBankRdBursts::11 25243 # Per bank write bursts +system.physmem.perBankRdBursts::12 25580 # Per bank write bursts +system.physmem.perBankRdBursts::13 25319 # Per bank write bursts +system.physmem.perBankRdBursts::14 25297 # Per bank write bursts +system.physmem.perBankRdBursts::15 25547 # Per bank write bursts +system.physmem.perBankWrBursts::0 8465 # Per bank write bursts +system.physmem.perBankWrBursts::1 7798 # Per bank write bursts +system.physmem.perBankWrBursts::2 8098 # Per bank write bursts +system.physmem.perBankWrBursts::3 7477 # Per bank write bursts +system.physmem.perBankWrBursts::4 7191 # Per bank write bursts +system.physmem.perBankWrBursts::5 7211 # Per bank write bursts +system.physmem.perBankWrBursts::6 7415 # Per bank write bursts +system.physmem.perBankWrBursts::7 7062 # Per bank write bursts +system.physmem.perBankWrBursts::8 7370 # Per bank write bursts +system.physmem.perBankWrBursts::9 7621 # Per bank write bursts +system.physmem.perBankWrBursts::10 7713 # Per bank write bursts +system.physmem.perBankWrBursts::11 7334 # Per bank write bursts +system.physmem.perBankWrBursts::12 7954 # Per bank write bursts +system.physmem.perBankWrBursts::13 8039 # Per bank write bursts +system.physmem.perBankWrBursts::14 8051 # Per bank write bursts +system.physmem.perBankWrBursts::15 8038 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 1922757529500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 1924155087500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410439 # Read request sizes (log2) +system.physmem.readPktSize::6 410310 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123171 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122859 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318040 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29346 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,199 +158,187 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 45 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 522.654583 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 319.374945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 410.670236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14914 22.83% 22.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11338 17.36% 40.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5449 8.34% 48.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2879 4.41% 52.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2604 3.99% 56.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1649 2.52% 59.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3829 5.86% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1203 1.84% 67.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21459 32.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65324 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5559 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.810757 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2831.423020 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5556 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6798 # What write queue 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+system.physmem.wrQLenPdf::36 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65042 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 524.503429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 321.000815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 410.854297 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14739 22.66% 22.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11347 17.45% 40.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5326 8.19% 48.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2916 4.48% 52.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2591 3.98% 56.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1650 2.54% 59.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3760 5.78% 65.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1191 1.83% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21522 33.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65042 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5512 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.419267 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2843.464031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5509 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5559 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5559 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.151826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.921629 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.873132 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4760 85.63% 85.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 185 3.33% 88.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.47% 89.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 178 3.20% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 6 0.11% 92.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.31% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 0.81% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.07% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 15 0.27% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.36% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.09% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 23 0.41% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.40% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 34 0.61% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 96.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 160 2.88% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.04% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.20% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5559 # Writes before turning the bus around for reads -system.physmem.totQLat 4493146250 # Total ticks spent queuing -system.physmem.totMemAccLat 12186740000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2051625000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10950.21 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5512 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5512 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.285377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.129455 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.189692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4905 88.99% 88.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 46 0.83% 89.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 19 0.34% 90.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 46 0.83% 91.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 202 3.66% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 8 0.15% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 9 0.16% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 26 0.47% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 191 3.47% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.09% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 3 0.05% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 9 0.16% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.09% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 8 0.15% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 4 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5512 # Writes before turning the bus around for reads +system.physmem.totQLat 4435069250 # Total ticks spent queuing +system.physmem.totMemAccLat 12126431750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2051030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10811.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29700.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29561.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.48 # Average write queue length when enqueuing -system.physmem.readRowHits 369435 # Number of row buffer hits during reads -system.physmem.writeRowHits 98708 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.14 # Row buffer hit rate for writes -system.physmem.avgGap 3603301.16 # Average gap between requests -system.physmem.pageHitRate 87.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247227120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134895750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1602939000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 400671360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63448746300 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1097999321250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1289419132860 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.608398 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1826411929500 # Time in different power states -system.physmem_0.memoryStateTime::REF 64205180000 # Time in different power states +system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing +system.physmem.readRowHits 369385 # Number of row buffer hits during reads +system.physmem.writeRowHits 98616 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.27 # Row buffer hit rate for writes +system.physmem.avgGap 3608902.78 # Average gap between requests +system.physmem.pageHitRate 87.79 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 245503440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133955250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1605013800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 393446160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 63335469060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1098934930500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1290324682530 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.593273 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1827969159500 # Time in different power states +system.physmem_0.memoryStateTime::REF 64251720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32143098000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31933066750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 246622320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 134565750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597596000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 397288800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125585332080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62799950070 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1098568432500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1289329787520 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.561935 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1827364757000 # Time in different power states -system.physmem_1.memoryStateTime::REF 64205180000 # Time in different power states +system.physmem_1.actEnergy 246214080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 134343000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1594593000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 402537600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125676364320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 62736550965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1099460297250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1290250900215 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.554927 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1828845452000 # Time in different power states +system.physmem_1.memoryStateTime::REF 64251720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 31190256750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31056774250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16164803 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14134057 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 313974 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10204663 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5324382 # Number of BTB hits +system.cpu0.branchPred.lookups 15943421 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13949758 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 305064 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 10079074 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5240379 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 52.175971 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 806868 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17359 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 51.992663 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 792227 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17177 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9175640 # DTB read hits -system.cpu0.dtb.read_misses 32141 # DTB read misses -system.cpu0.dtb.read_acv 535 # DTB read access violations -system.cpu0.dtb.read_accesses 683139 # DTB read accesses -system.cpu0.dtb.write_hits 5880520 # DTB write hits -system.cpu0.dtb.write_misses 7287 # DTB write misses -system.cpu0.dtb.write_acv 388 # DTB write access violations -system.cpu0.dtb.write_accesses 235457 # DTB write accesses -system.cpu0.dtb.data_hits 15056160 # DTB hits -system.cpu0.dtb.data_misses 39428 # DTB misses -system.cpu0.dtb.data_acv 923 # DTB access violations -system.cpu0.dtb.data_accesses 918596 # DTB accesses -system.cpu0.itb.fetch_hits 1432352 # ITB hits -system.cpu0.itb.fetch_misses 20066 # ITB misses -system.cpu0.itb.fetch_acv 603 # ITB acv -system.cpu0.itb.fetch_accesses 1452418 # ITB accesses +system.cpu0.dtb.read_hits 9007287 # DTB read hits +system.cpu0.dtb.read_misses 30074 # DTB read misses +system.cpu0.dtb.read_acv 538 # DTB read access violations +system.cpu0.dtb.read_accesses 622567 # DTB read accesses +system.cpu0.dtb.write_hits 5740520 # DTB write hits +system.cpu0.dtb.write_misses 6136 # DTB write misses +system.cpu0.dtb.write_acv 351 # DTB write access violations +system.cpu0.dtb.write_accesses 205436 # DTB write accesses +system.cpu0.dtb.data_hits 14747807 # DTB hits +system.cpu0.dtb.data_misses 36210 # DTB misses +system.cpu0.dtb.data_acv 889 # DTB access violations +system.cpu0.dtb.data_accesses 828003 # DTB accesses +system.cpu0.itb.fetch_hits 1373369 # ITB hits +system.cpu0.itb.fetch_misses 18540 # ITB misses +system.cpu0.itb.fetch_acv 561 # ITB acv +system.cpu0.itb.fetch_accesses 1391909 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -363,598 +351,596 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 147492353 # number of cpu cycles simulated +system.cpu0.numCycles 146208045 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26474452 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70295181 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16164803 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6131250 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 112660359 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1056864 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 660 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 29689 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 929577 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 461648 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8123308 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 229143 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 141085167 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.498246 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.734224 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26065681 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 69138767 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 15943421 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6032606 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 111931288 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1030760 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 960 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 29091 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 863166 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 466353 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7979260 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 223234 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 139872418 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.494299 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.727987 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 127941692 90.68% 90.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 834789 0.59% 91.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1813592 1.29% 92.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 779670 0.55% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2595829 1.84% 94.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 572321 0.41% 95.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 651682 0.46% 95.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 825551 0.59% 96.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5070041 3.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 126942613 90.76% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 822727 0.59% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1793626 1.28% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 758856 0.54% 93.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2553230 1.83% 94.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559004 0.40% 95.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 640050 0.46% 95.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 814516 0.58% 96.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4987796 3.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 141085167 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.109598 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.476602 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21397283 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 108970346 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8457985 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1766417 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 493135 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 516601 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 35757 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 61523415 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 108836 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 493135 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22231622 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 77943613 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19948481 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9304003 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11164311 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 59421431 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 199471 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2023547 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 224227 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 7186744 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 39708144 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72284783 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72145352 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 129802 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34979364 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4728772 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1463848 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 211077 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12544775 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9257817 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6153108 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1360057 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1005705 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53010076 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1876155 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52220777 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 51551 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6501431 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2875308 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1291728 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 141085167 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.370137 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.087516 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 139872418 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.109046 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472879 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21051176 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 108291493 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8312277 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1736520 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 480951 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 505721 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 34877 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 60486220 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 106478 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 480951 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21868372 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 77772833 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 19641346 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9147803 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10961111 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 58426169 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 200234 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2003921 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 229197 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 7028864 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39061354 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 71018610 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 70882139 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 127236 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34481529 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4579825 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1435923 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 207898 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12319734 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9087403 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6005193 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1334507 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 982358 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 52110504 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1852436 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 51364410 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50265 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6320051 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2764098 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1275155 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 139872418 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.367223 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.083437 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 119616695 84.78% 84.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9300562 6.59% 91.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3865352 2.74% 94.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2730572 1.94% 96.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2821393 2.00% 98.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1375831 0.98% 99.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 902270 0.64% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 360488 0.26% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 112004 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 118742134 84.89% 84.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9166235 6.55% 91.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3802026 2.72% 94.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2678681 1.92% 96.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2780722 1.99% 98.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1354022 0.97% 99.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 885059 0.63% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 353584 0.25% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109955 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 141085167 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 139872418 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 182068 18.38% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.38% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 471621 47.60% 65.98% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 337015 34.02% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 178057 18.55% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 457973 47.71% 66.26% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 323912 33.74% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35835168 68.62% 68.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56519 0.11% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28571 0.05% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9523186 18.24% 87.03% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5952100 11.40% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 819570 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 3341 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35317882 68.76% 68.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56025 0.11% 68.88% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.88% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27459 0.05% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1664 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9346041 18.20% 87.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5809377 11.31% 98.44% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 802621 1.56% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52220777 # Type of FU issued -system.cpu0.iq.rate 0.354058 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 990706 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018971 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 245998342 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61137250 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50831283 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 570635 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 267757 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 262095 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 52900146 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 307557 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 581308 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 51364410 # Type of FU issued +system.cpu0.iq.rate 0.351310 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 959944 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018689 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 243048711 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 60036028 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50017442 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 562736 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 263720 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 258274 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52017534 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 303479 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 574771 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1065241 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3900 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 17685 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 500436 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1026959 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3812 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17061 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 487007 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18736 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 408207 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18708 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 390954 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 493135 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 74418027 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1058724 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58259520 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 116565 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9257817 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6153108 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1657861 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39988 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 817674 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 17685 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 153306 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 351909 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 505215 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51717296 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9230924 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 503480 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 480951 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 74383875 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 944737 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 57300574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 113056 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9087403 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6005193 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1637090 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39248 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 704660 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17061 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 148957 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 344315 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 493272 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 50873166 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9059669 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 491244 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3373289 # number of nop insts executed -system.cpu0.iew.exec_refs 15132335 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8216790 # Number of branches executed -system.cpu0.iew.exec_stores 5901411 # Number of stores executed -system.cpu0.iew.exec_rate 0.350644 # Inst execution rate -system.cpu0.iew.wb_sent 51207379 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51093378 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26334208 # num instructions producing a value -system.cpu0.iew.wb_consumers 36473947 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.346414 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.722001 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 6824843 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 584427 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 463110 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 139880833 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.366966 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.256019 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 3337634 # number of nop insts executed +system.cpu0.iew.exec_refs 14819622 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8093106 # Number of branches executed +system.cpu0.iew.exec_stores 5759953 # Number of stores executed +system.cpu0.iew.exec_rate 0.347951 # Inst execution rate +system.cpu0.iew.wb_sent 50383521 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 50275716 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25952077 # num instructions producing a value +system.cpu0.iew.wb_consumers 35940166 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.343864 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.722091 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 6643709 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 577281 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 452311 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 138699255 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.364540 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.252346 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 121749360 87.04% 87.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7187615 5.14% 92.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3944064 2.82% 95.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2051216 1.47% 96.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1611429 1.15% 97.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 577022 0.41% 98.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 437359 0.31% 98.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 434985 0.31% 98.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1887783 1.35% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 120842585 87.13% 87.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7068214 5.10% 92.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3896866 2.81% 95.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2026273 1.46% 96.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1580895 1.14% 97.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 566091 0.41% 98.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 426311 0.31% 98.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 427447 0.31% 98.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1864573 1.34% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 139880833 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51331530 # Number of instructions committed -system.cpu0.commit.committedOps 51331530 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 138699255 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 50561379 # Number of instructions committed +system.cpu0.commit.committedOps 50561379 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13845248 # Number of memory references committed -system.cpu0.commit.loads 8192576 # Number of loads committed -system.cpu0.commit.membars 198790 # Number of memory barriers committed -system.cpu0.commit.branches 7761926 # Number of branches committed -system.cpu0.commit.fp_insts 259003 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47542487 # Number of committed integer instructions. -system.cpu0.commit.function_calls 656882 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2950502 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33426097 65.12% 70.87% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55327 0.11% 70.97% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.97% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28109 0.05% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.03% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8391366 16.35% 87.38% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5658677 11.02% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 819569 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13578630 # Number of memory references committed +system.cpu0.commit.loads 8060444 # Number of loads committed +system.cpu0.commit.membars 196368 # Number of memory barriers committed +system.cpu0.commit.branches 7652854 # Number of branches committed +system.cpu0.commit.fp_insts 255352 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 46813547 # Number of committed integer instructions. +system.cpu0.commit.function_calls 647795 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2921820 5.78% 5.78% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32972422 65.21% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 54875 0.11% 71.10% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.10% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 26997 0.05% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1664 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.16% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8256812 16.33% 87.49% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5524169 10.93% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 802620 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51331530 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1887783 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 195948573 # The number of ROB reads -system.cpu0.rob.rob_writes 117511436 # The number of ROB writes -system.cpu0.timesIdled 525574 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 6407186 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3698031423 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48384795 # Number of Instructions Simulated -system.cpu0.committedOps 48384795 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 3.048320 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.048320 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.328050 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.328050 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67995096 # number of integer regfile reads -system.cpu0.int_regfile_writes 36974255 # number of integer regfile writes -system.cpu0.fp_regfile_reads 128760 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130249 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1711265 # number of misc regfile reads -system.cpu0.misc_regfile_writes 819270 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1282737 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.160385 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10524244 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1283249 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.201249 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 50561379 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1864573 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 193850877 # The number of ROB reads +system.cpu0.rob.rob_writes 115577492 # The number of ROB writes +system.cpu0.timesIdled 518122 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 6335627 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701455446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 47642888 # Number of Instructions Simulated +system.cpu0.committedOps 47642888 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 3.068833 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.068833 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.325857 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.325857 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66867100 # number of integer regfile reads +system.cpu0.int_regfile_writes 36418674 # number of integer regfile writes +system.cpu0.fp_regfile_reads 126247 # number of floating regfile reads +system.cpu0.fp_regfile_writes 127860 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1687235 # number of misc regfile reads +system.cpu0.misc_regfile_writes 805033 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1264949 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.087207 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10332814 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1265389 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.165721 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.160385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988595 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988595 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56891628 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56891628 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6483780 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6483780 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3678701 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3678701 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 162607 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 162607 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 187520 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 187520 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10162481 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10162481 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10162481 # number of overall hits -system.cpu0.dcache.overall_hits::total 10162481 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1594725 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1594725 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1768883 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1768883 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21044 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21044 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2856 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2856 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3363608 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3363608 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3363608 # number of overall misses -system.cpu0.dcache.overall_misses::total 3363608 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54836064000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54836064000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 114300477543 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114300477543 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389087500 # number of LoadLockedReq miss cycles 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-system.cpu0.dcache.WriteReq_accesses::total 5447584 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183651 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183651 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 190376 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 190376 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13526089 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13526089 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13526089 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13526089 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197403 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197403 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.324710 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.324710 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114587 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114587 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248676 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248676 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248676 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248676 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34385.906034 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 34385.906034 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64617.319259 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 64617.319259 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18489.236837 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18489.236837 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15934.873950 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15934.873950 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50284.260694 # average overall miss latency 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accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7933235 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5315810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5315810 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 180683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 180683 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187866 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 187866 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13249045 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13249045 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13249045 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13249045 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197862 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.197862 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.319076 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.319076 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114051 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114051 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015399 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015399 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.246496 # miss rate for demand accesses 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+system.cpu0.dcache.avg_blocked_cycles::no_targets 139.791667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 756067 # number of writebacks -system.cpu0.dcache.writebacks::total 756067 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 579442 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 579442 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1502906 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1502906 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5209 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5209 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2082348 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2082348 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2082348 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2082348 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1015283 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1015283 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265977 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 265977 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15835 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15835 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2856 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2856 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1281260 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1281260 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1281260 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1281260 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7045 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7045 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10126 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10126 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17171 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17171 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43465523500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43465523500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 18235926784 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18235926784 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 187455000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 187455000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 42654000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 42654000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61701450284 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 61701450284 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61701450284 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 61701450284 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1562510000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1562510000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2299016000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2299016000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3861526000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3861526000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125677 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125677 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048825 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048825 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086223 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086223 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094725 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094725 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094725 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 42811.239329 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 42811.239329 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68562.044026 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68562.044026 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.017051 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.017051 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14934.873950 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14934.873950 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48156.853632 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221789.921930 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221789.921930 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227040.884851 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227040.884851 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224886.494671 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224886.494671 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 742386 # number of writebacks +system.cpu0.dcache.writebacks::total 742386 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 562218 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 562218 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1439926 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1439926 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4884 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4884 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2002144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2002144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2002144 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2002144 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1007465 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1007465 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 256223 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 256223 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15723 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15723 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2893 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2893 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1263688 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1263688 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1263688 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1263688 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7031 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7031 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10093 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10093 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17124 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17124 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43361344000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43361344000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 17653250388 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 17653250388 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 186143500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 186143500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 41712000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 41712000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61014594388 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 61014594388 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 61014594388 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 61014594388 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1559676000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1559676000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293857500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293857500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3853533500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3853533500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.126993 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.126993 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048200 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048200 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087020 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087020 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015399 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.095380 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095380 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.095380 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 43040.050027 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 43040.050027 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 68897.992717 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68897.992717 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11838.930230 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11838.930230 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14418.250951 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14418.250951 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 48282.957809 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221828.473901 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221828.473901 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227272.119291 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227272.119291 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 225036.994861 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225036.994861 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 908501 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.069795 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7168696 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 909010 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.886267 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 894689 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.080310 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7039625 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 895201 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.863737 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 42372449500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.069795 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992324 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9032627 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9032627 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7168696 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7168696 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7168696 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7168696 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7168696 # number of overall hits -system.cpu0.icache.overall_hits::total 7168696 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 954611 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 954611 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 954611 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 954611 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 954611 # number of overall misses -system.cpu0.icache.overall_misses::total 954611 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14637521487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14637521487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14637521487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14637521487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14637521487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14637521487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8123307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8123307 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8123307 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8123307 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8123307 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8123307 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117515 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117515 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117515 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117515 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117515 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117515 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15333.493420 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15333.493420 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15333.493420 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15333.493420 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15333.493420 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8572 # number of cycles access was blocked +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.080310 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992344 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992344 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8874714 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8874714 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7039625 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7039625 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7039625 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7039625 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7039625 # number of overall hits +system.cpu0.icache.overall_hits::total 7039625 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 939633 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 939633 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 939633 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 939633 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 939633 # number of overall misses +system.cpu0.icache.overall_misses::total 939633 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14412797481 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14412797481 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14412797481 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14412797481 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14412797481 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14412797481 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7979258 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7979258 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7979258 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7979258 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7979258 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7979258 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117759 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.117759 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117759 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.117759 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117759 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.117759 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15338.751918 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15338.751918 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15338.751918 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15338.751918 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15338.751918 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9737 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 278 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 297 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.834532 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 32.784512 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 908501 # number of writebacks -system.cpu0.icache.writebacks::total 908501 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45291 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 45291 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 45291 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 45291 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 45291 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 45291 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909320 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 909320 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 909320 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 909320 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 909320 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 909320 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12935759993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12935759993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12935759993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12935759993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12935759993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12935759993 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111940 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111940 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111940 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111940 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14225.751103 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14225.751103 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14225.751103 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 894689 # number of writebacks +system.cpu0.icache.writebacks::total 894689 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44177 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44177 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 44177 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44177 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 44177 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44177 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895456 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 895456 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 895456 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 895456 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 895456 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 895456 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12742984487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 12742984487 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12742984487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 12742984487 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12742984487 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12742984487 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112223 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112223 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112223 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112223 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14230.720981 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14230.720981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14230.720981 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3578846 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3133511 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63586 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2063930 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 845641 # Number of BTB hits +system.cpu1.branchPred.lookups 3770405 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3287478 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 72852 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2172402 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 929208 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 40.972368 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 169933 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4992 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 42.773299 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 184259 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5155 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1885255 # DTB read hits -system.cpu1.dtb.read_misses 9531 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 285831 # DTB read accesses -system.cpu1.dtb.write_hits 1175917 # DTB write hits -system.cpu1.dtb.write_misses 2028 # DTB write misses -system.cpu1.dtb.write_acv 35 # DTB write access violations -system.cpu1.dtb.write_accesses 108552 # DTB write accesses -system.cpu1.dtb.data_hits 3061172 # DTB hits -system.cpu1.dtb.data_misses 11559 # DTB misses -system.cpu1.dtb.data_acv 40 # DTB access violations -system.cpu1.dtb.data_accesses 394383 # DTB accesses -system.cpu1.itb.fetch_hits 516958 # ITB hits -system.cpu1.itb.fetch_misses 4674 # ITB misses -system.cpu1.itb.fetch_acv 66 # ITB acv -system.cpu1.itb.fetch_accesses 521632 # ITB accesses +system.cpu1.dtb.read_hits 2058998 # DTB read hits +system.cpu1.dtb.read_misses 11600 # DTB read misses +system.cpu1.dtb.read_acv 21 # DTB read access violations +system.cpu1.dtb.read_accesses 345698 # DTB read accesses +system.cpu1.dtb.write_hits 1317225 # DTB write hits +system.cpu1.dtb.write_misses 3094 # DTB write misses +system.cpu1.dtb.write_acv 53 # DTB write access violations +system.cpu1.dtb.write_accesses 138357 # DTB write accesses +system.cpu1.dtb.data_hits 3376223 # DTB hits +system.cpu1.dtb.data_misses 14694 # DTB misses +system.cpu1.dtb.data_acv 74 # DTB access violations +system.cpu1.dtb.data_accesses 484055 # DTB accesses +system.cpu1.itb.fetch_hits 573986 # ITB hits +system.cpu1.itb.fetch_misses 6844 # ITB misses +system.cpu1.itb.fetch_acv 105 # ITB acv +system.cpu1.itb.fetch_accesses 580830 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -967,564 +953,568 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 15151136 # number of cpu cycles simulated +system.cpu1.numCycles 16344557 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 6180932 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13745317 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3578846 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1015574 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7699604 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 257606 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 14 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25107 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 173727 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 62622 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 6567420 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 14895137 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3770405 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1113467 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 8326976 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 284690 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 333 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 274833 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 63331 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1537985 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 51060 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 14270827 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.963176 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.372632 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 1681040 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 57489 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 15400785 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.967167 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.371525 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 11867377 83.16% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 153441 1.08% 84.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 242213 1.70% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 178756 1.25% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 307848 2.16% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 121777 0.85% 90.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 138851 0.97% 91.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 186713 1.31% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1073851 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 12783684 83.01% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 166452 1.08% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 261215 1.70% 85.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 200313 1.30% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 351067 2.28% 89.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 133990 0.87% 90.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 151147 0.98% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 199120 1.29% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1153797 7.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 14270827 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.236210 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.907214 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5071818 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 7138589 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1741534 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 196274 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 122611 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 106199 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 6268 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 11163667 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19967 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 122611 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5211151 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 520290 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5613443 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1798962 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1004368 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10604371 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4257 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 67823 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18974 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 511038 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6965041 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12634725 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12576141 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52884 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5956129 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1008912 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 437815 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 40748 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1803693 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1932664 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1246799 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 224198 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 128085 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 9340268 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 503829 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 9138713 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20420 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1499424 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 677663 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 370337 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 14270827 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.640377 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.363961 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 15400785 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.230683 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.911321 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 5395420 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 7755332 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1888719 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 226049 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 135264 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 116204 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 7167 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 12211095 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 22842 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 135264 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 5551383 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 663921 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5888186 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1958901 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1203128 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 11612321 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 4312 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 84745 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20732 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 660077 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 7621170 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 13919150 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 13857621 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 55424 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 6464282 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1156880 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 465120 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 44099 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2006629 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2105779 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1396456 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 250989 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 150424 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 10250493 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 528025 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 10010931 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 21465 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1679970 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 786543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 387236 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 15400785 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.650027 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.374650 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 10455091 73.26% 73.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1683189 11.79% 85.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 712225 4.99% 90.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 493511 3.46% 93.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 444759 3.12% 96.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 238311 1.67% 98.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 152079 1.07% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65820 0.46% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 25842 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 11244282 73.01% 73.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1815288 11.79% 84.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 776099 5.04% 89.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 545502 3.54% 93.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 489702 3.18% 96.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 259974 1.69% 98.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 169251 1.10% 99.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 72741 0.47% 99.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 27946 0.18% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 14270827 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 15400785 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22910 9.24% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.24% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 135436 54.62% 63.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 89607 36.14% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26802 9.62% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 149738 53.73% 63.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 102168 36.66% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5683316 62.19% 62.23% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 16216 0.18% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.41% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10845 0.12% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.52% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1965659 21.51% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1197875 13.11% 97.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 259525 2.84% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3957 0.04% 0.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 6209301 62.03% 62.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 16861 0.17% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.23% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 11959 0.12% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1978 0.02% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2148593 21.46% 83.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1341864 13.40% 97.24% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 276418 2.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 9138713 # Type of FU issued -system.cpu1.iq.rate 0.603170 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 247953 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.027132 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 32611679 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 11249940 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8808383 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 204947 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 97488 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 94992 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 9273516 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 109632 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94173 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 10010931 # Type of FU issued +system.cpu1.iq.rate 0.612493 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 278708 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027840 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 35509985 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 12361464 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 9636562 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 212834 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 101438 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 98868 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 10172012 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 113670 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 100974 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 262201 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 474 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 4003 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 124065 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 300733 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 901 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4546 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 138575 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 413 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 65383 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 436 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 85477 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 122611 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 306675 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 177978 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 10362316 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 27137 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1932664 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1246799 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 457137 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4115 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 173001 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 4003 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 29001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 94231 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 123232 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 9024161 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1901420 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 114552 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 135264 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 341224 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 281245 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 11333478 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 30763 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2105779 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1396456 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 478482 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4958 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 275268 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4546 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 33466 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 102178 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 135644 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 9885056 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2078095 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 125874 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 518219 # number of nop insts executed -system.cpu1.iew.exec_refs 3085060 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1341299 # Number of branches executed -system.cpu1.iew.exec_stores 1183640 # Number of stores executed -system.cpu1.iew.exec_rate 0.595610 # Inst execution rate -system.cpu1.iew.wb_sent 8932335 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8903375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4245423 # num instructions producing a value -system.cpu1.iew.wb_consumers 6036438 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.587637 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703299 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1526496 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 133492 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 112683 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 13989586 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.626917 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.604217 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 554960 # number of nop insts executed +system.cpu1.iew.exec_refs 3404439 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1465257 # Number of branches executed +system.cpu1.iew.exec_stores 1326344 # Number of stores executed +system.cpu1.iew.exec_rate 0.604792 # Inst execution rate +system.cpu1.iew.wb_sent 9770196 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 9735430 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4636977 # num instructions producing a value +system.cpu1.iew.wb_consumers 6583946 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.595637 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.704285 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1707241 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 140789 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 123833 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 15089302 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.633097 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.610231 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 10816267 77.32% 77.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1467149 10.49% 87.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 531154 3.80% 91.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 320114 2.29% 93.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 241905 1.73% 95.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 101551 0.73% 96.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 91287 0.65% 97.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 103861 0.74% 97.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 316298 2.26% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 11642359 77.16% 77.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1582874 10.49% 87.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 578528 3.83% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 347459 2.30% 93.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 270616 1.79% 95.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 111368 0.74% 96.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 102382 0.68% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 112638 0.75% 97.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 341078 2.26% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 13989586 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8770307 # Number of instructions committed -system.cpu1.commit.committedOps 8770307 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 15089302 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 9552993 # Number of instructions committed +system.cpu1.commit.committedOps 9552993 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2793197 # Number of memory references committed -system.cpu1.commit.loads 1670463 # Number of loads committed -system.cpu1.commit.membars 42427 # Number of memory barriers committed -system.cpu1.commit.branches 1252873 # Number of branches committed -system.cpu1.commit.fp_insts 93374 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 8120952 # Number of committed integer instructions. -system.cpu1.commit.function_calls 139980 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 429153 4.89% 4.89% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 5216835 59.48% 64.38% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16050 0.18% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10839 0.12% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.68% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.70% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1712890 19.53% 84.23% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1123256 12.81% 97.04% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 259525 2.96% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3062927 # Number of memory references committed +system.cpu1.commit.loads 1805046 # Number of loads committed +system.cpu1.commit.membars 44912 # Number of memory barriers committed +system.cpu1.commit.branches 1363215 # Number of branches committed +system.cpu1.commit.fp_insts 97092 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 8861525 # Number of committed integer instructions. +system.cpu1.commit.function_calls 149395 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 458406 4.80% 4.80% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5679268 59.45% 64.25% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 16577 0.17% 64.42% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.42% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 11953 0.13% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.55% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1978 0.02% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1849958 19.37% 83.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1258435 13.17% 97.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 276418 2.89% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8770307 # Class of committed instruction -system.cpu1.commit.bw_lim_events 316298 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 23885701 # The number of ROB reads -system.cpu1.rob.rob_writes 20870962 # The number of ROB writes -system.cpu1.timesIdled 125875 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 880309 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3829642661 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 8344672 # Number of Instructions Simulated -system.cpu1.committedOps 8344672 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.815666 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.815666 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550762 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550762 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11618114 # number of integer regfile reads -system.cpu1.int_regfile_writes 6343189 # number of integer regfile writes -system.cpu1.fp_regfile_reads 52190 # number of floating regfile reads -system.cpu1.fp_regfile_writes 51516 # number of floating regfile writes -system.cpu1.misc_regfile_reads 503472 # number of misc regfile reads -system.cpu1.misc_regfile_writes 210349 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 98962 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.970752 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2466427 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 99271 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.845393 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048837181500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.970752 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951115 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.951115 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 309 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.603516 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11541624 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11541624 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1517477 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1517477 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 889696 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 889696 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 32286 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 32286 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 29965 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 29965 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2407173 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2407173 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2407173 # number of overall hits -system.cpu1.dcache.overall_hits::total 2407173 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 186675 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 186675 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 194181 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 194181 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4996 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4996 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2988 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2988 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 380856 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 380856 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 380856 # number of overall misses -system.cpu1.dcache.overall_misses::total 380856 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2524860000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2524860000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9140210329 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 9140210329 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 47601500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 47601500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 47681500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 47681500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 11665070329 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 11665070329 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 11665070329 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 11665070329 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1704152 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1704152 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1083877 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1083877 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 37282 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 37282 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 32953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 32953 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2788029 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2788029 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2788029 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2788029 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.109541 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.109541 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.179154 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.179154 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134006 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134006 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090675 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090675 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136604 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.136604 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136604 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.136604 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13525.431900 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13525.431900 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 47070.569876 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 47070.569876 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9527.922338 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9527.922338 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15957.663989 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15957.663989 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30628.558639 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30628.558639 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 30628.558639 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 543818 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1735 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 16052 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.878520 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 173.500000 # average number of cycles each access was blocked +system.cpu1.commit.op_class_0::total 9552993 # Class of committed instruction +system.cpu1.commit.bw_lim_events 341078 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 25912274 # The number of ROB reads +system.cpu1.rob.rob_writes 22828201 # The number of ROB writes +system.cpu1.timesIdled 132318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 943772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3831967714 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 9098543 # Number of Instructions Simulated +system.cpu1.committedOps 9098543 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.796393 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.796393 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.556671 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.556671 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 12770865 # number of integer regfile reads +system.cpu1.int_regfile_writes 6910748 # number of integer regfile writes +system.cpu1.fp_regfile_reads 54739 # number of floating regfile reads +system.cpu1.fp_regfile_writes 53934 # number of floating regfile writes +system.cpu1.misc_regfile_reads 528553 # number of misc regfile reads +system.cpu1.misc_regfile_writes 224621 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 116660 # number of replacements +system.cpu1.dcache.tags.tagsinuse 487.079416 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2668588 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 117172 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 22.774963 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048837209000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.079416 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.951327 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.951327 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12701896 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12701896 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1640446 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1640446 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 950506 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 950506 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 34609 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 34609 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 32422 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 32422 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2590952 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2590952 # number of demand (read+write) hits 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15240312278 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15240312278 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15240312278 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15240312278 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1852140 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1852140 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1216285 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1216285 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 39971 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 39971 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 35465 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 35465 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3068425 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3068425 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3068425 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3068425 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.114297 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.114297 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.218517 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.218517 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134147 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134147 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085803 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.085803 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.155608 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.155608 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.155608 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.155608 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13263.373076 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13263.373076 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 46777.720505 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 46777.720505 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9780.399105 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9780.399105 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15269.635228 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15269.635228 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31918.689178 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31918.689178 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31918.689178 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 748281 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 2150 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 22290 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 12 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 33.570256 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 179.166667 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 64059 # number of writebacks -system.cpu1.dcache.writebacks::total 64059 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 113306 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 113306 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 159042 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 159042 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 272348 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 272348 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 272348 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 272348 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 73369 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 73369 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 35139 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 35139 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4523 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4523 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2988 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2988 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 108508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 108508 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 108508 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 108508 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 150 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 150 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2931 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2931 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3081 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3081 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 931066500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 931066500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1566203053 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1566203053 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38495000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38495000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 44693500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 44693500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2497269553 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2497269553 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2497269553 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2497269553 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30161500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30161500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 685230000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 685230000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 715391500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 715391500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.043053 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.043053 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032420 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032420 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121319 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121319 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.090675 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.090675 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038919 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038919 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038919 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12690.189317 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12690.189317 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44571.645551 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44571.645551 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8510.944064 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8510.944064 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14957.663989 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14957.663989 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23014.612314 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201076.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201076.666667 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 233787.103378 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 233787.103378 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 232194.579682 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 232194.579682 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 77506 # number of writebacks +system.cpu1.dcache.writebacks::total 77506 # number of writebacks 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number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 162 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 162 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2978 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2978 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3140 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3140 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1028731500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1028731500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2065280441 # number of WriteReq MSHR miss cycles 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12622.472393 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12622.472393 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46060.940296 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 46060.940296 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8675.312302 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8675.312302 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14274.654832 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14274.654832 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24489.955049 # average overall mshr miss latency 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231175 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 223833 # number of replacements -system.cpu1.icache.tags.tagsinuse 467.351638 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1306354 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 224343 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 5.823021 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1896743746500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 467.351638 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.912796 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.912796 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1762389 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1762389 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1306354 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1306354 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1306354 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1306354 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1306354 # number of overall hits -system.cpu1.icache.overall_hits::total 1306354 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 231631 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 231631 # number of ReadReq misses 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accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1537985 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1537985 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1537985 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1537985 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1537985 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.150607 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.150607 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.150607 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.150607 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.150607 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.150607 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14382.509250 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14382.509250 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14382.509250 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14382.509250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14382.509250 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14382.509250 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 764 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 236774 # number of replacements +system.cpu1.icache.tags.tagsinuse 467.367156 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1435165 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 237286 # Sample count of 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access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 223833 # number of writebacks -system.cpu1.icache.writebacks::total 223833 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 7227 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 7227 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 7227 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 7227 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 7227 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 7227 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 224404 # number of ReadReq MSHR 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overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.219568 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13357.219568 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 236774 # number of writebacks +system.cpu1.icache.writebacks::total 236774 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8521 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8521 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8521 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8521 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8521 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8521 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 237354 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 237354 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 237354 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 237354 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 237354 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 237354 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3178535500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3178535500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3178535500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3178535500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3178535500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3178535500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.141195 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.141195 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.141195 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.141195 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13391.539641 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13391.539641 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13391.539641 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1538,12 +1528,12 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7371 # Transaction distribution -system.iobus.trans_dist::ReadResp 7371 # Transaction distribution -system.iobus.trans_dist::WriteReq 54609 # Transaction distribution -system.iobus.trans_dist::WriteResp 54609 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7368 # Transaction distribution +system.iobus.trans_dist::ReadResp 7368 # Transaction distribution +system.iobus.trans_dist::WriteReq 54623 # Transaction distribution +system.iobus.trans_dist::WriteResp 54623 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1551,12 +1541,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 1814 system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40504 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40528 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123982 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2701 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1564,72 +1554,72 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73842 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735474 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12353500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 73938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2735562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12379500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 827500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 818500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 177000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14420500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14310000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5954500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5965001 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 87000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215061495 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215710405 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27447000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41952000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.507724 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.518954 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1726981783000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.507724 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.031733 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.031733 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1726981777000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.518954 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.032435 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.032435 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses -system.iocache.demand_misses::total 176 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 176 # number of overall misses -system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22155383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22155383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5431231112 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5431231112 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22155383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22155383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22155383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22155383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 23088383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 23088383 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5246547022 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5246547022 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 23088383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 23088383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 23088383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 23088383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1638,40 +1628,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125882.857955 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125882.857955 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130709.258568 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130709.258568 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125882.857955 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125882.857955 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125882.857955 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 131933.617143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 131933.617143 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126264.608731 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126264.608731 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131933.617143 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 131933.617143 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131933.617143 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 1 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.411765 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 0 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13355383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13355383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353631112 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3353631112 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13355383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13355383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13355383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13355383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14338383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 14338383 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3167138735 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3167138735 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 14338383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 14338383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 14338383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 14338383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1680,199 +1670,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75882.857955 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80709.258568 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80709.258568 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75882.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75882.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 81933.617143 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76221.090080 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76221.090080 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 81933.617143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 81933.617143 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345304 # number of replacements -system.l2c.tags.tagsinuse 65190.216881 # Cycle average of tags in use -system.l2c.tags.total_refs 3990482 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410468 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.721786 # Average number of references to valid blocks. +system.l2c.tags.replacements 345132 # number of replacements +system.l2c.tags.tagsinuse 65190.773198 # Cycle average of tags in use +system.l2c.tags.total_refs 3987579 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 410285 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.719047 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 11177481000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53120.456317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5260.305264 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6531.960119 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 208.754945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 68.740237 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.810554 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 53112.873337 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5260.284322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6538.875697 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 210.626415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 68.113427 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.810438 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.080266 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.099670 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.001049 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994724 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1730 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6556 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50377 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38372212 # Number of tag accesses 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number of overall hits -system.l2c.overall_hits::cpu1.inst 222750 # number of overall hits -system.l2c.overall_hits::cpu1.data 89258 # number of overall hits -system.l2c.overall_hits::total 2099666 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2766 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1119 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3885 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 420 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 441 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114874 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7330 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122204 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13592 # number of ReadCleanReq misses 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UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1368 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4306 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 471 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 466 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 937 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 270204 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 30168 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300372 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 909038 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 224378 # number of ReadCleanReq accesses(hits+misses) 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accesses -system.l2c.overall_accesses::cpu1.inst 224378 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 97417 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2510895 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941457 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.817982 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.902229 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.891720 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.946352 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.918890 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.425138 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.242973 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.406842 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.014952 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.007256 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013428 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.270311 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.012327 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.254204 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014952 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.302993 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007256 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.083753 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.163778 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014952 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.302993 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007256 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.083753 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.163778 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1417.932032 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15593.386953 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 5500.900901 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6767.857143 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1289.115646 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3961.672474 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 139637.668228 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 159170.190996 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 140809.261563 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 133709.792525 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135052.211302 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 133853.383706 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 124160.748564 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140913.148372 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 124211.469842 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 129500.655353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 133709.792525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 128744.726054 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 135052.211302 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 157315.173428 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 129500.655353 # average overall miss latency +system.l2c.tags.occ_percent::cpu0.data 0.099775 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001039 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994732 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65153 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 4362 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5957 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 51615 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994156 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 38355291 # Number of tag accesses +system.l2c.tags.data_accesses 38355291 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 819892 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 819892 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 858364 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 858364 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 165 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 273 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 438 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 47 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 77 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 148311 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 29871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 178182 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 881771 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 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31166738507 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 110342008 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 31277080515 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1658755004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 45601453507 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 223319004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1590103526 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 49073631041 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1658755004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 45601453507 # number of overall MSHR miss cycles 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accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.918890 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425138 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242973 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.406842 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013412 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270311 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.012327 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254204 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.163770 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014951 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.302993 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007175 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.083753 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.163770 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71726.319595 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71754.691689 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71734.491634 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71313.095238 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71783.446712 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71554.006969 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129637.668228 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 149170.190996 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130809.261563 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123868.199461 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114196.885440 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130913.148372 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114247.497306 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123709.955117 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118770.159856 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125204.037267 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 147315.173428 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 119524.990881 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209281.405252 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 188496.666667 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208848.088951 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215520.738692 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 221655.237120 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216897.794287 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212960.835129 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 220040.895813 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214037.946869 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.943299 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.805278 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.898423 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.899573 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935897 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.917735 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.430716 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.247506 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.406491 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013424 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272479 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.011126 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254224 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.305136 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.092772 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.163781 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014988 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.305136 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007526 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.092772 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.163781 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68903.825137 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 69046.944198 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68945.534331 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68539.192399 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68930.365297 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68738.649593 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128639.037171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 150611.859338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 130408.047773 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123796.224956 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 114173.496328 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131830.356033 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114227.470162 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 118387.523773 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 149137.453198 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119385.166976 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123630.841768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 118387.523773 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125038.636058 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 149137.453198 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119385.166976 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209320.011378 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 186126.543210 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208797.650494 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215752.154959 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 220821.188717 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216907.046133 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213111.159776 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 219031.210191 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214028.498816 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 296301 # Transaction distribution -system.membus.trans_dist::WriteReq 13057 # Transaction distribution -system.membus.trans_dist::WriteResp 13057 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123171 # Transaction distribution -system.membus.trans_dist::CleanEvict 262771 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10335 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5768 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5173 # Transaction distribution -system.membus.trans_dist::ReadExReq 122191 # Transaction distribution -system.membus.trans_dist::ReadExResp 121777 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289182 # Transaction distribution +system.membus.trans_dist::ReadReq 7193 # Transaction distribution +system.membus.trans_dist::ReadResp 296309 # Transaction distribution +system.membus.trans_dist::WriteReq 13071 # Transaction distribution +system.membus.trans_dist::WriteResp 13071 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122859 # Transaction distribution +system.membus.trans_dist::CleanEvict 263080 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10389 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5858 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 122048 # Transaction distribution +system.membus.trans_dist::ReadExResp 121637 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289192 # Transaction distribution system.membus.trans_dist::BadAddressError 76 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40504 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1187227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40528 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181775 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 152 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1227883 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124828 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1352711 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73842 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31492800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31566642 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1222455 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1305892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73938 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31464576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31538514 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34224882 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 11791 # Total snoops (count) -system.membus.snoop_fanout::samples 875399 # Request fanout histogram +system.membus.pkt_size::total 34196754 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 11972 # Total snoops (count) +system.membus.snoop_fanout::samples 875257 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 875399 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 875257 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 875399 # Request fanout histogram -system.membus.reqLayer0.occupancy 36670000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 875257 # Request fanout histogram +system.membus.reqLayer0.occupancy 36588499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1357207403 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1355446474 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 98500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 101000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2187691105 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2176763250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69834733 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 924363 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 5063738 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2531809 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 339719 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1340 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5062297 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2530952 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 339931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1332 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1264 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2239104 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13057 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13057 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 943311 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 859282 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 775827 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10329 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5844 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16173 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301707 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301707 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1133724 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1098277 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7193 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2238586 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13071 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13071 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 942766 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1131462 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 825685 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 10428 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5935 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 16363 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 301553 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 301553 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1132810 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1098675 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 76 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2546826 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3860959 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 579596 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 310532 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7297913 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 104800384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130368640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22732288 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10357298 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 268258610 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 462469 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2998699 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.119628 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.324813 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2685333 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3847367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 711442 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373868 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7618010 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114552128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128359012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30341632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 12338926 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 285591698 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462928 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2998059 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.119755 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.324954 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2640250 88.05% 88.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 358173 11.94% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 274 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2639295 88.03% 88.03% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 358495 11.96% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 268 0.01% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2998699 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4501023919 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2998059 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4499211916 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 297385 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 295885 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1365634171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1344759827 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1954807358 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1928238108 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 338746615 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 358125739 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 168528157 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 195506142 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2164,161 +2153,170 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6529 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 184433 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65060 40.50% 40.50% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1928 1.20% 41.78% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 186 0.12% 41.90% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 93335 58.10% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 160640 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64056 49.21% 49.21% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1928 1.48% 50.79% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 186 0.14% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 63870 49.07% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 130171 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865608787500 97.03% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 63996500 0.00% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 577908500 0.03% 97.06% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 88293000 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 56422061000 2.93% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1922761046500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984568 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6521 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 181676 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 64229 40.40% 40.40% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.08% 40.49% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1930 1.21% 41.70% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 188 0.12% 41.82% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 92486 58.18% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 158964 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 63227 49.20% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1930 1.50% 50.80% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 188 0.15% 50.95% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 63039 49.05% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 128515 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1866746585000 97.03% 97.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 63847000 0.00% 97.04% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 578525000 0.03% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 89345000 0.00% 97.07% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 56353429000 2.93% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1923831731000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.984400 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684309 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810327 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.51% 3.51% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.33% 11.84% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.75% 13.60% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.47% 28.07% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 28.51% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.95% 32.46% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.39% 36.84% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.63% 39.47% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.44% 39.91% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.32% 41.23% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.07% 44.30% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 45.18% # number of syscalls executed -system.cpu0.kern.syscall::45 36 15.79% 60.96% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.32% 62.28% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.39% 66.67% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.39% 71.05% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 71.49% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.63% 74.12% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.84% 85.96% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.32% 87.28% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.07% 90.35% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.32% 92.11% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.95% 96.05% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.93% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.81% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.44% 98.25% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 228 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.681606 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.808453 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 7 3.65% 3.65% # number of syscalls executed +system.cpu0.kern.syscall::3 16 8.33% 11.98% # number of syscalls executed +system.cpu0.kern.syscall::4 4 2.08% 14.06% # number of syscalls executed +system.cpu0.kern.syscall::6 28 14.58% 28.65% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.52% 29.17% # number of syscalls executed +system.cpu0.kern.syscall::17 8 4.17% 33.33% # number of syscalls executed +system.cpu0.kern.syscall::19 7 3.65% 36.98% # number of syscalls executed +system.cpu0.kern.syscall::20 4 2.08% 39.06% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.52% 39.58% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.56% 41.15% # number of syscalls executed +system.cpu0.kern.syscall::33 6 3.12% 44.27% # number of syscalls executed +system.cpu0.kern.syscall::41 2 1.04% 45.31% # number of syscalls executed +system.cpu0.kern.syscall::45 31 16.15% 61.46% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.56% 63.02% # number of syscalls executed +system.cpu0.kern.syscall::48 8 4.17% 67.19% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.69% 71.88% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.52% 72.40% # number of syscalls executed +system.cpu0.kern.syscall::59 6 3.12% 75.52% # number of syscalls executed +system.cpu0.kern.syscall::71 21 10.94% 86.46% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.56% 88.02% # number of syscalls executed +system.cpu0.kern.syscall::74 5 2.60% 90.62% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.52% 91.15% # number of syscalls executed +system.cpu0.kern.syscall::90 2 1.04% 92.19% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.65% 95.83% # number of syscalls executed +system.cpu0.kern.syscall::97 2 1.04% 96.88% # number of syscalls executed +system.cpu0.kern.syscall::98 2 1.04% 97.92% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.52% 98.44% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.52% 98.96% # number of syscalls executed +system.cpu0.kern.syscall::147 2 1.04% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 192 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed +system.cpu0.kern.callpal::wripir 288 0.17% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3530 2.09% 2.26% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.29% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed -system.cpu0.kern.callpal::swpipl 153808 90.93% 93.22% # number of callpals executed -system.cpu0.kern.callpal::rdps 6346 3.75% 96.97% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.97% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.98% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu0.kern.callpal::rti 4586 2.71% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 386 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 169154 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7135 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1348 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3442 2.06% 2.23% # number of callpals executed +system.cpu0.kern.callpal::tbi 49 0.03% 2.26% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.27% # number of callpals executed +system.cpu0.kern.callpal::swpipl 152297 91.02% 93.29% # number of callpals executed +system.cpu0.kern.callpal::rdps 6331 3.78% 97.07% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.07% # number of callpals executed +system.cpu0.kern.callpal::wrusp 2 0.00% 97.07% # number of callpals executed +system.cpu0.kern.callpal::rdusp 8 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.08% # number of callpals executed +system.cpu0.kern.callpal::rti 4417 2.64% 99.72% # number of callpals executed +system.cpu0.kern.callpal::callsys 330 0.20% 99.92% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 167317 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6879 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1175 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1347 -system.cpu0.kern.mode_good::user 1348 +system.cpu0.kern.mode_good::kernel 1175 +system.cpu0.kern.mode_good::user 1175 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188788 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170810 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317694 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1920558467500 99.89% 99.89% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2202571000 0.11% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.291780 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1921452590000 99.89% 99.89% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2041385500 0.11% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3531 # number of times the context was actually changed +system.cpu0.kern.swap_context 3443 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2548 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 55289 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 17293 36.54% 36.54% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1926 4.07% 40.61% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 284 0.60% 41.21% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 27821 58.79% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 47324 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16920 47.31% 47.31% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1926 5.39% 52.69% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 284 0.79% 53.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 16636 46.51% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 35766 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1875921374000 97.58% 97.58% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 562894500 0.03% 97.61% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 139598000 0.01% 97.62% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 45773010000 2.38% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1922396876500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.978431 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2563 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 58062 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 18132 36.97% 36.97% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1928 3.93% 40.90% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 288 0.59% 41.49% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 28696 58.51% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 49044 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 17757 47.43% 47.43% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1928 5.15% 52.57% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 288 0.77% 53.34% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 17469 46.66% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 37442 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1877611262500 97.58% 97.58% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 563601000 0.03% 97.61% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 141411000 0.01% 97.62% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 45839038500 2.38% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1924155313000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.979318 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.597966 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.755769 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 11 11.22% 11.22% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.18% 20.41% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.02% 21.43% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.12% 27.55% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.06% 30.61% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.06% 33.67% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.08% 37.76% # number of syscalls executed -system.cpu1.kern.syscall::45 18 18.37% 56.12% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.06% 59.18% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.02% 60.20% # number of syscalls executed -system.cpu1.kern.syscall::71 27 27.55% 87.76% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.18% 96.94% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.06% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 98 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.608761 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.763437 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 1 0.75% 0.75% # number of syscalls executed +system.cpu1.kern.syscall::3 14 10.45% 11.19% # number of syscalls executed +system.cpu1.kern.syscall::6 14 10.45% 21.64% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.75% 22.39% # number of syscalls executed +system.cpu1.kern.syscall::17 7 5.22% 27.61% # number of syscalls executed +system.cpu1.kern.syscall::19 3 2.24% 29.85% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.49% 31.34% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.24% 33.58% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.24% 35.82% # number of syscalls executed +system.cpu1.kern.syscall::33 5 3.73% 39.55% # number of syscalls executed +system.cpu1.kern.syscall::45 23 17.16% 56.72% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.24% 58.96% # number of syscalls executed +system.cpu1.kern.syscall::48 2 1.49% 60.45% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.75% 61.19% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.75% 61.94% # number of syscalls executed +system.cpu1.kern.syscall::71 33 24.63% 86.57% # number of syscalls executed +system.cpu1.kern.syscall::74 11 8.21% 94.78% # number of syscalls executed +system.cpu1.kern.syscall::90 1 0.75% 95.52% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.49% 97.01% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.24% 99.25% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.75% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 134 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 186 0.38% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.39% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1060 2.16% 2.55% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.56% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 42140 86.06% 88.63% # number of callpals executed -system.cpu1.kern.callpal::rdps 2415 4.93% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.58% # number of callpals executed -system.cpu1.kern.callpal::rti 2973 6.07% 99.65% # number of callpals executed -system.cpu1.kern.callpal::callsys 129 0.26% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 188 0.37% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1149 2.26% 2.64% # number of callpals executed +system.cpu1.kern.callpal::tbi 4 0.01% 2.64% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.66% # number of callpals executed +system.cpu1.kern.callpal::swpipl 43675 85.89% 88.55% # number of callpals executed +system.cpu1.kern.callpal::rdps 2435 4.79% 93.34% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.34% # number of callpals executed +system.cpu1.kern.callpal::wrusp 5 0.01% 93.35% # number of callpals executed +system.cpu1.kern.callpal::rdusp 1 0.00% 93.35% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.35% # number of callpals executed +system.cpu1.kern.callpal::rti 3152 6.20% 99.55% # number of callpals executed +system.cpu1.kern.callpal::callsys 185 0.36% 99.92% # number of callpals executed +system.cpu1.kern.callpal::imb 41 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 48967 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1257 # number of protection mode switches -system.cpu1.kern.mode_switch::user 391 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2415 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 600 -system.cpu1.kern.mode_good::user 391 -system.cpu1.kern.mode_good::idle 209 -system.cpu1.kern.mode_switch_good::kernel 0.477327 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 50850 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1515 # number of protection mode switches +system.cpu1.kern.mode_switch::user 561 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2424 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 773 +system.cpu1.kern.mode_good::user 561 +system.cpu1.kern.mode_good::idle 212 +system.cpu1.kern.mode_switch_good::kernel 0.510231 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.086542 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.295348 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 4412319000 0.23% 0.23% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 702202000 0.04% 0.27% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1916962357500 99.73% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1061 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.087459 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.343556 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4865757000 0.25% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 846470000 0.04% 0.30% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1918443078000 99.70% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1150 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index f6eb98841..28bcd517c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.875760 # Number of seconds simulated -sim_ticks 1875760362000 # Number of ticks simulated -final_tick 1875760362000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.875758 # Number of seconds simulated +sim_ticks 1875758115500 # Number of ticks simulated +final_tick 1875758115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137394 # Simulator instruction rate (inst/s) -host_op_rate 137394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4864266040 # Simulator tick rate (ticks/s) -host_mem_usage 335280 # Number of bytes of host memory used -host_seconds 385.62 # Real time elapsed on the host -sim_insts 52982087 # Number of instructions simulated -sim_ops 52982087 # Number of ops (including micro ops) simulated +host_inst_rate 136821 # Simulator instruction rate (inst/s) +host_op_rate 136821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4844017901 # Simulator tick rate (ticks/s) +host_mem_usage 335520 # Number of bytes of host memory used +host_seconds 387.23 # Real time elapsed on the host +sim_insts 52981544 # Number of instructions simulated +sim_ops 52981544 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 958208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24881088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24881024 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25840256 # Number of bytes read from this memory +system.physmem.bytes_read::total 25840192 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 958208 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 958208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7524736 # Number of bytes written to this memory -system.physmem.bytes_written::total 7524736 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7524864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7524864 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 14972 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388766 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403754 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117574 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117574 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 510837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13264534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403753 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117576 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117576 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 510838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13264516 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13775883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 510837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 510837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4011566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4011566 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4011566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 510837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13264534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13775866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 510838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 510838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4011639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4011639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4011639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 510838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13264516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403754 # Number of read requests accepted -system.physmem.writeReqs 117574 # Number of write requests accepted -system.physmem.readBursts 403754 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117574 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25832192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523264 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25840256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7524736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17787505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403753 # Number of read requests accepted +system.physmem.writeReqs 117576 # Number of write requests accepted +system.physmem.readBursts 403753 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117576 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25832384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7523392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25840192 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7524864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303613 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25610 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25611 # Per bank write bursts system.physmem.perBankRdBursts::1 25424 # Per bank write bursts -system.physmem.perBankRdBursts::2 25555 # Per bank write bursts -system.physmem.perBankRdBursts::3 25501 # Per bank write bursts +system.physmem.perBankRdBursts::2 25556 # Per bank write bursts +system.physmem.perBankRdBursts::3 25503 # Per bank write bursts system.physmem.perBankRdBursts::4 25379 # Per bank write bursts -system.physmem.perBankRdBursts::5 24724 # Per bank write bursts +system.physmem.perBankRdBursts::5 24725 # Per bank write bursts system.physmem.perBankRdBursts::6 24941 # Per bank write bursts -system.physmem.perBankRdBursts::7 25082 # Per bank write bursts +system.physmem.perBankRdBursts::7 25083 # Per bank write bursts system.physmem.perBankRdBursts::8 24938 # Per bank write bursts -system.physmem.perBankRdBursts::9 25020 # Per bank write bursts -system.physmem.perBankRdBursts::10 25562 # Per bank write bursts +system.physmem.perBankRdBursts::9 25019 # Per bank write bursts +system.physmem.perBankRdBursts::10 25561 # Per bank write bursts system.physmem.perBankRdBursts::11 24881 # Per bank write bursts -system.physmem.perBankRdBursts::12 24459 # Per bank write bursts -system.physmem.perBankRdBursts::13 25275 # Per bank write bursts +system.physmem.perBankRdBursts::12 24458 # Per bank write bursts +system.physmem.perBankRdBursts::13 25273 # Per bank write bursts system.physmem.perBankRdBursts::14 25708 # Per bank write bursts -system.physmem.perBankRdBursts::15 25569 # Per bank write bursts -system.physmem.perBankWrBursts::0 7930 # Per bank write bursts +system.physmem.perBankRdBursts::15 25571 # Per bank write bursts +system.physmem.perBankWrBursts::0 7931 # Per bank write bursts system.physmem.perBankWrBursts::1 7523 # Per bank write bursts system.physmem.perBankWrBursts::2 7959 # Per bank write bursts -system.physmem.perBankWrBursts::3 7525 # Per bank write bursts +system.physmem.perBankWrBursts::3 7526 # Per bank write bursts system.physmem.perBankWrBursts::4 7322 # Per bank write bursts -system.physmem.perBankWrBursts::5 6662 # Per bank write bursts +system.physmem.perBankWrBursts::5 6664 # Per bank write bursts system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 6719 # Per bank write bursts +system.physmem.perBankWrBursts::7 6720 # Per bank write bursts system.physmem.perBankWrBursts::8 7147 # Per bank write bursts system.physmem.perBankWrBursts::9 6703 # Per bank write bursts -system.physmem.perBankWrBursts::10 7409 # Per bank write bursts -system.physmem.perBankWrBursts::11 6974 # Per bank write bursts -system.physmem.perBankWrBursts::12 7145 # Per bank write bursts +system.physmem.perBankWrBursts::10 7408 # Per bank write bursts +system.physmem.perBankWrBursts::11 6973 # Per bank write bursts +system.physmem.perBankWrBursts::12 7144 # Per bank write bursts system.physmem.perBankWrBursts::13 7893 # Per bank write bursts system.physmem.perBankWrBursts::14 8063 # Per bank write bursts system.physmem.perBankWrBursts::15 7807 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 1875755162500 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times write queue was full causing retry +system.physmem.totGap 1875752798500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403754 # Read request sizes (log2) +system.physmem.readPktSize::6 403753 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117574 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 315451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 35937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23972 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117576 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 315454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 35859 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24058 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 71 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -148,126 +148,116 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 78 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62200 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.255177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 330.514254 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 411.900658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13736 22.08% 22.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10542 16.95% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4957 7.97% 47.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2726 4.38% 51.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2468 3.97% 55.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1593 2.56% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3731 6.00% 63.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1159 1.86% 65.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21288 34.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62200 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5203 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.574092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2240.859569 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5198 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 21 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62096 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 537.164648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 331.293750 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 411.963299 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13665 22.01% 22.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10559 17.00% 39.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4854 7.82% 46.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2778 4.47% 51.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2418 3.89% 55.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1622 2.61% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3711 5.98% 63.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1214 1.96% 65.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21275 34.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62096 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.619423 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2241.505208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5195 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5203 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5203 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.592927 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.087485 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.896632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4449 85.51% 85.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 153 2.94% 88.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.29% 88.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 183 3.52% 92.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7 0.13% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.40% 92.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 39 0.75% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.02% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.19% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.33% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.12% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.15% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 19 0.37% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.52% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 31 0.60% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 95.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 162 3.11% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.13% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.08% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.08% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 10 0.19% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5203 # Writes before turning the bus around for reads -system.physmem.totQLat 4177261250 # Total ticks spent queuing -system.physmem.totMemAccLat 11745286250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10349.29 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5200 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.606346 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.258970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.077519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4603 88.52% 88.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 36 0.69% 89.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 24 0.46% 89.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 35 0.67% 90.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 205 3.94% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.21% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 15 0.29% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 35 0.67% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 175 3.37% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.12% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 7 0.13% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.04% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 1 0.02% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 11 0.21% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 6 0.12% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 4 0.08% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 7 0.13% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 3 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 3 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::344-351 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5200 # Writes before turning the bus around for reads +system.physmem.totQLat 4180311250 # Total ticks spent queuing +system.physmem.totMemAccLat 11748392500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10356.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29099.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29106.76 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.78 # Average system read bandwidth in MiByte/s @@ -276,72 +266,72 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.14 # Average write queue length when enqueuing -system.physmem.readRowHits 363742 # Number of row buffer hits during reads -system.physmem.writeRowHits 95236 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.00 # Row buffer hit rate for writes -system.physmem.avgGap 3598032.64 # Average gap between requests -system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232485120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126852000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1577284800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 378496800 # Energy for write commands per rank (pJ) +system.physmem.avgRdQLen 2.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing +system.physmem.readRowHits 363824 # Number of row buffer hits during reads +system.physmem.writeRowHits 95264 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.02 # Row buffer hit rate for writes +system.physmem.avgGap 3598021.21 # Average gap between requests +system.physmem.pageHitRate 88.08 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 232326360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126765375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577331600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 378529200 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61464969315 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1071536113500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1257831356895 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.573520 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1782393910500 # Time in different power states +system.physmem_0.actBackEnergy 61450630965 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1071548691000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1257829429860 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.572492 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1782417296500 # Time in different power states system.physmem_0.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30725132000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30701746000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 237746880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 129723000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570966800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383233680 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 237119400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129380625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1570990200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 383214240 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 122515155360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 61443954270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1071554556000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1257835335990 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.575636 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1782423204750 # Time in different power states +system.physmem_1.actBackEnergy 61460167635 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1071540333750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1257836361210 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.576183 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1782399409250 # Time in different power states system.physmem_1.memoryStateTime::REF 62635560000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30695851500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30719647000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17943792 # Number of BP lookups -system.cpu.branchPred.condPredicted 15652255 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 367731 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11526736 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5853565 # Number of BTB hits +system.cpu.branchPred.lookups 17926200 # Number of BP lookups +system.cpu.branchPred.condPredicted 15634549 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 367641 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11517888 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5853508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.782503 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 912127 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21143 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.821019 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 912312 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21142 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10250861 # DTB read hits -system.cpu.dtb.read_misses 41155 # DTB read misses -system.cpu.dtb.read_acv 533 # DTB read access violations -system.cpu.dtb.read_accesses 965519 # DTB read accesses -system.cpu.dtb.write_hits 6643163 # DTB write hits -system.cpu.dtb.write_misses 9679 # DTB write misses -system.cpu.dtb.write_acv 405 # DTB write access violations -system.cpu.dtb.write_accesses 341919 # DTB write accesses -system.cpu.dtb.data_hits 16894024 # DTB hits -system.cpu.dtb.data_misses 50834 # DTB misses -system.cpu.dtb.data_acv 938 # DTB access violations -system.cpu.dtb.data_accesses 1307438 # DTB accesses -system.cpu.itb.fetch_hits 1771509 # ITB hits -system.cpu.itb.fetch_misses 27218 # ITB misses -system.cpu.itb.fetch_acv 651 # ITB acv -system.cpu.itb.fetch_accesses 1798727 # ITB accesses +system.cpu.dtb.read_hits 10248777 # DTB read hits +system.cpu.dtb.read_misses 41124 # DTB read misses +system.cpu.dtb.read_acv 537 # DTB read access violations +system.cpu.dtb.read_accesses 965282 # DTB read accesses +system.cpu.dtb.write_hits 6643148 # DTB write hits +system.cpu.dtb.write_misses 9690 # DTB write misses +system.cpu.dtb.write_acv 398 # DTB write access violations +system.cpu.dtb.write_accesses 341994 # DTB write accesses +system.cpu.dtb.data_hits 16891925 # DTB hits +system.cpu.dtb.data_misses 50814 # DTB misses +system.cpu.dtb.data_acv 935 # DTB access violations +system.cpu.dtb.data_accesses 1307276 # DTB accesses +system.cpu.itb.fetch_hits 1767471 # ITB hits +system.cpu.itb.fetch_misses 28221 # ITB misses +system.cpu.itb.fetch_acv 656 # ITB acv +system.cpu.itb.fetch_accesses 1795692 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -354,251 +344,251 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 154312476 # number of cpu cycles simulated +system.cpu.numCycles 154296938 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29589797 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78040481 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17943792 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6765692 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115536731 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1228012 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1868 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 28793 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1263154 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 470523 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 558 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8990853 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 270749 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 147505430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.529069 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.785300 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29565992 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 77998562 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17926200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6765820 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115499750 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1227580 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1879 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 29906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1313604 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 470747 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 522 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8986717 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 269982 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 147496190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.528817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.784795 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 132981412 90.15% 90.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 927735 0.63% 90.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1956667 1.33% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 905252 0.61% 92.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2772062 1.88% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 613973 0.42% 95.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 725766 0.49% 95.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1009557 0.68% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5613006 3.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132977860 90.16% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 927689 0.63% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1955483 1.33% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 905427 0.61% 92.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2772003 1.88% 94.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 615447 0.42% 95.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 725348 0.49% 95.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1009173 0.68% 96.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5607760 3.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 147505430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116282 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.505730 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23997616 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 111589834 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9436408 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1909015 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 572556 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 581578 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 41802 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68051619 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 132447 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 572556 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24921470 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 78409233 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 21681516 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10334902 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11585751 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65629269 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204540 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2094492 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 230558 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7313834 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43742274 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79592762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79412105 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168205 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38181578 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5560688 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1689598 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 239417 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13566650 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10375081 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6952014 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1510108 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1095838 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58467936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2138049 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57495232 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57340 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7623893 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3407756 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1476849 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 147505430 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.389784 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.113628 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 147496190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116180 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.505509 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23986183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 111594322 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9434858 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1908489 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 572337 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 581608 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 41807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68042420 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 132440 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 572337 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24909467 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78381394 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 21682831 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10333745 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 11616414 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65623799 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 205401 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2094519 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 225742 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7349306 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43739456 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79586592 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79405874 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168265 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38181154 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5558294 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1689229 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 239421 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13564930 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10374266 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6952166 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1510457 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1094829 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58464384 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2137218 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57492092 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57307 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7620053 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3404147 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1476015 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 147496190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.389787 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.113704 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 123907632 84.00% 84.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10178942 6.90% 90.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4283791 2.90% 93.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3020718 2.05% 95.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3080788 2.09% 97.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1492274 1.01% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1011781 0.69% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 404686 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124818 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 123903149 84.00% 84.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10174594 6.90% 90.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4283554 2.90% 93.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3020095 2.05% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3079434 2.09% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1494296 1.01% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1011464 0.69% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 404727 0.27% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124877 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 147505430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 147496190 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 210139 18.65% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 541380 48.04% 66.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375310 33.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210492 18.68% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 541350 48.03% 66.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 375218 33.29% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7282 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39050510 67.92% 67.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61871 0.11% 68.04% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39049419 67.92% 67.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61870 0.11% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.04% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 38553 0.07% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10660993 18.54% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6723341 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949046 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10658869 18.54% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6723409 11.69% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 949053 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57495232 # Type of FU issued -system.cpu.iq.rate 0.372590 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1126829 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019599 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 262967275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67912541 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55849108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 712787 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336322 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 328951 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58232058 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 382721 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 635480 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57492092 # Type of FU issued +system.cpu.iq.rate 0.372607 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1127060 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019604 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 262951820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67904206 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55848058 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712920 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 336440 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329015 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58229078 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382791 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 635540 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1282102 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3336 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1281314 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3324 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19413 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 573763 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 573929 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 18204 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 460617 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 459106 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 572556 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 74664181 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1190404 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64295088 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139940 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10375081 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6952014 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1890561 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 43857 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 943603 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 572337 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 74665457 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1160593 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64290812 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139650 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10374266 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6952166 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1889682 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 913665 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19413 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 177030 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 409389 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 586419 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56909013 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10319700 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586218 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 176905 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 409384 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 586289 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56905925 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10317589 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 586166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3689103 # number of nop insts executed -system.cpu.iew.exec_refs 16987647 # number of memory reference insts executed -system.cpu.iew.exec_branches 8974028 # Number of branches executed -system.cpu.iew.exec_stores 6667947 # Number of stores executed -system.cpu.iew.exec_rate 0.368791 # Inst execution rate -system.cpu.iew.wb_sent 56315341 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56178059 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28756993 # num instructions producing a value -system.cpu.iew.wb_consumers 39942343 # num instructions consuming a value -system.cpu.iew.wb_rate 0.364054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.719963 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8005041 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661200 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 146102886 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.384475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.286214 # Number of insts commited each cycle +system.cpu.iew.exec_nop 3689210 # number of nop insts executed +system.cpu.iew.exec_refs 16985526 # number of memory reference insts executed +system.cpu.iew.exec_branches 8973539 # Number of branches executed +system.cpu.iew.exec_stores 6667937 # Number of stores executed +system.cpu.iew.exec_rate 0.368808 # Inst execution rate +system.cpu.iew.wb_sent 56314090 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56177073 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28757350 # num instructions producing a value +system.cpu.iew.wb_consumers 39943859 # num instructions consuming a value +system.cpu.iew.wb_rate 0.364084 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719944 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 8001816 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661203 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537200 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146094021 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.384495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.286335 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 126320849 86.46% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7855297 5.38% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4275062 2.93% 94.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2236701 1.53% 96.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1745224 1.19% 97.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 615726 0.42% 97.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 478400 0.33% 98.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 477555 0.33% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2098072 1.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 126314306 86.46% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7853790 5.38% 91.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4274774 2.93% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2236101 1.53% 96.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1744788 1.19% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615632 0.42% 97.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 478334 0.33% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 476966 0.33% 98.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2099330 1.44% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 146102886 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56172911 # Number of instructions committed -system.cpu.commit.committedOps 56172911 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146094021 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56172359 # Number of instructions committed +system.cpu.commit.committedOps 56172359 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471230 # Number of memory references committed -system.cpu.commit.loads 9092979 # Number of loads committed -system.cpu.commit.membars 226353 # Number of memory barriers committed -system.cpu.commit.branches 8440862 # Number of branches committed +system.cpu.commit.refs 15471189 # Number of memory references committed +system.cpu.commit.loads 9092952 # Number of loads committed +system.cpu.commit.membars 226351 # Number of memory barriers committed +system.cpu.commit.branches 8440746 # Number of branches committed system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52022252 # Number of committed integer instructions. -system.cpu.commit.function_calls 740590 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198097 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36219833 64.48% 70.17% # Class of committed instruction +system.cpu.commit.int_insts 52021709 # Number of committed integer instructions. +system.cpu.commit.function_calls 740586 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3198088 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36219325 64.48% 70.17% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 60677 0.11% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction @@ -627,34 +617,34 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319332 16.59% 86.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384206 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949045 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9319303 16.59% 86.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6384192 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 949053 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56172911 # Class of committed instruction -system.cpu.commit.bw_lim_events 2098072 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 207933116 # The number of ROB reads -system.cpu.rob.rob_writes 129754111 # The number of ROB writes -system.cpu.timesIdled 581360 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6807046 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3597208249 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52982087 # Number of Instructions Simulated -system.cpu.committedOps 52982087 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.912541 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.912541 # CPI: Total CPI of All Threads -system.cpu.ipc 0.343343 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.343343 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74569031 # number of integer regfile reads -system.cpu.int_regfile_writes 40527114 # number of integer regfile writes -system.cpu.fp_regfile_reads 166982 # number of floating regfile reads -system.cpu.fp_regfile_writes 167538 # number of floating regfile writes -system.cpu.misc_regfile_reads 1985520 # number of misc regfile reads -system.cpu.misc_regfile_writes 939432 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1401817 # number of replacements +system.cpu.commit.op_class_0::total 56172359 # Class of committed instruction +system.cpu.commit.bw_lim_events 2099330 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 207919346 # The number of ROB reads +system.cpu.rob.rob_writes 129746181 # The number of ROB writes +system.cpu.timesIdled 581168 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6800748 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3597219294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52981544 # Number of Instructions Simulated +system.cpu.committedOps 52981544 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.912277 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.912277 # CPI: Total CPI of All Threads +system.cpu.ipc 0.343374 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.343374 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74565581 # number of integer regfile reads +system.cpu.int_regfile_writes 40526554 # number of integer regfile writes +system.cpu.fp_regfile_reads 167056 # number of floating regfile reads +system.cpu.fp_regfile_writes 167536 # number of floating regfile writes +system.cpu.misc_regfile_reads 1985625 # number of misc regfile reads +system.cpu.misc_regfile_writes 939435 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1401792 # number of replacements system.cpu.dcache.tags.tagsinuse 511.992665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11831384 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1402329 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.436953 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 11831016 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1402304 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.436841 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 36569500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.992665 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy @@ -664,386 +654,386 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 system.cpu.dcache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63839342 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63839342 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7238802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7238802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4190242 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4190242 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186215 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186215 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215725 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215725 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11429044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11429044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11429044 # number of overall hits -system.cpu.dcache.overall_hits::total 11429044 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1797438 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1797438 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1957552 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1957552 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23250 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23250 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 63836509 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63836509 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7238578 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7238578 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4190111 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4190111 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186204 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186204 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215724 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215724 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11428689 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11428689 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11428689 # number of overall hits +system.cpu.dcache.overall_hits::total 11428689 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1796989 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1796989 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1957670 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1957670 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23246 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23246 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 29 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 29 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3754990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3754990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3754990 # number of overall misses -system.cpu.dcache.overall_misses::total 3754990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57215969500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57215969500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116801916611 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116801916611 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 447608000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 447608000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 892500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 892500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 174017886111 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 174017886111 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 174017886111 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 174017886111 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9036240 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9036240 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6147794 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6147794 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209465 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209465 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215754 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15184034 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15184034 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15184034 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15184034 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198914 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.198914 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318415 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318415 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110997 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110997 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 3754659 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3754659 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3754659 # number of overall misses +system.cpu.dcache.overall_misses::total 3754659 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57191537500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57191537500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 116815247150 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 116815247150 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 448333000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 448333000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 872000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 872000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 174006784650 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 174006784650 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 174006784650 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 174006784650 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9035567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9035567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6147781 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6147781 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209450 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209450 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215753 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215753 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15183348 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15183348 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15183348 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15183348 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198879 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198879 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318435 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318435 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.110986 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.110986 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000134 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000134 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247299 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247299 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247299 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247299 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31831.957208 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 31831.957208 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59667.337885 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 59667.337885 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19251.956989 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19251.956989 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30775.862069 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30775.862069 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46343.102408 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46343.102408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46343.102408 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46343.102408 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7142391 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 5288 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 134027 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.247288 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.247288 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.247288 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.247288 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31826.314741 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 31826.314741 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 59670.550782 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 59670.550782 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19286.457885 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19286.457885 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30068.965517 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30068.965517 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46344.231167 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46344.231167 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46344.231167 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7151643 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 5595 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 133832 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.290688 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 188.857143 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53.437466 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 199.821429 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 841132 # number of writebacks -system.cpu.dcache.writebacks::total 841132 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703605 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 703605 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666863 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1666863 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2370468 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2370468 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2370468 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2370468 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093833 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1093833 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290689 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 290689 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18017 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18017 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 841120 # number of writebacks +system.cpu.dcache.writebacks::total 841120 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 703166 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 703166 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1666991 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1666991 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5234 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5234 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2370157 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2370157 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2370157 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2370157 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1093823 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1093823 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290679 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290679 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18012 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 18012 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 29 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 29 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1384522 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1384522 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1384522 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1384522 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1384502 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1384502 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1384502 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1384502 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9598 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16528 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16528 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44560579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 44560579000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18438109720 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18438109720 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229318500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229318500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 863500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 863500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62998688720 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 62998688720 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62998688720 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 62998688720 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1529006000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1529006000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154205500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683211500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683211500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121050 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121050 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086014 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086014 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 44561431000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 44561431000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18441083775 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18441083775 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 229476500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 229476500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 843000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 843000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63002514775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63002514775 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63002514775 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63002514775 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1528979500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1528979500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2154218500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2154218500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3683198000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3683198000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.121057 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.121057 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047282 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047282 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085997 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085997 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000134 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000134 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091183 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091183 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091183 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40738.009367 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40738.009367 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63428.990158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63428.990158 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12727.895876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12727.895876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29775.862069 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29775.862069 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45502.121830 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45502.121830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45502.121830 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45502.121830 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220635.786436 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220635.786436 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224443.165243 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224443.165243 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222846.775169 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222846.775169 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091186 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091186 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091186 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40739.160723 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40739.160723 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63441.403662 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63441.403662 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12740.200977 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12740.200977 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 29068.965517 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 29068.965517 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45505.542625 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45505.542625 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220631.962482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220631.962482 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 224444.519692 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224444.519692 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 222845.958374 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 222845.958374 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1036100 # number of replacements -system.cpu.icache.tags.tagsinuse 507.835115 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7900592 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1036608 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.621581 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1035081 # number of replacements +system.cpu.icache.tags.tagsinuse 507.835100 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7897485 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1035589 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.626080 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 42318910500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.835115 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 507.835100 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.991865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.991865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 355 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10027831 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10027831 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7900593 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7900593 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7900593 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7900593 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7900593 # number of overall hits -system.cpu.icache.overall_hits::total 7900593 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1090257 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1090257 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1090257 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1090257 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1090257 # number of overall misses -system.cpu.icache.overall_misses::total 1090257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16373914482 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16373914482 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16373914482 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16373914482 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16373914482 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16373914482 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8990850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8990850 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8990850 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8990850 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8990850 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8990850 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121263 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121263 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121263 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121263 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121263 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121263 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15018.398856 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15018.398856 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15018.398856 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15018.398856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15018.398856 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15018.398856 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 11165 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10022677 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10022677 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7897486 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7897486 # number of ReadReq hits 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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129392.901975 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124682.194617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124682.194617 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114208.329073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114208.329073 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124682.194617 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118712.992236 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118934.033892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124682.194617 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118712.992236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118934.033892 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208125.036075 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208125.036075 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212939.049802 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212939.049802 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210920.589303 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210920.589303 # average overall mshr uncacheable latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014458 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248754 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248754 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165848 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014458 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165848 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 69118.811881 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 69118.811881 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129427.147964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129427.147964 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124563.280572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124563.280572 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114212.195238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114212.195238 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124563.280572 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118725.776852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118941.942729 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208121.212121 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208121.212121 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 212940.143780 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 212940.143780 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 210919.621249 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 210919.621249 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4877468 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2438381 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4875380 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2437337 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2172 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1198 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1198 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2144935 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2143899 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 958726 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1035549 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 821965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 958701 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1035081 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 823325 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 130 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 159 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1036981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301454 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035962 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1101105 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3109195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4238791 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7347986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132621696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143635700 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 276257396 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 422449 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2878056 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001305 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.036107 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3106690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4240094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7346784 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132526592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143633332 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 276159924 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 422430 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2876994 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001301 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.036051 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2874299 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3757 0.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2873250 99.87% 99.87% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3744 0.13% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2878056 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4329029000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2876994 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4326954000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556718501 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1555197985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2115441804 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2115406799 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1233,37 +1223,37 @@ system.iobus.pkt_size_system.bridge.master::total 44148 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5360000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 5356500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 826000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 825500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 179500 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14342000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 14331000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2178000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5944500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5952500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 88000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215036503 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215698160 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.249428 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.249420 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1725995793000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.249428 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1725995722000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.249420 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078089 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078089 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1281,8 +1271,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21806383 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21806383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5430705120 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5430705120 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245293777 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245293777 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21806383 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21806383 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21806383 # number of overall miss cycles @@ -1305,17 +1295,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126048.456647 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126048.456647 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130696.599923 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130696.599923 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126234.447848 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126234.447848 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency system.iocache.demand_avg_miss_latency::total 126048.456647 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 126048.456647 # average overall miss latency system.iocache.overall_avg_miss_latency::total 126048.456647 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 216 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 17 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.705882 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1331,8 +1321,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13156383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13156383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3353105120 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3353105120 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165897973 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165897973 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13156383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13156383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13156383 # number of overall MSHR miss cycles @@ -1347,62 +1337,61 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76048.456647 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80696.599923 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80696.599923 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.229616 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.229616 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 76048.456647 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76048.456647 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295855 # Transaction distribution +system.membus.trans_dist::ReadResp 295856 # Transaction distribution system.membus.trans_dist::WriteReq 9598 # Transaction distribution system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117574 # Transaction distribution -system.membus.trans_dist::CleanEvict 261706 # Transaction distribution -system.membus.trans_dist::UpgradeReq 351 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117576 # Transaction distribution +system.membus.trans_dist::CleanEvict 261861 # Transaction distribution +system.membus.trans_dist::UpgradeReq 350 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.membus.trans_dist::UpgradeResp 358 # Transaction distribution -system.membus.trans_dist::ReadExReq 115261 # Transaction distribution -system.membus.trans_dist::ReadExResp 115261 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289006 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 115259 # Transaction distribution +system.membus.trans_dist::ReadExResp 115259 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 289007 # Transaction distribution system.membus.trans_dist::BadAddressError 81 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1146220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145859 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179438 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1304255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1179077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1262502 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30707328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30751476 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33409140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33409204 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 842165 # Request fanout histogram +system.membus.snoop_fanout::samples 842145 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 842165 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 842145 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 842165 # Request fanout histogram -system.membus.reqLayer0.occupancy 28939500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 842145 # Request fanout histogram +system.membus.reqLayer0.occupancy 28932500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1314314398 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1314336715 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 106000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 105000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2139101639 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2138304000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69817453 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 911117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1436,28 +1425,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211011 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211012 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74664 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105567 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182242 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105568 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182243 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73297 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73297 49.32% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 148605 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818035845500 96.92% 96.92% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 64907500 0.00% 96.93% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 561478000 0.03% 96.96% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 57097305000 3.04% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1875759536000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1818034033000 96.92% 96.92% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 64890000 0.00% 96.93% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 561380500 0.03% 96.96% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 57096986000 3.04% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1875757289500 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694317 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815427 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694311 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815422 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1496,7 +1485,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175125 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175126 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1505,20 +1494,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191970 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.callpal::total 191971 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1909 +system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326269 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394011 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29997949500 1.60% 1.60% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2897677500 0.15% 1.75% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842863901000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29989573500 1.60% 1.60% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2896538000 0.15% 1.75% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842871170000 98.25% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 190a0b7d0..1e558125c 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,21 +4,21 @@ sim_seconds 1.843590 # Nu sim_ticks 1843589966000 # Number of ticks simulated final_tick 1843589966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221527 # Simulator instruction rate (inst/s) -host_op_rate 221527 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5683484333 # Simulator tick rate (ticks/s) -host_mem_usage 334252 # Number of bytes of host memory used -host_seconds 324.38 # Real time elapsed on the host -sim_insts 71858146 # Number of instructions simulated -sim_ops 71858146 # Number of ops (including micro ops) simulated +host_inst_rate 235004 # Simulator instruction rate (inst/s) +host_op_rate 235004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6029262323 # Simulator tick rate (ticks/s) +host_mem_usage 334496 # Number of bytes of host memory used +host_seconds 305.77 # Real time elapsed on the host +sim_insts 71858166 # Number of instructions simulated +sim_ops 71858166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 498752 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 20812864 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 142016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1542016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1542464 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 270784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2513856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2513408 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 25781248 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 498752 # Number of instructions bytes read from this memory @@ -30,9 +30,9 @@ system.physmem.bytes_written::total 7470272 # Nu system.physmem.num_reads::cpu0.inst 7793 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 325201 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 24094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 24101 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 4231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39279 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 39272 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 402832 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 116723 # Number of write requests responded to by this memory @@ -40,9 +40,9 @@ system.physmem.num_writes::total 116723 # Nu system.physmem.bw_read::cpu0.inst 270533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 11289313 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 77032 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 836420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 836663 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.inst 146879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1363566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1363323 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 13984264 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 270533 # Instruction read bandwidth from this memory (bytes/s) @@ -55,58 +55,58 @@ system.physmem.bw_total::writebacks 4052025 # To system.physmem.bw_total::cpu0.inst 270533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 11289313 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 77032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 836420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 836663 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.inst 146879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1363566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1363323 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18036288 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 69838 # Number of read requests accepted -system.physmem.writeReqs 42816 # Number of write requests accepted +system.physmem.writeReqs 43200 # Number of write requests accepted system.physmem.readBursts 69838 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 42816 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 43200 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 4468672 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 960 # Total number of bytes read from write queue -system.physmem.bytesWritten 2738752 # Total number of bytes written to DRAM +system.physmem.bytesWritten 2763328 # Total number of bytes written to DRAM system.physmem.bytesReadSys 4469632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2740224 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 2764800 # Total written bytes from the system interface side system.physmem.servicedByWrQ 15 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 59609 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 4348 # Per bank write bursts system.physmem.perBankRdBursts::1 4129 # Per bank write bursts system.physmem.perBankRdBursts::2 4337 # Per bank write bursts system.physmem.perBankRdBursts::3 4598 # Per bank write bursts system.physmem.perBankRdBursts::4 3888 # Per bank write bursts system.physmem.perBankRdBursts::5 4661 # Per bank write bursts -system.physmem.perBankRdBursts::6 4236 # Per bank write bursts +system.physmem.perBankRdBursts::6 4235 # Per bank write bursts system.physmem.perBankRdBursts::7 4148 # Per bank write bursts -system.physmem.perBankRdBursts::8 4711 # Per bank write bursts +system.physmem.perBankRdBursts::8 4712 # Per bank write bursts system.physmem.perBankRdBursts::9 4417 # Per bank write bursts system.physmem.perBankRdBursts::10 4595 # Per bank write bursts system.physmem.perBankRdBursts::11 4084 # Per bank write bursts -system.physmem.perBankRdBursts::12 4057 # Per bank write bursts -system.physmem.perBankRdBursts::13 4571 # Per bank write bursts +system.physmem.perBankRdBursts::12 4058 # Per bank write bursts +system.physmem.perBankRdBursts::13 4570 # Per bank write bursts system.physmem.perBankRdBursts::14 4705 # Per bank write bursts system.physmem.perBankRdBursts::15 4338 # Per bank write bursts system.physmem.perBankWrBursts::0 2799 # Per bank write bursts system.physmem.perBankWrBursts::1 2436 # Per bank write bursts -system.physmem.perBankWrBursts::2 2776 # Per bank write bursts -system.physmem.perBankWrBursts::3 2976 # Per bank write bursts -system.physmem.perBankWrBursts::4 2273 # Per bank write bursts -system.physmem.perBankWrBursts::5 2670 # Per bank write bursts +system.physmem.perBankWrBursts::2 2792 # Per bank write bursts +system.physmem.perBankWrBursts::3 3104 # Per bank write bursts +system.physmem.perBankWrBursts::4 2401 # Per bank write bursts +system.physmem.perBankWrBursts::5 2782 # Per bank write bursts system.physmem.perBankWrBursts::6 2480 # Per bank write bursts system.physmem.perBankWrBursts::7 2289 # Per bank write bursts -system.physmem.perBankWrBursts::8 3133 # Per bank write bursts +system.physmem.perBankWrBursts::8 3134 # Per bank write bursts system.physmem.perBankWrBursts::9 2510 # Per bank write bursts system.physmem.perBankWrBursts::10 2861 # Per bank write bursts system.physmem.perBankWrBursts::11 2441 # Per bank write bursts system.physmem.perBankWrBursts::12 2439 # Per bank write bursts -system.physmem.perBankWrBursts::13 2832 # Per bank write bursts +system.physmem.perBankWrBursts::13 2831 # Per bank write bursts system.physmem.perBankWrBursts::14 3033 # Per bank write bursts system.physmem.perBankWrBursts::15 2845 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1842578089000 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 1842577981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -120,11 +120,11 @@ system.physmem.writePktSize::2 0 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 42816 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 5331 # What read queue length does an incoming req see +system.physmem.writePktSize::6 43200 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 49697 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8415 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6353 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 5333 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -155,190 +155,183 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 38 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 748 # What write queue length does an incoming req see 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# What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 44 # What write queue length does an incoming req see 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req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 359.185887 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 202.348650 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 370.654869 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7177 35.77% 35.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4604 22.94% 58.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1640 8.17% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 939 4.68% 71.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 711 3.54% 75.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 484 2.41% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 449 2.24% 79.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 396 1.97% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3666 18.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20066 # Bytes accessed per row activation +system.physmem.wrQLenPdf::15 746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2031 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 20081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 360.141427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 203.044984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 371.054922 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7137 35.54% 35.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4621 23.01% 58.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1666 8.30% 66.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 928 4.62% 71.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 708 3.53% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 489 2.44% 77.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 446 2.22% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 393 1.96% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3693 18.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 20081 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 1852 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 37.694924 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 845.707060 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 845.707136 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 1850 99.89% 99.89% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::34816-36863 1 0.05% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 1852 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 1852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.106371 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.632339 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.643623 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.84% 1.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.38% 2.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.22% 2.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 3 0.16% 2.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1503 81.16% 83.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 52 2.81% 86.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.59% 87.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 74 4.00% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.22% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 8 0.43% 91.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.92% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.43% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 7 0.38% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.05% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.16% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.43% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 8 0.43% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 15 0.81% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.05% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 66 3.56% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.05% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 2 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.11% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.11% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.16% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.313715 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.866365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.527044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 41 2.21% 2.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 7 0.38% 2.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1554 83.91% 86.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 22 1.19% 87.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 8 0.43% 88.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 17 0.92% 89.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 85 4.59% 93.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 1 0.05% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 5 0.27% 93.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 12 0.65% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 79 4.27% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 1 0.05% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 1 0.05% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 2 0.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.11% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 1 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 2 0.11% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 4 0.22% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.11% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-207 1 0.05% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.05% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 1852 # Writes before turning the bus around for reads -system.physmem.totQLat 871326250 # Total ticks spent queuing -system.physmem.totMemAccLat 2180507500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 868841000 # Total ticks spent queuing +system.physmem.totMemAccLat 2178022250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 349115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12479.07 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12443.48 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31229.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31193.48 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.49 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.49 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.08 # Average write queue length when enqueuing -system.physmem.readRowHits 58948 # Number of row buffer hits during reads -system.physmem.writeRowHits 33602 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.48 # Row buffer hit rate for writes -system.physmem.avgGap 16356082.24 # Average gap between requests -system.physmem.pageHitRate 82.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 75161520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 40936500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 267891000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 134129520 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 4.02 # Average write queue length when enqueuing +system.physmem.readRowHits 58950 # Number of row buffer hits during reads +system.physmem.writeRowHits 33969 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.63 # Row buffer hit rate for writes +system.physmem.avgGap 16300518.24 # Average gap between requests +system.physmem.pageHitRate 82.21 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 75327840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 41027250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 267883200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 136617840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 36125026515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 799629184500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 925463073795 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.948938 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1310373436000 # Time in different power states +system.physmem_0.actBackEnergy 36136650240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 799618982250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 925467232860 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.951944 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1310356278000 # Time in different power states system.physmem_0.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9753765000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9770912000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 76537440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 41650125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 276728400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 76484520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 41621250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 276736200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 143169120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 89190744240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35621035650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799049139750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 924399004725 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.002289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1311095993000 # Time in different power states +system.physmem_1.actBackEnergy 35633622105 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 799038075000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 924400452435 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.003354 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1311078051250 # Time in different power states system.physmem_1.memoryStateTime::REF 45598540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9016803000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9034735750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4864865 # DTB read hits +system.cpu0.dtb.read_hits 4864866 # DTB read hits system.cpu0.dtb.read_misses 6190 # DTB read misses system.cpu0.dtb.read_acv 126 # DTB read access violations system.cpu0.dtb.read_accesses 429298 # DTB read accesses -system.cpu0.dtb.write_hits 3435007 # DTB write hits +system.cpu0.dtb.write_hits 3435008 # DTB write hits system.cpu0.dtb.write_misses 688 # DTB write misses system.cpu0.dtb.write_acv 84 # DTB write access violations system.cpu0.dtb.write_accesses 165213 # DTB write accesses -system.cpu0.dtb.data_hits 8299872 # DTB hits +system.cpu0.dtb.data_hits 8299874 # DTB hits system.cpu0.dtb.data_misses 6878 # DTB misses system.cpu0.dtb.data_acv 210 # DTB access violations system.cpu0.dtb.data_accesses 594511 # DTB accesses @@ -374,10 +367,10 @@ system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # nu system.cpu0.kern.ipl_good::22 1880 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73436 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148955 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1820420159000 98.74% 98.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1820420490500 98.74% 98.74% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 39420000 0.00% 98.75% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 369089000 0.02% 98.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22760564000 1.23% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22760232500 1.23% 100.00% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::total 1843589232000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -442,32 +435,32 @@ system.cpu0.kern.mode_switch_good::kernel 0.322243 # f system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29996442500 1.63% 1.63% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2592008500 0.14% 1.77% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1811000779000 98.23% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 29995203000 1.63% 1.63% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2591439000 0.14% 1.77% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1811002588000 98.23% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.cpu0.committedInsts 32582067 # Number of instructions committed system.cpu0.committedOps 32582067 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 30467910 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 163902 # Number of float alu accesses -system.cpu0.num_func_calls 798063 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4326151 # number of instructions that are conditional controls +system.cpu0.num_func_calls 798062 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4326152 # number of instructions that are conditional controls system.cpu0.num_int_insts 30467910 # number of integer instructions system.cpu0.num_fp_insts 163902 # number of float instructions system.cpu0.num_int_register_reads 42599897 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22343202 # number of times the integer registers were written +system.cpu0.num_int_register_writes 22343200 # number of times the integer registers were written system.cpu0.num_fp_register_reads 84869 # number of times the floating registers were read system.cpu0.num_fp_register_writes 86282 # number of times the floating registers were written -system.cpu0.num_mem_refs 8329685 # number of memory refs -system.cpu0.num_load_insts 4886081 # Number of load instructions -system.cpu0.num_store_insts 3443604 # Number of store instructions -system.cpu0.num_idle_cycles 904742998.483282 # Number of idle cycles -system.cpu0.num_busy_cycles 23823652.516718 # Number of busy cycles +system.cpu0.num_mem_refs 8329687 # number of memory refs +system.cpu0.num_load_insts 4886082 # Number of load instructions +system.cpu0.num_store_insts 3443605 # Number of store instructions +system.cpu0.num_idle_cycles 904742998.451047 # Number of idle cycles +system.cpu0.num_busy_cycles 23823652.548953 # Number of busy cycles system.cpu0.not_idle_fraction 0.025656 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.974344 # Percentage of idle cycles system.cpu0.Branches 5381713 # Number of branches fetched system.cpu0.op_class::No_OpClass 1604740 4.92% 4.92% # Class of executed instruction -system.cpu0.op_class::IntAlu 21953707 67.37% 72.29% # Class of executed instruction +system.cpu0.op_class::IntAlu 21953705 67.37% 72.29% # Class of executed instruction system.cpu0.op_class::IntMult 32143 0.10% 72.39% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.39% # Class of executed instruction system.cpu0.op_class::FloatAdd 13006 0.04% 72.43% # Class of executed instruction @@ -496,196 +489,196 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.43% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.43% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.43% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.43% # Class of executed instruction -system.cpu0.op_class::MemRead 5016903 15.39% 87.83% # Class of executed instruction -system.cpu0.op_class::MemWrite 3446713 10.58% 98.40% # Class of executed instruction +system.cpu0.op_class::MemRead 5016904 15.39% 87.83% # Class of executed instruction +system.cpu0.op_class::MemWrite 3446714 10.58% 98.40% # Class of executed instruction system.cpu0.op_class::IprAccess 520313 1.60% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::total 32589155 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1393262 # number of replacements +system.cpu0.dcache.tags.replacements 1393265 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997813 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13241810 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393774 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.500687 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 13241654 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393777 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.500554 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.746834 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216845 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034134 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497552 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236752 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265692 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.747103 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 121.216699 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 136.034010 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497553 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.236751 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.265691 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63387052 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63387052 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4025112 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1019452 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2537983 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7582547 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3145682 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 772489 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5275560 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 63386315 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63386315 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4025113 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1019893 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2537393 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7582399 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3145683 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 772678 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1357185 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275546 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114073 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19050 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51169 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184292 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51175 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184298 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122917 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21014 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55400 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 199331 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7170794 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1791941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3895372 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12858107 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7170794 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1791941 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3895372 # number of overall hits -system.cpu0.dcache.overall_hits::total 12858107 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 7170796 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1792571 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3894578 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12857945 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7170796 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1792571 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3894578 # number of overall hits +system.cpu0.dcache.overall_hits::total 12857945 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 726690 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 86798 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 548610 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1362098 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 86811 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 548555 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1362056 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 165054 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 38388 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 671853 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 875295 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 38389 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 671866 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 875309 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9398 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2090 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7704 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19192 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7703 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19191 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 891744 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 125186 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1220463 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2237393 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 125200 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1220421 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2237365 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 891744 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 125186 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1220463 # number of overall misses -system.cpu0.dcache.overall_misses::total 2237393 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310299500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8894370000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11204669500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2132273000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29520003133 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 31652276133 # number of WriteReq miss cycles +system.cpu0.dcache.overall_misses::cpu1.data 125200 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1220421 # number of overall misses +system.cpu0.dcache.overall_misses::total 2237365 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2310208500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8890735000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11200943500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2130423000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 29514538622 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 31644961622 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27861500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150264500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178126000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 111000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 111000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4442572500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 38414373133 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 42856945633 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4442572500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 38414373133 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 42856945633 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751802 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106250 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3086593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8944645 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310736 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 810877 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029242 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 150253000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 178114500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 108000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 108000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4440631500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 38405273622 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 42845905122 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4440631500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 38405273622 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 42845905122 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4751803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1106704 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3085948 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8944455 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3310737 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 811067 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2029051 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 6150855 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123471 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21140 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58873 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203484 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58878 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203489 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122918 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21014 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55403 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 199335 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8062538 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1917127 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5115835 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15095500 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8062538 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1917127 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5115835 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15095500 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 8062540 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 1917771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5114999 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15095310 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8062540 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 1917771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5114999 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15095310 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.152929 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078461 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177740 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152281 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.078441 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.177759 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152279 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049854 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047341 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331086 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.142305 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.047331 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.331123 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.142307 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.076115 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.098865 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130858 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094317 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130830 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094310 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.110603 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065299 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238566 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.065284 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.238597 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.148216 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.110603 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065299 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238566 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065284 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.238597 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.148216 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26616.966981 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16212.555367 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8226.037701 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55545.300615 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43938.187569 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36161.838161 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 26611.932820 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16207.554393 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 8223.555786 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 55495.662820 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 43929.204070 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 36152.903286 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13330.861244 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19504.737799 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.263026 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 37000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27750 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19154.858191 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35487.774192 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31475.245979 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19154.858191 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1652146 # number of cycles access was blocked +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 19505.776970 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9281.147413 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 36000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19150.163305 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35468.302716 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31468.873136 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19150.163305 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1652562 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 2580 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 59796 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 59814 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.629708 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.628348 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets 215 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835859 # number of writebacks -system.cpu0.dcache.writebacks::total 835859 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 288357 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 288357 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572581 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 572581 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1582 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1582 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 860938 # number of demand (read+write) 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288309 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 288309 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 572598 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 572598 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 860907 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 860907 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 860907 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 860907 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 86811 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 260246 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 347057 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 38389 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 99268 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137657 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2090 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6122 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8212 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 125186 # number of demand (read+write) MSHR misses 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number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 1329 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2652 # number of ReadReq MSHR uncacheable @@ -695,235 +688,235 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3516 system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223501500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676661000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6900162500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2093885000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4616741882 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6710626882 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2223397500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4676165000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6899562500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2092034000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 4615486880 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6707520880 # number of WriteReq MSHR miss cycles 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miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9293402882 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13610789382 # number of overall MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 77436500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103208000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4315431500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9291651880 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13607083380 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4315431500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 9291651880 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13607083380 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 293417500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 298094000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591511500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372514000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 372517000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 424017500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796531500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665931500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 796534500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 665934500 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 722111500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388043000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078461 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084317 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048921 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022381 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1388046000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.078441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084333 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038801 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.047331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.048923 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022380 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.098865 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103987 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103978 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040356 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000015 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.032110 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065299 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070277 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065284 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070286 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.032110 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25616.966981 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17969.671819 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19882.272346 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54545.300615 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46505.982372 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48747.834389 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 25611.932820 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17968.249272 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19880.199794 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 54495.662820 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46495.213765 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48726.333423 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.861244 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.807579 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.888456 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 36000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 36000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34487.774192 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25849.114476 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28080.215597 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12648.889252 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12567.949342 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 34468.302716 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25845.034908 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28072.396052 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 220780.662152 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 225316.704460 # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223043.552036 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230231.149567 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 230233.003708 # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 223402.265543 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226544.795222 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225969.290804 # average overall mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 226545.648464 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 225970.308789 # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 224188.606023 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.396887 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 225039.883268 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 963474 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.175730 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41537475 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 963985 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 43.089337 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 963447 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.175727 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41538422 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 963958 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 43.091527 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 10558559500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250464 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956509 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.968757 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 261.250530 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 81.956033 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 167.969164 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.510255 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160071 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328064 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.160070 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.328065 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998390 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43482483 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43482483 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 32077013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7031290 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2429172 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 41537475 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32077013 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7031290 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2429172 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 41537475 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32077013 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7031290 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2429172 # number of overall hits -system.cpu0.icache.overall_hits::total 41537475 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 512142 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 125208 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 343493 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 980843 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 512142 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 125208 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 343493 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 980843 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 512142 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 125208 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 343493 # number of overall misses -system.cpu0.icache.overall_misses::total 980843 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899043000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5060933969 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6959976969 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1899043000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5060933969 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6959976969 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1899043000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5060933969 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6959976969 # number of overall miss cycles +system.cpu0.icache.tags.tag_accesses 43483376 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43483376 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 32077016 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7032806 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2428600 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41538422 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32077016 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7032806 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2428600 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41538422 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32077016 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7032806 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2428600 # number of overall hits +system.cpu0.icache.overall_hits::total 41538422 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 512139 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 125213 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 343464 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 980816 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 512139 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 125213 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 343464 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 980816 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 512139 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 125213 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 343464 # number of overall misses +system.cpu0.icache.overall_misses::total 980816 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1899535500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5061406468 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6960941968 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1899535500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 5061406468 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6960941968 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1899535500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 5061406468 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6960941968 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 32589155 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7156498 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2772665 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 42518318 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7158019 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2772064 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42519238 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 32589155 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7156498 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2772665 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 42518318 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7158019 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2772064 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42519238 # number of demand (read+write) accesses system.cpu0.icache.overall_accesses::cpu0.inst 32589155 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7156498 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2772665 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 42518318 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7158019 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2772064 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42519238 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015715 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017496 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123886 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023069 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.017493 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.123902 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023068 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015715 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017496 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123886 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023069 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.017493 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.123902 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023068 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015715 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017496 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123886 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023069 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15167.105936 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14733.732475 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7095.913382 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7095.913382 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15167.105936 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14733.732475 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7095.913382 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8552 # number of cycles access was blocked +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.017493 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.123902 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023068 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 15170.433581 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14736.352188 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7097.092592 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7097.092592 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 15170.433581 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14736.352188 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7097.092592 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8655 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 357 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 361 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.955182 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.975069 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 963474 # number of writebacks -system.cpu0.icache.writebacks::total 963474 # number of writebacks +system.cpu0.icache.writebacks::writebacks 963447 # number of writebacks +system.cpu0.icache.writebacks::total 963447 # number of writebacks system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16678 # number of ReadReq MSHR hits system.cpu0.icache.ReadReq_mshr_hits::total 16678 # number of ReadReq MSHR hits system.cpu0.icache.demand_mshr_hits::cpu2.inst 16678 # number of demand (read+write) MSHR hits system.cpu0.icache.demand_mshr_hits::total 16678 # number of demand (read+write) MSHR hits system.cpu0.icache.overall_mshr_hits::cpu2.inst 16678 # number of overall MSHR hits system.cpu0.icache.overall_mshr_hits::total 16678 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125208 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326815 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 452023 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 125208 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326815 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 452023 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 125208 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326815 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 452023 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1773835000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4488659473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6262494473 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1773835000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4488659473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6262494473 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1773835000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4488659473 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6262494473 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010631 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010631 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017496 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117870 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.010631 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13854.371289 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14167.105936 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13734.557695 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13854.371289 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 125213 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326786 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 451999 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 125213 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 326786 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 451999 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 125213 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 326786 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 451999 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1774322500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4489110472 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6263432972 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1774322500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4489110472 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6263432972 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1774322500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4489110472 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6263432972 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010630 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010630 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.017493 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.117885 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010630 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13857.183250 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 14170.433581 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13737.156647 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13857.183250 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1125427 # DTB read hits +system.cpu1.dtb.read_hits 1125881 # DTB read hits system.cpu1.dtb.read_misses 1262 # DTB read misses system.cpu1.dtb.read_acv 31 # DTB read access violations -system.cpu1.dtb.read_accesses 117717 # DTB read accesses -system.cpu1.dtb.write_hits 832316 # DTB write hits +system.cpu1.dtb.read_accesses 118172 # DTB read accesses +system.cpu1.dtb.write_hits 832506 # DTB write hits system.cpu1.dtb.write_misses 154 # DTB write misses system.cpu1.dtb.write_acv 18 # DTB write access violations -system.cpu1.dtb.write_accesses 48434 # DTB write accesses -system.cpu1.dtb.data_hits 1957743 # DTB hits +system.cpu1.dtb.write_accesses 48626 # DTB write accesses +system.cpu1.dtb.data_hits 1958387 # DTB hits system.cpu1.dtb.data_misses 1416 # DTB misses system.cpu1.dtb.data_acv 49 # DTB access violations -system.cpu1.dtb.data_accesses 166151 # DTB accesses -system.cpu1.itb.fetch_hits 753702 # ITB hits +system.cpu1.dtb.data_accesses 166798 # DTB accesses +system.cpu1.itb.fetch_hits 755228 # ITB hits system.cpu1.itb.fetch_misses 636 # ITB misses system.cpu1.itb.fetch_acv 28 # ITB acv -system.cpu1.itb.fetch_accesses 754338 # ITB accesses +system.cpu1.itb.fetch_accesses 755864 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -936,7 +929,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953452897 # number of cpu cycles simulated +system.cpu1.numCycles 953452805 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -956,35 +949,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu1.committedInsts 7155032 # Number of instructions committed -system.cpu1.committedOps 7155032 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6639972 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 39507 # Number of float alu accesses -system.cpu1.num_func_calls 205327 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 849342 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6639972 # number of integer instructions -system.cpu1.num_fp_insts 39507 # number of float instructions -system.cpu1.num_int_register_reads 9236476 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4860513 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 20546 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 21005 # number of times the floating registers were written -system.cpu1.num_mem_refs 1964570 # number of memory refs -system.cpu1.num_load_insts 1130012 # Number of load instructions -system.cpu1.num_store_insts 834558 # Number of store instructions -system.cpu1.num_idle_cycles 924897585.359422 # Number of idle cycles -system.cpu1.num_busy_cycles 28555311.640577 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029949 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970051 # Percentage of idle cycles -system.cpu1.Branches 1119214 # Number of branches fetched -system.cpu1.op_class::No_OpClass 390317 5.45% 5.45% # Class of executed instruction -system.cpu1.op_class::IntAlu 4631234 64.71% 70.17% # Class of executed instruction -system.cpu1.op_class::IntMult 7711 0.11% 70.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu1.op_class::FloatAdd 3307 0.05% 70.32% # Class of executed instruction +system.cpu1.committedInsts 7156553 # Number of instructions committed +system.cpu1.committedOps 7156553 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6641394 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 39637 # Number of float alu accesses +system.cpu1.num_func_calls 205363 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 849545 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6641394 # number of integer instructions +system.cpu1.num_fp_insts 39637 # number of float instructions +system.cpu1.num_int_register_reads 9238548 # number of times the integer registers were read +system.cpu1.num_int_register_writes 4861490 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 20633 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 21093 # number of times the floating registers were written +system.cpu1.num_mem_refs 1965214 # number of memory refs +system.cpu1.num_load_insts 1130466 # Number of load instructions +system.cpu1.num_store_insts 834748 # Number of store instructions +system.cpu1.num_idle_cycles 924897133.577308 # Number of idle cycles +system.cpu1.num_busy_cycles 28555671.422692 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029950 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970050 # Percentage of idle cycles +system.cpu1.Branches 1119461 # Number of branches fetched +system.cpu1.op_class::No_OpClass 390354 5.45% 5.45% # Class of executed instruction +system.cpu1.op_class::IntAlu 4632011 64.71% 70.16% # Class of executed instruction +system.cpu1.op_class::IntMult 7720 0.11% 70.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 3352 0.05% 70.32% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 70.32% # Class of executed instruction system.cpu1.op_class::FloatCvt 0 0.00% 70.32% # Class of executed instruction system.cpu1.op_class::FloatMult 0 0.00% 70.32% # Class of executed instruction -system.cpu1.op_class::FloatDiv 440 0.01% 70.33% # Class of executed instruction +system.cpu1.op_class::FloatDiv 449 0.01% 70.33% # Class of executed instruction system.cpu1.op_class::FloatSqrt 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdAdd 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdAddAcc 0 0.00% 70.33% # Class of executed instruction @@ -1006,40 +999,40 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.33% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.33% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.33% # Class of executed instruction -system.cpu1.op_class::MemRead 1158585 16.19% 86.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 835763 11.68% 98.20% # Class of executed instruction +system.cpu1.op_class::MemRead 1159039 16.19% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 835953 11.68% 98.20% # Class of executed instruction system.cpu1.op_class::IprAccess 129140 1.80% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7156497 # Class of executed instruction -system.cpu2.branchPred.lookups 10791906 # Number of BP lookups -system.cpu2.branchPred.condPredicted 10058996 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 121698 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 8434906 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 6656118 # Number of BTB hits +system.cpu1.op_class::total 7158018 # Class of executed instruction +system.cpu2.branchPred.lookups 10791255 # Number of BP lookups +system.cpu2.branchPred.condPredicted 10058403 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 121654 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8435844 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6655738 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 78.911585 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 298697 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7721 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.898306 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 298678 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7720 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3520448 # DTB read hits -system.cpu2.dtb.read_misses 12146 # DTB read misses +system.cpu2.dtb.read_hits 3519605 # DTB read hits +system.cpu2.dtb.read_misses 12192 # DTB read misses system.cpu2.dtb.read_acv 125 # DTB read access violations -system.cpu2.dtb.read_accesses 256305 # DTB read accesses -system.cpu2.dtb.write_hits 2173477 # DTB write hits -system.cpu2.dtb.write_misses 2690 # DTB write misses +system.cpu2.dtb.read_accesses 255658 # DTB read accesses +system.cpu2.dtb.write_hits 2173211 # DTB write hits +system.cpu2.dtb.write_misses 2700 # DTB write misses system.cpu2.dtb.write_acv 124 # DTB write access violations -system.cpu2.dtb.write_accesses 93625 # DTB write accesses -system.cpu2.dtb.data_hits 5693925 # DTB hits -system.cpu2.dtb.data_misses 14836 # DTB misses +system.cpu2.dtb.write_accesses 93379 # DTB write accesses +system.cpu2.dtb.data_hits 5692816 # DTB hits +system.cpu2.dtb.data_misses 14892 # DTB misses system.cpu2.dtb.data_acv 249 # DTB access violations -system.cpu2.dtb.data_accesses 349930 # DTB accesses -system.cpu2.itb.fetch_hits 553155 # ITB hits -system.cpu2.itb.fetch_misses 5226 # ITB misses -system.cpu2.itb.fetch_acv 187 # ITB acv -system.cpu2.itb.fetch_accesses 558381 # ITB accesses +system.cpu2.dtb.data_accesses 349037 # DTB accesses +system.cpu2.itb.fetch_hits 552522 # ITB hits +system.cpu2.itb.fetch_misses 5239 # ITB misses +system.cpu2.itb.fetch_acv 186 # ITB acv +system.cpu2.itb.fetch_accesses 557761 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1052,143 +1045,143 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 32236279 # number of cpu cycles simulated +system.cpu2.numCycles 32231216 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9243840 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 40617547 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 10791906 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 6954815 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 20753592 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 401538 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 9243140 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 40614337 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10791255 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6954416 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 20748537 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 401448 # Number of cycles fetch has spent squashing system.cpu2.fetch.TlbCycles 916 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10212 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 2008 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 193151 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 89388 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1068 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2772679 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 90084 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.MiscStallCycles 10245 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 2007 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 193088 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 89379 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1066 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2772079 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 89992 # Number of outstanding Icache misses that were squashed system.cpu2.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 30494706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.331954 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.325119 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 30488864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.332104 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.325204 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 21037778 68.99% 68.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 294298 0.97% 69.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 469114 1.54% 71.49% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 5033169 16.51% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 879924 2.89% 90.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194801 0.64% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 230028 0.75% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 433107 1.42% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1922487 6.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 21032791 68.99% 68.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 294156 0.96% 69.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 468874 1.54% 71.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 5033027 16.51% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 879823 2.89% 90.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194768 0.64% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 230051 0.75% 92.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433078 1.42% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1922296 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 30494706 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.334775 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.259995 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7573321 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 14126025 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 7836977 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 524605 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 187915 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 174630 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13216 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 37265458 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 41467 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 187915 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7850244 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4676437 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6613578 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 8057400 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2863279 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 36458401 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 57802 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 368784 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 93789 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1799072 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 24336413 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 45554095 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 45489801 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 60051 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 22465786 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1870627 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 531021 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 62908 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3828322 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3503706 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2266582 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 453499 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 325031 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 33954893 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 679527 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 33661057 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 16143 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2513373 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1127788 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 486024 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 30494706 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.103833 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.612725 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 30488864 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.334808 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.260093 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7572995 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 14121086 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7836457 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 524591 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 187872 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 174587 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13215 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37262943 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 41463 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 187872 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7849913 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4677015 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6609993 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 8056869 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2861349 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 36455800 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 58084 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 369048 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 93720 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1797134 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 24334504 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 45550794 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 45486602 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 59958 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 22464723 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1869781 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 530990 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 62923 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3828293 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3503034 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2266301 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 453472 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 325651 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 33952570 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 679538 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 33658910 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16165 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2512562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1127430 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 486035 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 30488864 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.103974 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612784 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 18452821 60.51% 60.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2702851 8.86% 69.37% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1349809 4.43% 73.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 5753089 18.87% 92.67% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1041578 3.42% 96.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 588420 1.93% 98.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 396893 1.30% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 164409 0.54% 99.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 44836 0.15% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 18447860 60.51% 60.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2702530 8.86% 69.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1349610 4.43% 73.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5752968 18.87% 92.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1041424 3.42% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 588365 1.93% 98.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 396836 1.30% 99.31% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 164449 0.54% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44822 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 30494706 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 30488864 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 81527 21.02% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 179819 46.37% 67.39% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 126481 32.61% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 81533 21.03% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.03% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179737 46.36% 67.39% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 126415 32.61% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 3131 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 27465013 81.59% 81.60% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21327 0.06% 81.67% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 3114 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 27463980 81.59% 81.60% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21318 0.06% 81.67% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.67% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 22209 0.07% 81.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 22163 0.07% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.73% # Type of FU issued system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1566 0.00% 81.74% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1557 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.74% # Type of FU issued @@ -1210,101 +1203,101 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.74% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.74% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3648084 10.84% 92.57% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2197360 6.53% 99.10% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3647310 10.84% 92.57% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2197101 6.53% 99.10% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 302367 0.90% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 33661057 # Type of FU issued -system.cpu2.iq.rate 1.044198 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 387827 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.011522 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 97956454 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 37027606 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 33043548 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 264336 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 125822 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 122705 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 33904668 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 141085 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 200240 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 33658910 # Type of FU issued +system.cpu2.iq.rate 1.044295 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387685 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011518 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 97946508 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 37024649 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 33041720 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 264026 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 125654 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 122549 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 33902559 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 140922 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 200179 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 431120 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1112 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5749 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 178621 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 430903 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1110 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5745 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178531 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 4239 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 217381 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.cacheBlocked 217245 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 187915 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4008679 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 205535 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 35998675 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 51747 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3503706 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2266582 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 605109 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 12931 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 157162 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5749 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 59808 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134012 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193820 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33465262 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3541255 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 195795 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 187872 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4009534 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 206574 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35996335 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51785 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3503034 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2266301 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 605122 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12947 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 158194 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5745 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 59769 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 133968 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193737 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33463084 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3540458 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 195826 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1364255 # number of nop insts executed -system.cpu2.iew.exec_refs 5722116 # number of memory reference insts executed -system.cpu2.iew.exec_branches 7732316 # Number of branches executed -system.cpu2.iew.exec_stores 2180861 # Number of stores executed -system.cpu2.iew.exec_rate 1.038124 # Inst execution rate -system.cpu2.iew.wb_sent 33208664 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 33166253 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 19395256 # num instructions producing a value -system.cpu2.iew.wb_consumers 23138933 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.028849 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.838209 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 2630446 # The number of squashed insts skipped by commit +system.cpu2.iew.exec_nop 1364227 # number of nop insts executed +system.cpu2.iew.exec_refs 5721059 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7732015 # Number of branches executed +system.cpu2.iew.exec_stores 2180601 # Number of stores executed +system.cpu2.iew.exec_rate 1.038220 # Inst execution rate +system.cpu2.iew.wb_sent 33206737 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 33164269 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 19394211 # num instructions producing a value +system.cpu2.iew.wb_consumers 23137569 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.028949 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.838213 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 2629534 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 193503 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 177071 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 30033551 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.109504 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.847540 # Number of insts commited each cycle +system.cpu2.commit.branchMispredicts 177029 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 30027785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.109667 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.847605 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 19200071 63.93% 63.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2226295 7.41% 71.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1158853 3.86% 75.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5473619 18.23% 93.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 589521 1.96% 95.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 197097 0.66% 96.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 164200 0.55% 96.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 162437 0.54% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 861458 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 19194769 63.92% 63.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2226064 7.41% 71.34% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1158797 3.86% 75.20% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5473612 18.23% 93.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 589514 1.96% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 197059 0.66% 96.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164152 0.55% 96.59% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 162472 0.54% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 861346 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 30033551 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 33322350 # Number of instructions committed -system.cpu2.commit.committedOps 33322350 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 30027785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 33320829 # Number of instructions committed +system.cpu2.commit.committedOps 33320829 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5160547 # Number of memory references committed -system.cpu2.commit.loads 3072586 # Number of loads committed +system.cpu2.commit.refs 5159901 # Number of memory references committed +system.cpu2.commit.loads 3072131 # Number of loads committed system.cpu2.commit.membars 67946 # Number of memory barriers committed -system.cpu2.commit.branches 7560075 # Number of branches committed -system.cpu2.commit.fp_insts 120848 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 31822701 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240099 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1204434 3.61% 3.61% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 26541208 79.65% 83.26% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20874 0.06% 83.33% # Class of committed instruction +system.cpu2.commit.branches 7559828 # Number of branches committed +system.cpu2.commit.fp_insts 120718 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 31821279 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240082 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1204397 3.61% 3.61% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 26540433 79.65% 83.27% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20865 0.06% 83.33% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 83.33% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 21768 0.07% 83.39% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 21723 0.07% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 83.39% # Class of committed instruction system.cpu2.commit.op_class_0::FloatMult 0 0.00% 83.39% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1566 0.00% 83.40% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1557 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 83.40% # Class of committed instruction @@ -1326,29 +1319,29 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 83.40% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 83.40% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 83.40% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3140532 9.42% 92.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2089601 6.27% 99.09% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3140077 9.42% 92.82% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2089410 6.27% 99.09% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 302367 0.91% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 33322350 # Class of committed instruction -system.cpu2.commit.bw_lim_events 861458 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 65049813 # The number of ROB reads -system.cpu2.rob.rob_writes 72365341 # The number of ROB writes -system.cpu2.timesIdled 178213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1741573 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747477665 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 32121047 # Number of Instructions Simulated -system.cpu2.committedOps 32121047 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.003587 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.003587 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.996425 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.996425 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 43934131 # number of integer regfile reads -system.cpu2.int_regfile_writes 23251716 # number of integer regfile writes -system.cpu2.fp_regfile_reads 74710 # number of floating regfile reads -system.cpu2.fp_regfile_writes 74652 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5374912 # number of misc regfile reads -system.cpu2.misc_regfile_writes 272966 # number of misc regfile writes +system.cpu2.commit.op_class_0::total 33320829 # Class of committed instruction +system.cpu2.commit.bw_lim_events 861346 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 65041726 # The number of ROB reads +system.cpu2.rob.rob_writes 72360391 # The number of ROB writes +system.cpu2.timesIdled 178229 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1742352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1747482810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 32119546 # Number of Instructions Simulated +system.cpu2.committedOps 32119546 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.003477 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.003477 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.996535 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.996535 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 43931463 # number of integer regfile reads +system.cpu2.int_regfile_writes 23250358 # number of integer regfile writes +system.cpu2.fp_regfile_reads 74602 # number of floating regfile reads +system.cpu2.fp_regfile_writes 74558 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5374687 # number of misc regfile reads +system.cpu2.misc_regfile_writes 272957 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1391,7 +1384,7 @@ system.iobus.pkt_size_system.bridge.master::total 45584 system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707192 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2564500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 2566000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 118500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1399,20 +1392,20 @@ system.iobus.reqLayer22.occupancy 55500 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2121000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 2120500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 84230549 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 86466426 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 8820000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16458000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16844000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements system.iocache.tags.tagsinuse 1.261273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1694926918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1694926915000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.261273 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078830 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078830 # Average percentage of cache occupancy @@ -1429,14 +1422,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9458962 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9458962 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 2126843587 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2126843587 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9458962 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9458962 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9458962 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9458962 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9575962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9575962 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 2102569464 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 2102569464 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9575962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9575962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9575962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9575962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) @@ -1453,77 +1446,77 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54676.080925 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54676.080925 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 51185.107504 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 51185.107504 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54676.080925 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54676.080925 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54676.080925 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 55352.381503 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 55352.381503 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 50600.920870 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 50600.920870 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 55352.381503 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 55352.381503 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.166667 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41512 # number of writebacks system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 69 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16272 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 16272 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 69 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 69 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 69 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 69 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6008962 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 6008962 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1313243587 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1313243587 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 6008962 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 6008962 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 6008962 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 6008962 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.391606 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.391606 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.398844 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.398844 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 87086.405797 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80705.726831 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80705.726831 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 87086.405797 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 87086.405797 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::tsunami.ide 16656 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 16656 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 6075962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 6075962 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 1269053528 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1269053528 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 6075962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 6075962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 6075962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 6075962 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 0.400847 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.400847 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86799.457143 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76191.974544 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76191.974544 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 86799.457143 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 86799.457143 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 337614 # number of replacements -system.l2c.tags.tagsinuse 65425.004009 # Cycle average of tags in use -system.l2c.tags.total_refs 4005267 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65425.009940 # Cycle average of tags in use +system.l2c.tags.total_refs 4005222 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 402776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.944155 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 9.944043 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54894.973613 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2664.591905 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2878.625445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 441.912379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 553.808439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2003.360689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1987.731539 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 54894.998559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2664.593878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2878.621970 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 441.912362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 553.890082 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2003.349443 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1987.643647 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.837631 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.040658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.043924 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.006743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008452 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.030569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.030330 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.030329 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.998306 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id @@ -1532,12 +1525,12 @@ system.l2c.tags.age_task_id_blocks_1024::2 6136 # system.l2c.tags.age_task_id_blocks_1024::3 2779 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::4 55356 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38412750 # Number of tag accesses -system.l2c.tags.data_accesses 38412750 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 835859 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 835859 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 963177 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 963177 # number of WritebackClean hits +system.l2c.tags.tag_accesses 38412363 # Number of tag accesses +system.l2c.tags.data_accesses 38412363 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 835864 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 835864 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 963150 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 963150 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits @@ -1545,31 +1538,31 @@ system.l2c.UpgradeReq_hits::total 13 # nu system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 90398 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 24435 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 72282 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187115 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 504328 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 122989 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 322557 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 949874 # number of ReadCleanReq hits +system.l2c.ReadExReq_hits::cpu1.data 24436 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 72279 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187113 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 504325 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 122994 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 322528 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 949847 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 485259 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 78702 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 253717 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 817678 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 504328 # number of demand (read+write) hits +system.l2c.ReadSharedReq_hits::cpu1.data 78708 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2.data 253716 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 817683 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 504325 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 575657 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 122989 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 103137 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 322557 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 325999 # number of demand (read+write) hits -system.l2c.demand_hits::total 1954667 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 504328 # number of overall hits +system.l2c.demand_hits::cpu1.inst 122994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 103144 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 322528 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 325995 # number of demand (read+write) hits +system.l2c.demand_hits::total 1954643 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 504325 # number of overall hits system.l2c.overall_hits::cpu0.data 575657 # number of overall hits -system.l2c.overall_hits::cpu1.inst 122989 # number of overall hits -system.l2c.overall_hits::cpu1.data 103137 # number of overall hits -system.l2c.overall_hits::cpu2.inst 322557 # number of overall hits -system.l2c.overall_hits::cpu2.data 325999 # number of overall hits -system.l2c.overall_hits::total 1954667 # number of overall hits +system.l2c.overall_hits::cpu1.inst 122994 # number of overall hits +system.l2c.overall_hits::cpu1.data 103144 # number of overall hits +system.l2c.overall_hits::cpu2.inst 322528 # number of overall hits +system.l2c.overall_hits::cpu2.data 325995 # number of overall hits +system.l2c.overall_hits::total 1954643 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 22 # number of UpgradeReq misses @@ -1578,57 +1571,57 @@ system.l2c.SCUpgradeReq_misses::cpu2.data 1 # n system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 74645 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13952 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 27192 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115789 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 27191 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115788 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 7793 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 2219 # number 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uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1323 # number of ReadReq MSHR uncacheable @@ -1759,191 +1752,191 @@ system.l2c.WriteReq_mshr_uncacheable::total 3516 # system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2947 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3221 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 6168 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 1004500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 1004500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 70500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 70500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1639811000 # number of ReadExReq MSHR miss cycles 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# number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 4878050500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8497831504 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 276798000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 281540000 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 558338000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 353898000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 353901000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 402187000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 756085000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 630696000 # number of overall MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 756088000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 630699000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu2.data 683727000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1314423000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1314426000 # number of overall MSHR uncacheable cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.608696 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.333333 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363456 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273358 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.135832 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.363447 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.273359 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.135830 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006690 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114594 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046721 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.029775 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017723 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.189652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012947 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.108381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.029775 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 71750 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71750 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117532.325115 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125700.959841 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 122930.961987 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123226.356589 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116441.046534 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117536.509851 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117043.234163 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122011.266336 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117071.816223 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123863.625620 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123138.945668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121061.261839 # average overall mshr miss latency +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.114656 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.046700 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.020733 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.029776 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017722 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.189686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012948 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.108365 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.029776 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68607.142857 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68607.142857 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117398.795872 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 125662.406679 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 122860.134166 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123414.186667 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 116335.867752 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 117560.865717 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 117008.907258 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.920685 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 116950.072479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 124048.925550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 123120.911156 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121025.870597 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 208275.395034 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 212804.232804 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 210534.690799 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218725.587145 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218727.441286 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 211900.421496 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215041.240046 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214012.894469 # average overall mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 215042.093288 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 214013.912453 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 212271.654766 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 213103.599222 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 213104.085603 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7144 # Transaction distribution -system.membus.trans_dist::ReadResp 294754 # Transaction distribution +system.membus.trans_dist::ReadResp 294755 # Transaction distribution system.membus.trans_dist::WriteReq 9812 # Transaction distribution system.membus.trans_dist::WriteResp 9812 # Transaction distribution system.membus.trans_dist::WritebackDirty 116723 # Transaction distribution -system.membus.trans_dist::CleanEvict 261691 # Transaction distribution +system.membus.trans_dist::CleanEvict 261851 # Transaction distribution system.membus.trans_dist::UpgradeReq 160 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 162 # Transaction distribution -system.membus.trans_dist::ReadExReq 115651 # Transaction distribution -system.membus.trans_dist::ReadExResp 115651 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 287866 # Transaction distribution +system.membus.trans_dist::UpgradeResp 116 # Transaction distribution +system.membus.trans_dist::ReadExReq 115650 # Transaction distribution +system.membus.trans_dist::ReadExResp 115650 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 287867 # Transaction distribution system.membus.trans_dist::BadAddressError 256 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::InvalidateResp 24896 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143284 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1143238 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 512 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1177708 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1302629 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1177662 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1286086 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45584 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30604608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::total 30650192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2664384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33314576 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 159 # Total snoops (count) -system.membus.snoop_fanout::samples 840768 # Request fanout histogram +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2664320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33314512 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 160 # Total snoops (count) +system.membus.snoop_fanout::samples 840765 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 840768 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 840765 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 840768 # Request fanout histogram -system.membus.reqLayer0.occupancy 11147000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 840765 # Request fanout histogram +system.membus.reqLayer0.occupancy 11148000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 348692458 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 350987320 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 375048955 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 374958750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 27286702 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 368038 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4714972 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2357166 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4714924 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2357142 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1609 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1129 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1129 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7144 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062235 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062215 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 9812 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 9812 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 878682 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 963177 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 599628 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 879068 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 963447 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 600902 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 35 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 39 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302904 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302904 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 964165 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1091197 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302901 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302901 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 964138 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1091204 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 256 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 16272 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891480 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4214095 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7105575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123348160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142745680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266093840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 421214 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4208473 # Request fanout histogram +system.toL2Bus.trans_dist::InvalidateReq 16656 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2891696 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4215380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7107076 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 123363712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142746256 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 266109968 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 421211 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4208443 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 0.000983 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.031334 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4204337 99.90% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4204307 99.90% 99.90% # Request fanout histogram system.toL2Bus.snoop_fanout::1 4136 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4208473 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1783329500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4208443 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1783289500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 99462 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 100962 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 678448171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 678414167 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 743541954 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 743545456 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index a63afd969..e7604208d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848979 # Number of seconds simulated -sim_ticks 2848979128500 # Number of ticks simulated -final_tick 2848979128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848869 # Number of seconds simulated +sim_ticks 2848869082500 # Number of ticks simulated +final_tick 2848869082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154282 # Simulator instruction rate (inst/s) -host_op_rate 186830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3456392917 # Simulator tick rate (ticks/s) -host_mem_usage 618280 # Number of bytes of host memory used -host_seconds 824.26 # Real time elapsed on the host -sim_insts 127169330 # Number of instructions simulated -sim_ops 153997543 # Number of ops (including micro ops) simulated +host_inst_rate 198569 # Simulator instruction rate (inst/s) +host_op_rate 240456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4442491449 # Simulator tick rate (ticks/s) +host_mem_usage 621364 # Number of bytes of host memory used +host_seconds 641.28 # Real time elapsed on the host +sim_insts 127338052 # Number of instructions simulated +sim_ops 154199103 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8704 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1698560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1348800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8516160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 208256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 632788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 357568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1697856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1350060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8564736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 206784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 630484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 333888 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12772244 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1698560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 208256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1906816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8849024 # Number of bytes written to this memory +system.physmem.bytes_read::total 12794304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1697856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 206784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1904640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8859904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8866588 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 132 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8877468 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 136 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3254 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5587 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133824 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5217 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200113 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138266 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200453 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138436 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142657 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2965 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142827 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3055 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 596200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 473433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2989197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 125507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 595975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 473893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3006363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 221310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 117200 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4483095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 596200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 669298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3106033 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4491012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 595975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 668560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3109972 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3112198 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3106033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3116138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3109972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3055 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 596200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 479584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2989197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 125507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 595975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 480045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3006363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 221324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 117200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7595293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200113 # Number of read requests accepted -system.physmem.writeReqs 142657 # Number of write requests accepted -system.physmem.readBursts 200113 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 142657 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12798592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 8879168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12772244 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8866588 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7607149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200453 # Number of read requests accepted +system.physmem.writeReqs 142827 # Number of write requests accepted +system.physmem.readBursts 200453 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 142827 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12818368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue +system.physmem.bytesWritten 8890624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12794304 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8877468 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 69084 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12287 # Per bank write bursts -system.physmem.perBankRdBursts::1 12592 # Per bank write bursts -system.physmem.perBankRdBursts::2 13485 # Per bank write bursts -system.physmem.perBankRdBursts::3 12796 # Per bank write bursts -system.physmem.perBankRdBursts::4 15663 # Per bank write bursts -system.physmem.perBankRdBursts::5 12764 # Per bank write bursts -system.physmem.perBankRdBursts::6 12615 # Per bank write bursts -system.physmem.perBankRdBursts::7 12815 # Per bank write bursts -system.physmem.perBankRdBursts::8 11998 # Per bank write bursts -system.physmem.perBankRdBursts::9 12140 # Per bank write bursts -system.physmem.perBankRdBursts::10 11596 # Per bank write bursts -system.physmem.perBankRdBursts::11 10685 # Per bank write bursts -system.physmem.perBankRdBursts::12 11914 # Per bank write bursts -system.physmem.perBankRdBursts::13 12844 # Per bank write bursts -system.physmem.perBankRdBursts::14 12075 # Per bank write bursts -system.physmem.perBankRdBursts::15 11709 # Per bank write bursts -system.physmem.perBankWrBursts::0 8805 # Per bank write bursts -system.physmem.perBankWrBursts::1 9189 # Per bank write bursts -system.physmem.perBankWrBursts::2 9797 # Per bank write bursts -system.physmem.perBankWrBursts::3 9112 # Per bank write bursts -system.physmem.perBankWrBursts::4 8303 # Per bank write bursts -system.physmem.perBankWrBursts::5 8892 # Per bank write bursts -system.physmem.perBankWrBursts::6 8866 # Per bank write bursts -system.physmem.perBankWrBursts::7 8915 # Per bank write bursts -system.physmem.perBankWrBursts::8 8401 # Per bank write bursts -system.physmem.perBankWrBursts::9 8590 # Per bank write bursts -system.physmem.perBankWrBursts::10 8283 # Per bank write bursts -system.physmem.perBankWrBursts::11 7752 # Per bank write bursts -system.physmem.perBankWrBursts::12 8566 # Per bank write bursts -system.physmem.perBankWrBursts::13 8822 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12269 # Per bank write bursts +system.physmem.perBankRdBursts::1 12614 # Per bank write bursts +system.physmem.perBankRdBursts::2 13475 # Per bank write bursts +system.physmem.perBankRdBursts::3 12831 # Per bank write bursts +system.physmem.perBankRdBursts::4 15664 # Per bank write bursts +system.physmem.perBankRdBursts::5 12720 # Per bank write bursts +system.physmem.perBankRdBursts::6 12662 # Per bank write bursts +system.physmem.perBankRdBursts::7 12956 # Per bank write bursts +system.physmem.perBankRdBursts::8 12071 # Per bank write bursts +system.physmem.perBankRdBursts::9 12246 # Per bank write bursts +system.physmem.perBankRdBursts::10 11615 # Per bank write bursts +system.physmem.perBankRdBursts::11 10653 # Per bank write bursts +system.physmem.perBankRdBursts::12 11883 # Per bank write bursts +system.physmem.perBankRdBursts::13 12836 # Per bank write bursts +system.physmem.perBankRdBursts::14 12055 # Per bank write bursts +system.physmem.perBankRdBursts::15 11737 # Per bank write bursts +system.physmem.perBankWrBursts::0 8758 # Per bank write bursts +system.physmem.perBankWrBursts::1 9183 # Per bank write bursts +system.physmem.perBankWrBursts::2 9791 # Per bank write bursts +system.physmem.perBankWrBursts::3 9102 # Per bank write bursts +system.physmem.perBankWrBursts::4 8279 # Per bank write bursts +system.physmem.perBankWrBursts::5 8882 # Per bank write bursts +system.physmem.perBankWrBursts::6 8907 # Per bank write bursts +system.physmem.perBankWrBursts::7 8993 # Per bank write bursts +system.physmem.perBankWrBursts::8 8509 # Per bank write bursts +system.physmem.perBankWrBursts::9 8693 # Per bank write bursts +system.physmem.perBankWrBursts::10 8248 # Per bank write bursts +system.physmem.perBankWrBursts::11 7749 # Per bank write bursts +system.physmem.perBankWrBursts::12 8519 # Per bank write bursts +system.physmem.perBankWrBursts::13 8825 # Per bank write bursts system.physmem.perBankWrBursts::14 8545 # Per bank write bursts -system.physmem.perBankWrBursts::15 7899 # Per bank write bursts +system.physmem.perBankWrBursts::15 7933 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 2848978583000 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 2848868537000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 557 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199528 # Read request sizes (log2) +system.physmem.readPktSize::6 199873 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138266 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 88817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138436 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 88840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -184,161 +184,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92122 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.314387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.718922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.822907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 49981 54.26% 54.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17852 19.38% 73.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6274 6.81% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3559 3.86% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2993 3.25% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1358 1.47% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 900 0.98% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 994 1.08% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8211 8.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92122 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6829 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.283204 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.566486 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6828 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8081 # What write queue length does an incoming req see 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length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 234.543816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.254652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.662523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50344 54.39% 54.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17979 19.42% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6295 6.80% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3544 3.83% 84.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2825 3.05% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1428 1.54% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 907 0.98% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1020 1.10% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8215 8.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92557 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6759 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.632490 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 567.452985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6758 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6829 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.315859 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.777431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.379766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5626 82.38% 82.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 466 6.82% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 97 1.42% 90.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 149 2.18% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 29 0.42% 93.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 128 1.87% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 35 0.51% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.25% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.37% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.34% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.10% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 138 2.02% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.12% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.38% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.06% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.21% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6829 # Writes before turning the bus around for reads -system.physmem.totQLat 5270639949 # Total ticks spent queuing -system.physmem.totMemAccLat 9020227449 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 999890000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26356.10 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6759 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.552744 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.790179 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.439026 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5671 83.90% 83.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 455 6.73% 90.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 79 1.17% 91.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 48 0.71% 92.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.47% 92.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.31% 93.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 53 0.78% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.21% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 132 1.95% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.22% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.19% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 74 1.09% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.38% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 85 1.26% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6759 # Writes before turning the bus around for reads +system.physmem.totQLat 5409044047 # Total ticks spent queuing +system.physmem.totMemAccLat 9164425297 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1001435000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27006.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45106.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 45756.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.71 # Average write queue length when enqueuing -system.physmem.readRowHits 166028 # Number of row buffer hits during reads -system.physmem.writeRowHits 80563 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes -system.physmem.avgGap 8311633.41 # Average gap between requests -system.physmem.pageHitRate 72.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 367945200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 200763750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 819124800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 465775920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186081086880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85063480605 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634767041000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1907765218155 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.632478 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719452348147 # Time in different power states -system.physmem_0.memoryStateTime::REF 95133480000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.87 # Average write queue length when enqueuing +system.physmem.readRowHits 166261 # Number of row buffer hits during reads +system.physmem.writeRowHits 80380 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.86 # Row buffer hit rate for writes +system.physmem.avgGap 8298964.51 # Average gap between requests +system.physmem.pageHitRate 72.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 368829720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 201246375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 820489800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 465801840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85113851220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634657451750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1907701637745 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.635783 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719265528725 # Time in different power states +system.physmem_0.memoryStateTime::REF 95129840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34391644853 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34469380775 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328497120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179239500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 740688000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433239840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186081086880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83753939520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635915761250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1907432452110 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.515676 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721369982715 # Time in different power states -system.physmem_1.memoryStateTime::REF 95133480000 # Time in different power states +system.physmem_1.actEnergy 330840720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180518250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 434257200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83792356380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635816657750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1907370338340 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.519491 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721199868682 # Time in different power states +system.physmem_1.memoryStateTime::REF 95129840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32475502785 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32535082068 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -364,15 +361,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 36411615 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17748077 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1698439 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20740706 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 15063288 # Number of BTB hits +system.cpu0.branchPred.lookups 36420174 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17682232 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1669191 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20721489 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 15026104 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.626689 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11337600 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 822333 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.514596 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11397312 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 800928 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -403,57 +400,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 73296 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 73296 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47393 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25903 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 73296 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 73296 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 73296 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7538 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12243.300610 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11373.544979 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7165.218707 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7499 99.48% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 33 0.44% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 73306 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 73306 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47488 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25818 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 73306 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 73306 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 73306 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7529 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12317.505645 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.047410 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7148.063589 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7474 99.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 46 0.61% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7538 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7529 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5846 77.55% 77.55% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1692 22.45% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7538 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73296 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5847 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1682 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7529 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73306 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73296 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7538 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7529 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7538 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 80834 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7529 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 80835 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24914388 # DTB read hits -system.cpu0.dtb.read_misses 66763 # DTB read misses -system.cpu0.dtb.write_hits 18539888 # DTB write hits -system.cpu0.dtb.write_misses 6533 # DTB write misses +system.cpu0.dtb.read_hits 24946697 # DTB read hits +system.cpu0.dtb.read_misses 66576 # DTB read misses +system.cpu0.dtb.write_hits 18555175 # DTB write hits +system.cpu0.dtb.write_misses 6730 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3822 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2016 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24981151 # DTB read accesses -system.cpu0.dtb.write_accesses 18546421 # DTB write accesses +system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25013273 # DTB read accesses +system.cpu0.dtb.write_accesses 18561905 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43454276 # DTB hits -system.cpu0.dtb.misses 73296 # DTB misses -system.cpu0.dtb.accesses 43527572 # DTB accesses +system.cpu0.dtb.hits 43501872 # DTB hits +system.cpu0.dtb.misses 73306 # DTB misses +system.cpu0.dtb.accesses 43575178 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,37 +480,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 4166 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4166 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walks 4169 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4169 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3842 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4166 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4166 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4166 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2675 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12725.794393 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12032.430474 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5005.050560 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2427 90.73% 90.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 233 8.71% 99.44% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 14 0.52% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3845 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4169 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12688.506177 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11997.245115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5018.704234 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2423 90.72% 90.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 228 8.54% 99.25% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 18 0.67% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2675 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2671 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2356 88.07% 88.07% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 319 11.93% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2675 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2352 88.06% 88.06% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 319 11.94% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2671 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4166 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4166 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4169 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4169 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2675 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2675 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 71495102 # ITB inst hits -system.cpu0.itb.inst_misses 4166 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2671 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2671 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6840 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 71444406 # ITB inst hits +system.cpu0.itb.inst_misses 4169 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -522,131 +520,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2450 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2449 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 8197 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 8126 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71499268 # ITB inst accesses -system.cpu0.itb.hits 71495102 # DTB hits -system.cpu0.itb.misses 4166 # DTB misses -system.cpu0.itb.accesses 71499268 # DTB accesses -system.cpu0.numCycles 248928104 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 71448575 # ITB inst accesses +system.cpu0.itb.hits 71444406 # DTB hits +system.cpu0.itb.misses 4169 # DTB misses +system.cpu0.itb.accesses 71448575 # DTB accesses +system.cpu0.numCycles 248815256 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 113059938 # Number of instructions committed -system.cpu0.committedOps 136701894 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8937139 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1889 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5449058014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.201736 # CPI: cycles per instruction -system.cpu0.ipc 0.454187 # IPC: instructions per cycle +system.cpu0.committedInsts 113230333 # Number of instructions committed +system.cpu0.committedOps 136910947 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8928789 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1886 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5448949721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.197426 # CPI: cycles per instruction +system.cpu0.ipc 0.455078 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed -system.cpu0.tickCycles 199965513 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 48962591 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 758556 # number of replacements -system.cpu0.dcache.tags.tagsinuse 498.399366 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41853464 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 759068 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.137964 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed +system.cpu0.tickCycles 199822657 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 48992599 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 758548 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.039628 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41909246 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 759060 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.212033 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.399366 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973436 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.973436 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.039628 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974687 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.974687 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86857605 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86857605 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23301250 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23301250 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17363998 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17363998 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329371 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 329371 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374920 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374920 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370784 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 370784 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40665248 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40665248 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40994619 # number of overall hits -system.cpu0.dcache.overall_hits::total 40994619 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 492930 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 492930 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 604783 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 604783 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 142057 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 142057 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21393 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21393 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20582 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20582 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1097713 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1097713 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1239770 # number of overall misses -system.cpu0.dcache.overall_misses::total 1239770 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6978123000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6978123000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12569253000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12569253000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330022000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330022000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 544680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 544680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 19547376000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 19547376000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 19547376000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 19547376000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23794180 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23794180 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17968781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17968781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471428 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 471428 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396313 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396313 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391366 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391366 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41762961 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41762961 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42234389 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42234389 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020716 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020716 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033657 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033657 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301333 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301333 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053980 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053980 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052590 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052590 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026284 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026284 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029355 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029355 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14156.417747 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14156.417747 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20783.079220 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20783.079220 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15426.634881 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15426.634881 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26463.924789 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26463.924789 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 86968977 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 86968977 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23338731 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23338731 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17382396 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17382396 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329314 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 329314 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374886 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374886 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370842 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370842 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 40721127 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 40721127 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 41050441 # number of overall hits +system.cpu0.dcache.overall_hits::total 41050441 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 492920 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 492920 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 604804 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 604804 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141961 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141961 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21406 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21406 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20501 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20501 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1097724 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1097724 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1239685 # number of overall misses +system.cpu0.dcache.overall_misses::total 1239685 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6985498500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6985498500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12567334500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12567334500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329657000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 329657000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 538169500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 538169500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1008000 # number of StoreCondFailReq miss cycles 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+system.cpu0.dcache.ReadReq_miss_rate::total 0.020683 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033624 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.033624 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301228 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301228 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054016 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054016 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052386 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052386 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026250 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026250 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029314 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029314 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14171.667816 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14171.667816 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20779.185488 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20779.185488 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15400.214893 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15400.214893 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26250.890200 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26250.890200 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17807.364949 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17807.364949 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.937416 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15766.937416 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17812.157701 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17812.157701 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15772.420413 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15772.420413 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,149 +653,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 758556 # number of writebacks -system.cpu0.dcache.writebacks::total 758556 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75954 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 75954 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266286 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 266286 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14845 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14845 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 342240 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 342240 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 342240 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 342240 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416976 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 416976 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 338497 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 338497 # number of WriteReq MSHR misses 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of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1805226500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1805226500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104756500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104756500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 524110500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 524110500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 625500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403740500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12403740500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14208967000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14208967000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702515500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702515500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452693000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452693000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12155208500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12155208500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017524 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017524 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018838 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018838 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230022 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230022 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016522 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016522 # mshr miss rate for LoadLockedReq accesses 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21021.016434 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16647.391621 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16647.391621 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15998.243739 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15998.243739 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25464.507822 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25464.507822 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 758548 # number of writebacks +system.cpu0.dcache.writebacks::total 758548 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75935 # number of ReadReq MSHR hits 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MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12154368000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12154368000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230025 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230025 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016483 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016483 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052386 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052386 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018067 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018067 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020429 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020429 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12686.046261 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12686.046261 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21011.547641 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21011.547641 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16697.555463 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16697.555463 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.542560 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.542560 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25251.524316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25251.524316 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16418.509331 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16418.509331 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16447.238839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16447.238839 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209146.425562 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209146.425562 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189830.559811 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189830.559811 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200016.595086 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200016.595086 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16416.670086 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16416.670086 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16451.914707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16451.914707 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.193951 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.193951 # average ReadReq mshr uncacheable latency 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-system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 145014717 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 145014717 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69444830 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69444830 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69444830 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69444830 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69444830 # number of overall hits -system.cpu0.icache.overall_hits::total 69444830 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 2041686 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2041686 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 2041686 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2041686 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 2041686 # number of overall misses -system.cpu0.icache.overall_misses::total 2041686 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20560339500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20560339500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20560339500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20560339500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20560339500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20560339500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 71486516 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 71486516 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 71486516 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 71486516 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 71486516 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 71486516 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028560 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028560 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028560 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028560 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028560 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028560 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10070.275008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10070.275008 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10070.275008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10070.275008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10070.275008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10070.275008 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 144916894 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 144916894 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69390799 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69390799 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69390799 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69390799 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69390799 # number of overall hits +system.cpu0.icache.overall_hits::total 69390799 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 2045099 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2045099 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 2045099 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2045099 # number of demand (read+write) misses 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 71435898 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 71435898 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 71435898 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028628 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028628 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028628 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028628 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028628 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028628 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.333805 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.333805 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10064.333805 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10064.333805 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,337 +804,336 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 2041160 # number of writebacks -system.cpu0.icache.writebacks::total 2041160 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2041686 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 2041686 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 2041686 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 2041686 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 2041686 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 2041686 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 2044571 # number of writebacks +system.cpu0.icache.writebacks::total 2044571 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2045099 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 2045099 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 2045099 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 2045099 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 2045099 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 2045099 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19539497000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19539497000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19539497000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19539497000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19539497000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19539497000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19560010000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19560010000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19560010000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19560010000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19560010000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19560010000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028560 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028560 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028560 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9570.275253 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9570.275253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9570.275253 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028628 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028628 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.334049 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1926179 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1926371 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 166 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927519 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1927689 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 149 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 244645 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 305884 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16117.392846 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4898605 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 322066 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.209941 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 245495 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 305066 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16110.532476 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4906564 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 321213 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.275110 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14778.459491 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.434424 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065090 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1278.433841 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.902006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003689 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14727.121799 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.543151 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067969 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1324.799556 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.898872 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 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44445.898363 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64088.648483 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201141.323681 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193860.415972 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182312.630553 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182312.630553 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201169.028372 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193883.482590 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182323.863241 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182323.863241 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192241.760050 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188732.747959 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192260.833429 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188750.123690 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 5755750 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900650 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 351752 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 347037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4715 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 143210 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2766468 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 746011 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2247535 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 246533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 331594 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87502 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 300476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 297107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2041686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3118 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6096444 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2755852 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13844 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 190303 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 9056443 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 259253824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104429286 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 364416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 364070870 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1078661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4070756 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104237 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.309335 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 5762889 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2904395 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 45067 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 350664 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 143133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2769477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 745212 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2295997 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 245518 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 331271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87260 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42942 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114488 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 300512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 297211 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2045099 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606063 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3097 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6142602 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2764050 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13802 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 189783 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9110237 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261989504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104964478 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23152 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 362636 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 367339770 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1076533 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4071717 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104210 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.309410 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3651149 89.69% 89.69% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 414892 10.19% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4715 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3652260 89.70% 89.70% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 414602 10.18% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4855 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4070756 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5766247494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4071717 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5772987994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116466956 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116128992 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3069095112 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3074216608 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1306223847 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1306190305 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 8018479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8023481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 99225447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 99154439 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3641195 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2056746 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 213596 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2171070 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1462919 # Number of BTB hits +system.cpu1.branchPred.lookups 3635973 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2046610 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 209049 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2276641 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1455770 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.382397 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 753966 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 56559 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 63.943766 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 756757 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 55280 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1295,57 +1292,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 23130 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 23130 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18836 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4294 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 23130 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 23130 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 23130 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1830 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11932.513661 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11127.774947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7404.648675 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1668 91.15% 91.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 148 8.09% 99.23% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.44% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.16% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1830 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 23538 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 23538 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19270 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4268 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 23538 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 23538 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 23538 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1839 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11777.052746 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10980.884481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6685.927584 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1677 91.19% 91.19% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 150 8.16% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.38% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1839 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1322 72.24% 72.24% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 508 27.76% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1830 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23130 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1325 72.05% 72.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 514 27.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1839 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23538 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23130 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1830 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23538 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1839 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1830 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24960 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1839 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 25377 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3607725 # DTB read hits -system.cpu1.dtb.read_misses 21408 # DTB read misses -system.cpu1.dtb.write_hits 2997772 # DTB write hits -system.cpu1.dtb.write_misses 1722 # DTB write misses +system.cpu1.dtb.read_hits 3603943 # DTB read hits +system.cpu1.dtb.read_misses 21681 # DTB read misses +system.cpu1.dtb.write_hits 2994136 # DTB write hits +system.cpu1.dtb.write_misses 1857 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1725 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 120 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 128 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3629133 # DTB read accesses -system.cpu1.dtb.write_accesses 2999494 # DTB write accesses +system.cpu1.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3625624 # DTB read accesses +system.cpu1.dtb.write_accesses 2995993 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6605497 # DTB hits -system.cpu1.dtb.misses 23130 # DTB misses -system.cpu1.dtb.accesses 6628627 # DTB accesses +system.cpu1.dtb.hits 6598079 # DTB hits +system.cpu1.dtb.misses 23538 # DTB misses +system.cpu1.dtb.accesses 6621617 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,44 +1372,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1936 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1936 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 152 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1784 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1936 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11855.029586 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11358.377652 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4391.934541 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 130 15.38% 15.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 557 65.92% 81.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.25% 94.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 22 2.60% 97.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.36% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 2 0.24% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.71% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 1941 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1941 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1790 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1941 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1941 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1941 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 844 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11680.687204 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11150.609492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4460.342613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 146 17.30% 17.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 544 64.45% 81.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.27% 95.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 21 2.49% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 844 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 705 83.53% 83.53% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 139 16.47% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 844 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1936 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1936 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1941 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1941 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2781 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 6961088 # ITB inst hits -system.cpu1.itb.inst_misses 1936 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 844 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 844 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2785 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 6953743 # ITB inst hits +system.cpu1.itb.inst_misses 1941 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1421,130 +1418,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 908 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1058 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1049 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6963024 # ITB inst accesses -system.cpu1.itb.hits 6961088 # DTB hits -system.cpu1.itb.misses 1936 # DTB misses -system.cpu1.itb.accesses 6963024 # DTB accesses -system.cpu1.numCycles 40816703 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6955684 # ITB inst accesses +system.cpu1.itb.hits 6953743 # DTB hits +system.cpu1.itb.misses 1941 # DTB misses +system.cpu1.itb.accesses 6955684 # DTB accesses +system.cpu1.numCycles 40734093 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 14109392 # Number of instructions committed -system.cpu1.committedOps 17295649 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1386756 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5656506173 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.892875 # CPI: cycles per instruction -system.cpu1.ipc 0.345677 # IPC: instructions per cycle +system.cpu1.committedInsts 14107719 # Number of instructions committed +system.cpu1.committedOps 17288156 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1387486 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2746 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5656373541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.887362 # CPI: cycles per instruction +system.cpu1.ipc 0.346337 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2772 # number of quiesce instructions executed -system.cpu1.tickCycles 27557255 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 13259448 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 157096 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.586306 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6254726 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157444 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.726671 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91652045000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.586306 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.928880 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.928880 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 2746 # number of quiesce instructions executed +system.cpu1.tickCycles 27498026 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 13236067 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 156251 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.671754 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6246920 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 156599 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.891187 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91622282000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.671754 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927093 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.927093 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13266107 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13266107 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3282974 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3282974 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2751908 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2751908 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42647 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42647 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70687 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70687 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62029 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 62029 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6034882 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6034882 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6077529 # number of overall hits -system.cpu1.dcache.overall_hits::total 6077529 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 135266 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 135266 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 122118 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 122118 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24580 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24580 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16502 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16502 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23395 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23395 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 257384 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 257384 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 281964 # number of overall misses -system.cpu1.dcache.overall_misses::total 281964 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2192537500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2192537500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4529521000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4529521000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 318889500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 318889500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 637518000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 637518000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6722058500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6722058500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6722058500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6722058500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3418240 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3418240 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2874026 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2874026 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67227 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 67227 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87189 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87189 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85424 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85424 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6292266 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6292266 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6359493 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6359493 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039572 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039572 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042490 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.042490 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.365627 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.365627 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189267 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189267 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273869 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273869 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040905 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040905 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044337 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044337 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16209.080626 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16209.080626 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37091.346075 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37091.346075 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19324.294025 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19324.294025 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27250.181663 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27250.181663 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 13254229 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13254229 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3282688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3282688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2748164 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2748164 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42687 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42687 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70657 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70657 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61986 # number of StoreCondReq hits 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26116.846813 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23840.130300 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23840.130300 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26089.294219 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26089.294219 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23818.719484 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23818.719484 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1553,149 +1550,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan 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LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4788 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 201448 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 201448 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 225334 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 225334 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2976 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2976 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2312 # number of WriteReq MSHR uncacheable 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MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5045383500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 252039500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 252039500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641439000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641439000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035611 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035611 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.355939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.355939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054944 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054944 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274041 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274041 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for demand accesses 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average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22411.685502 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130920.450723 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130920.450723 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108922.760710 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108922.760710 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121299.583649 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121299.583649 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22802.005977 # average overall mshr miss latency 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occupancy +system.cpu1.icache.tags.replacements 863100 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.134862 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6088925 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 863612 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.050533 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73321501000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.134862 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974873 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974873 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 460 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14784438 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14784438 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6095160 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6095160 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6095160 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6095160 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6095160 # number of overall hits -system.cpu1.icache.overall_hits::total 6095160 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 864706 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 864706 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 864706 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 864706 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 864706 # number of overall misses -system.cpu1.icache.overall_misses::total 864706 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7648423000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7648423000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7648423000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7648423000 # number of demand (read+write) miss cycles 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data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6088925 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6088925 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6088925 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6088925 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6088925 # number of overall hits +system.cpu1.icache.overall_hits::total 6088925 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 863612 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 863612 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 863612 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 863612 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 863612 # number of overall misses +system.cpu1.icache.overall_misses::total 863612 # number of overall misses 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miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8850.454255 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8850.454255 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1704,457 +1701,447 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 864194 # number of writebacks -system.cpu1.icache.writebacks::total 864194 # number of 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system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124242 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124242 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124242 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8345.113831 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8345.113831 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8345.113831 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124215 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for demand accesses 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137058.035714 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 119025 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 119084 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 52 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 119510 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 119557 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 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average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32777.297974 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122897.914564 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123121.555916 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101369.104284 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101369.104284 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122826.444892 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123052.461140 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101459.558824 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101459.558824 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113482.115821 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113805.411416 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113484.493192 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113807.500000 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 2148021 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1081444 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18331 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 178235 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 177001 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1234 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 34229 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1087159 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 125656 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 907759 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 98212 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 24432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72484 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41782 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85083 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 2143691 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1079194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 177461 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175960 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1501 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 34625 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1085487 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 125339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 924619 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 97697 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 24084 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71468 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84759 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57811 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55294 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 864706 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 235840 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2577500 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 749010 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6415 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52647 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3385572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109611648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25531190 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10780 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100892 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 135254510 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 383471 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1462314 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.140260 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.349678 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57626 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55185 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 863612 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 234129 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 33 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2590548 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 747561 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6394 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 53434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3397937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 110516736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25535556 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 102512 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 136165456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 380835 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1457969 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.140235 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.350184 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1258444 86.06% 86.06% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 202636 13.86% 99.92% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1234 0.08% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1255011 86.08% 86.08% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 201457 13.82% 99.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1501 0.10% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1462314 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2111082490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1457969 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2107221995 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78627228 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78416105 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1297343267 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1295704762 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 334901961 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 333278550 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3720499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3731000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 27451445 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 27832447 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31009 # Transaction distribution system.iobus.trans_dist::ReadResp 31009 # Transaction distribution -system.iobus.trans_dist::WriteReq 59424 # Transaction distribution -system.iobus.trans_dist::WriteResp 59424 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2173,11 +2160,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2196,63 +2183,63 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51120500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 51092500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 84500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 571500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 576000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6117000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6104500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32846500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32859000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186337026 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187096728 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.469949 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.469909 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272430408000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.469949 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904372 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904372 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272427086000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.469909 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904369 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904369 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2266,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 243 # system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32247375 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32247375 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4733187651 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4733187651 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32247375 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32247375 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32247375 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32247375 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31652377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31652377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4575926351 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4575926351 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31652377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31652377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31652377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31652377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2290,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 132705.246914 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 132705.246914 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130664.411744 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130664.411744 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 132705.246914 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 132705.246914 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 132705.246914 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 132705.246914 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 621 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130256.695473 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130256.695473 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126323.055184 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126323.055184 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130256.695473 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130256.695473 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.860759 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2316,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20097375 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20097375 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2921987651 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2921987651 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20097375 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20097375 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20097375 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20097375 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19502377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19502377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763035342 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2763035342 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19502377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19502377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19502377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19502377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2332,304 +2319,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82705.246914 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82705.246914 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80664.411744 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80664.411744 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82705.246914 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82705.246914 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82705.246914 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82705.246914 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80256.695473 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80256.695473 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76276.373178 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76276.373178 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 131701 # number of replacements -system.l2c.tags.tagsinuse 63232.493895 # Cycle average of tags in use -system.l2c.tags.total_refs 477114 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195835 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.436306 # Average number of references to valid blocks. +system.l2c.tags.replacements 132173 # number of replacements +system.l2c.tags.tagsinuse 63220.230545 # Cycle average of tags in use +system.l2c.tags.total_refs 476061 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 196324 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.424874 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13499.183462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.189305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030804 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9276.099032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2886.907500 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33207.909394 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.955383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1918.551839 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 583.845643 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1772.821532 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205981 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.141542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000091 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008909 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964851 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 28913 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 35162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4903 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23890 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 486 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3361 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31288 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.441177 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.536530 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6403013 # Number of tag accesses -system.l2c.tags.data_accesses 6403013 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 266916 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 266916 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 34147 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2219 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36366 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2260 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 929 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3189 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4341 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1335 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5676 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits 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overall hits -system.l2c.overall_hits::cpu1.dtb.walker 78 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits -system.l2c.overall_hits::cpu1.inst 9744 # number of overall hits -system.l2c.overall_hits::cpu1.data 6865 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3532 # number of overall hits -system.l2c.overall_hits::total 174061 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 10466 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2461 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12927 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 842 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1269 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2111 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11510 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8279 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19789 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 132 # number of ReadSharedReq misses +system.l2c.tags.occ_blocks::writebacks 13508.269285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.219026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9248.082270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2930.331388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33200.975902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.874579 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1907.881821 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 574.003662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1760.558132 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.206120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001270 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.141115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044713 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029112 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026864 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.964664 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29038 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 35051 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23744 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 61 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 489 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3341 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31190 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.443085 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.534836 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6395223 # Number of tag accesses +system.l2c.tags.data_accesses 6395223 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 266844 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 266844 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 34054 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 36240 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2212 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 949 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3161 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4419 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1324 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5743 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 427 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 47128 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 51485 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49241 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 65 # number of ReadSharedReq hits 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rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.113636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.244574 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.590492 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.612677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.529591 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.236984 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011111 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.322518 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.275371 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.728463 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.113636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.244574 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.590492 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.612677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.529591 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75618.001147 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75302.316132 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75557.902065 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77386.579572 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76685.185185 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76964.945523 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 136555.256299 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121725.510327 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 130351.028349 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.236663 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.528066 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.264073 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.268760 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.571944 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396986 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.721287 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.860924 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.773675 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.324321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.161086 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.232840 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.513239 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.276099 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.591143 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.531121 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.241563 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.276099 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.240331 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.591143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.586246 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.531121 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72833.870051 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72392.681930 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72750.884343 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74662.976630 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73882.886435 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.650168 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138043.153987 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122120.487067 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 131395.732529 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127460.264901 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129241.975309 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137039.470064 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127634.534999 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127863.691432 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137674.636844 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132369.214537 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122955.601576 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 136364.055714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133217.171091 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132369.214537 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122955.601576 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 136364.055714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133217.171091 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183140.762006 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.232654 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105001.010101 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169974.645290 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165307.861022 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84366.724362 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159280.634767 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104928.524050 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169983.978587 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165318.379779 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84456.099481 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159294.225881 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174711.869148 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174730.526324 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95971.312251 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 165238.859320 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95972.564617 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 165249.825387 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 39046 # Transaction distribution -system.membus.trans_dist::ReadResp 215465 # Transaction distribution -system.membus.trans_dist::WriteReq 31035 # Transaction distribution -system.membus.trans_dist::WriteResp 31035 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138266 # Transaction distribution -system.membus.trans_dist::CleanEvict 17702 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74461 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40765 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15160 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40157 # Transaction distribution -system.membus.trans_dist::ReadExResp 19667 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176419 # Transaction distribution +system.membus.trans_dist::ReadReq 39041 # Transaction distribution +system.membus.trans_dist::ReadResp 215941 # Transaction distribution +system.membus.trans_dist::WriteReq 31034 # Transaction distribution +system.membus.trans_dist::WriteResp 31034 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138436 # Transaction distribution +system.membus.trans_dist::CleanEvict 18070 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73582 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40721 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 40108 # Transaction distribution +system.membus.trans_dist::ReadExResp 19531 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176900 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 679941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 802135 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 911060 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14216 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 787125 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860056 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19320688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19513284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19353628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19546218 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21831428 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 121126 # Total snoops (count) -system.membus.snoop_fanout::samples 594326 # Request fanout histogram +system.membus.pkt_size::total 21864362 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120262 # Total snoops (count) +system.membus.snoop_fanout::samples 594139 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 594326 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 594139 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 594326 # Request fanout histogram -system.membus.reqLayer0.occupancy 91340500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 594139 # Request fanout histogram +system.membus.reqLayer0.occupancy 91324000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12352499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12307500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1009821404 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1010896317 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1176071579 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1147679286 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64144132 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1341127 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2945,52 +2930,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1045963 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 564632 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 154673 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 994 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 39049 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 502457 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 405200 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105572 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 110705 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43954 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 154659 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51324 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51324 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 463423 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 1042334 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 562614 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 153410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21132 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1023 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 500861 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31034 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31034 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 405302 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 139265 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109721 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153603 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51189 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51189 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 461832 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1306764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270016 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1576780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36870810 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4377514 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41248324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449455 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 943932 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.340597 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.476127 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1332417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1606737 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36835698 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4378808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41214506 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 447707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 941615 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.339048 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.475676 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 623426 66.05% 66.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 319512 33.85% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 994 0.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 623385 66.20% 66.20% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 317207 33.69% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1023 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 943932 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 904213819 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 941615 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 901922668 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 343121 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 693007025 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 690834076 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 215048953 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 214047025 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 456fdbc09..11bd5dafc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858559 # Number of seconds simulated -sim_ticks 2858558607500 # Number of ticks simulated -final_tick 2858558607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858536 # Number of seconds simulated +sim_ticks 2858536032500 # Number of ticks simulated +final_tick 2858536032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164210 # Simulator instruction rate (inst/s) -host_op_rate 198546 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4188709682 # Simulator tick rate (ticks/s) -host_mem_usage 583452 # Number of bytes of host memory used -host_seconds 682.44 # Real time elapsed on the host -sim_insts 112064376 # Number of instructions simulated -sim_ops 135496266 # Number of ops (including micro ops) simulated +host_inst_rate 177299 # Simulator instruction rate (inst/s) +host_op_rate 214372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4522420422 # Simulator tick rate (ticks/s) +host_mem_usage 585260 # Number of bytes of host memory used +host_seconds 632.08 # Real time elapsed on the host +sim_insts 112067614 # Number of instructions simulated +sim_ops 135500271 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1707776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9151404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9152172 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10868268 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1707776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1707776 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7938560 # Number of bytes written to this memory +system.physmem.bytes_read::total 10869356 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7939328 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7956084 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 126 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143512 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7956852 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170338 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124040 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170355 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124052 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 597426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3201405 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128433 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 597542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3201699 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 597426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597426 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2777120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 597542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 597542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2777411 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2777120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2821 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 597426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3207535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2783541 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2777411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 597542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3207829 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6585260 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170338 # Number of read requests accepted -system.physmem.writeReqs 128421 # Number of write requests accepted -system.physmem.readBursts 170338 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128421 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10893184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7968384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10868268 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7956084 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6585961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170355 # Number of read requests accepted +system.physmem.writeReqs 128433 # Number of write requests accepted +system.physmem.readBursts 170355 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128433 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10894592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue +system.physmem.bytesWritten 7969344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10869356 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7956852 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49420 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10768 # Per bank write bursts -system.physmem.perBankRdBursts::1 10789 # Per bank write bursts -system.physmem.perBankRdBursts::2 10902 # Per bank write bursts -system.physmem.perBankRdBursts::3 10725 # Per bank write bursts -system.physmem.perBankRdBursts::4 14061 # Per bank write bursts -system.physmem.perBankRdBursts::5 10215 # Per bank write bursts -system.physmem.perBankRdBursts::6 11008 # Per bank write bursts -system.physmem.perBankRdBursts::7 10953 # Per bank write bursts -system.physmem.perBankRdBursts::8 9930 # Per bank write bursts -system.physmem.perBankRdBursts::9 10231 # Per bank write bursts -system.physmem.perBankRdBursts::10 9936 # Per bank write bursts -system.physmem.perBankRdBursts::11 9160 # Per bank write bursts -system.physmem.perBankRdBursts::12 10275 # Per bank write bursts -system.physmem.perBankRdBursts::13 11196 # Per bank write bursts -system.physmem.perBankRdBursts::14 10249 # Per bank write bursts -system.physmem.perBankRdBursts::15 9808 # Per bank write bursts -system.physmem.perBankWrBursts::0 8070 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10771 # Per bank write bursts +system.physmem.perBankRdBursts::1 10790 # Per bank write bursts +system.physmem.perBankRdBursts::2 10898 # Per bank write bursts +system.physmem.perBankRdBursts::3 10736 # Per bank write bursts +system.physmem.perBankRdBursts::4 14068 # Per bank write bursts +system.physmem.perBankRdBursts::5 10207 # Per bank write bursts +system.physmem.perBankRdBursts::6 11005 # Per bank write bursts +system.physmem.perBankRdBursts::7 10952 # Per bank write bursts +system.physmem.perBankRdBursts::8 9928 # Per bank write bursts +system.physmem.perBankRdBursts::9 10232 # Per bank write bursts +system.physmem.perBankRdBursts::10 9939 # Per bank write bursts +system.physmem.perBankRdBursts::11 9163 # Per bank write bursts +system.physmem.perBankRdBursts::12 10281 # Per bank write bursts +system.physmem.perBankRdBursts::13 11195 # Per bank write bursts +system.physmem.perBankRdBursts::14 10251 # Per bank write bursts +system.physmem.perBankRdBursts::15 9812 # Per bank write bursts +system.physmem.perBankWrBursts::0 8074 # Per bank write bursts system.physmem.perBankWrBursts::1 8145 # Per bank write bursts -system.physmem.perBankWrBursts::2 8537 # Per bank write bursts -system.physmem.perBankWrBursts::3 8263 # Per bank write bursts -system.physmem.perBankWrBursts::4 7645 # Per bank write bursts -system.physmem.perBankWrBursts::5 7425 # Per bank write bursts -system.physmem.perBankWrBursts::6 7936 # Per bank write bursts -system.physmem.perBankWrBursts::7 8025 # Per bank write bursts -system.physmem.perBankWrBursts::8 7562 # Per bank write bursts -system.physmem.perBankWrBursts::9 7724 # Per bank write bursts -system.physmem.perBankWrBursts::10 7502 # Per bank write bursts -system.physmem.perBankWrBursts::11 7049 # Per bank write bursts -system.physmem.perBankWrBursts::12 7677 # Per bank write bursts -system.physmem.perBankWrBursts::13 8301 # Per bank write bursts -system.physmem.perBankWrBursts::14 7534 # Per bank write bursts -system.physmem.perBankWrBursts::15 7111 # Per bank write bursts +system.physmem.perBankWrBursts::2 8532 # Per bank write bursts +system.physmem.perBankWrBursts::3 8274 # Per bank write bursts +system.physmem.perBankWrBursts::4 7651 # Per bank write bursts +system.physmem.perBankWrBursts::5 7419 # Per bank write bursts +system.physmem.perBankWrBursts::6 7942 # Per bank write bursts +system.physmem.perBankWrBursts::7 8023 # Per bank write bursts +system.physmem.perBankWrBursts::8 7561 # Per bank write bursts +system.physmem.perBankWrBursts::9 7722 # Per bank write bursts +system.physmem.perBankWrBursts::10 7504 # Per bank write bursts +system.physmem.perBankWrBursts::11 7050 # Per bank write bursts +system.physmem.perBankWrBursts::12 7678 # Per bank write bursts +system.physmem.perBankWrBursts::13 8296 # Per bank write bursts +system.physmem.perBankWrBursts::14 7536 # Per bank write bursts +system.physmem.perBankWrBursts::15 7114 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2858558162000 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 2858535588000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169781 # Read request sizes (log2) +system.physmem.readPktSize::6 169798 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124040 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 292 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124052 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,113 +159,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61425 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.065592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.884404 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.926844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22406 36.48% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14897 24.25% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6725 10.95% 71.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3636 5.92% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2599 4.23% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1993 3.24% 85.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1038 1.69% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1103 1.80% 88.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7028 11.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61425 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.335689 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 568.600385 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6225 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.093102 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.837118 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.066728 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22431 36.52% 36.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14913 24.28% 60.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6673 10.86% 71.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3644 5.93% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2598 4.23% 81.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2007 3.27% 85.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1018 1.66% 86.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1090 1.77% 88.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7053 11.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61427 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6076 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.016458 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 575.560734 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6075 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.997751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.449468 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.121367 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5404 86.80% 86.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 111 1.78% 88.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 39 0.63% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 2.91% 92.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 25 0.40% 92.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 156 2.51% 95.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 42 0.67% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.13% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.31% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.19% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 165 2.65% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.35% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads -system.physmem.totQLat 1816793750 # Total ticks spent queuing -system.physmem.totMemAccLat 5008156250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10674.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6076 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.495967 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.543257 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.157568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5370 88.40% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 94 1.55% 89.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 44 0.72% 90.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 49 0.81% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 46 0.76% 92.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.41% 92.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 47 0.77% 93.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.16% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 146 2.40% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 96.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.13% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.16% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 76 1.25% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.40% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 88 1.45% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.13% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.13% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads +system.physmem.totQLat 1806632250 # Total ticks spent queuing +system.physmem.totMemAccLat 4998407250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 851140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10613.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29424.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29363.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -275,40 +274,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.34 # Average write queue length when enqueuing -system.physmem.readRowHits 139582 # Number of row buffer hits during reads -system.physmem.writeRowHits 93704 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.23 # Average write queue length when enqueuing +system.physmem.readRowHits 139599 # Number of row buffer hits during reads +system.physmem.writeRowHits 93721 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.24 # Row buffer hit rate for writes -system.physmem.avgGap 9568107.28 # Average gap between requests +system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes +system.physmem.avgGap 9567103.06 # Average gap between requests system.physmem.pageHitRate 79.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242131680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132115500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 697483800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 415018080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186707124240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87047496990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638777600000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1914018970290 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.574900 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726091168500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95453540000 # Time in different power states +system.physmem_0.actEnergy 242282880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132198000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 697530600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 415063440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87013655235 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638793270500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1913999599215 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.573595 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726118833250 # Time in different power states +system.physmem_0.memoryStateTime::REF 95452760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 37013727750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36964415750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 222241320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121262625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 630115200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 630240000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 391780800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186707124240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85156608060 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640436274500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913665406745 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.451214 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728865158250 # Time in different power states -system.physmem_1.memoryStateTime::REF 95453540000 # Time in different power states +system.physmem_1.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85155956550 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640422830750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913649653535 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.451174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2728842952750 # Time in different power states +system.physmem_1.memoryStateTime::REF 95452760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34239762750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34240173750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -328,15 +327,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31021791 # Number of BP lookups -system.cpu.branchPred.condPredicted 16837881 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2510623 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18481524 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13330573 # Number of BTB hits +system.cpu.branchPred.lookups 31018850 # Number of BP lookups +system.cpu.branchPred.condPredicted 16837096 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2510697 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18467994 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13332341 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.129187 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7835102 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1517797 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.191603 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7836957 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1518082 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -367,55 +366,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66394 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66394 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43409 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22985 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66394 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66394 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66394 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7806 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12863.502434 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10677.385301 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8586.171053 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7798 99.90% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66340 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66340 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43350 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22990 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66340 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66340 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66340 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7812 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8573.106392 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7804 99.90% 99.90% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7806 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7812 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6430 82.37% 82.37% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1376 17.63% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7806 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66394 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6422 82.21% 82.21% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1390 17.79% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7812 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66340 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66394 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7806 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66340 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7812 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7806 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74200 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7812 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74152 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24767538 # DTB read hits -system.cpu.dtb.read_misses 59423 # DTB read misses -system.cpu.dtb.write_hits 19447940 # DTB write hits -system.cpu.dtb.write_misses 6971 # DTB write misses +system.cpu.dtb.read_hits 24767530 # DTB read hits +system.cpu.dtb.read_misses 59359 # DTB read misses +system.cpu.dtb.write_hits 19448397 # DTB write hits +system.cpu.dtb.write_misses 6981 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1803 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4358 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 767 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24826961 # DTB read accesses -system.cpu.dtb.write_accesses 19454911 # DTB write accesses +system.cpu.dtb.perms_faults 756 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24826889 # DTB read accesses +system.cpu.dtb.write_accesses 19455378 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44215478 # DTB hits -system.cpu.dtb.misses 66394 # DTB misses -system.cpu.dtb.accesses 44281872 # DTB accesses +system.cpu.dtb.hits 44215927 # DTB hits +system.cpu.dtb.misses 66340 # DTB misses +system.cpu.dtb.accesses 44282267 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,19 +444,19 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5448 # Table walker walks requested -system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walks 5454 # Table walker walks requested +system.cpu.itb.walker.walksShort 5454 # Table walker walks initiated with short descriptors system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5127 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5133 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5454 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5454 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5454 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3187 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13028.710386 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10952.783272 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7366.378700 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2453 76.97% 76.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 733 23.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13010.982115 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7360.815983 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2457 77.09% 77.09% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 729 22.87% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3187 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution @@ -467,14 +466,14 @@ system.cpu.itb.walker.walkPageSizes::4K 2877 90.27% 90.27% # Ta system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3187 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5454 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5454 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3187 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3187 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8635 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57565583 # ITB inst hits -system.cpu.itb.inst_misses 5448 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 8641 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57568551 # ITB inst hits +system.cpu.itb.inst_misses 5454 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -487,123 +486,123 @@ system.cpu.itb.flush_entries 2975 # Nu system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8500 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8464 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57571031 # ITB inst accesses -system.cpu.itb.hits 57565583 # DTB hits -system.cpu.itb.misses 5448 # DTB misses -system.cpu.itb.accesses 57571031 # DTB accesses -system.cpu.numCycles 333209630 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57574005 # ITB inst accesses +system.cpu.itb.hits 57568551 # DTB hits +system.cpu.itb.misses 5454 # DTB misses +system.cpu.itb.accesses 57574005 # DTB accesses +system.cpu.numCycles 333181944 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112064376 # Number of instructions committed -system.cpu.committedOps 135496266 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7785576 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112067614 # Number of instructions committed +system.cpu.committedOps 135500271 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7782146 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5383968359 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.973377 # CPI: cycles per instruction -system.cpu.ipc 0.336318 # IPC: instructions per cycle +system.cpu.quiesceCycles 5383950822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.973044 # CPI: cycles per instruction +system.cpu.ipc 0.336356 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228553577 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104656053 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842821 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.899795 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42614913 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 843333 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.531537 # Average number of references to valid blocks. +system.cpu.tickCycles 228532556 # Number of cycles that the object actually ticked +system.cpu.idleCycles 104649388 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842951 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899807 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42615127 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 843463 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.524003 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.899795 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899807 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176231729 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176231729 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23070027 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23070027 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18281270 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18281270 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356578 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356578 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443846 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443846 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460293 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460293 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41351297 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41351297 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41707875 # number of overall hits -system.cpu.dcache.overall_hits::total 41707875 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 494345 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 494345 # number of ReadReq misses +system.cpu.dcache.tags.tag_accesses 176233418 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176233418 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23069734 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23069734 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18281775 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18281775 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356571 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356571 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443857 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443857 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460299 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460299 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41351509 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41351509 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41708080 # number of overall hits +system.cpu.dcache.overall_hits::total 41708080 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 494516 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 494516 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 548690 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 548690 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 169778 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 169778 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22259 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22259 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of 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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64255.734727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14119.354227 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.354227 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14040.517658 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14040.517658 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016905 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016905 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019524 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019524 # mshr miss rate for overall accesses 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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35908.317214 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35908.317214 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32752.031894 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32752.031894 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201661.692901 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201661.692901 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.207367 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.207367 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193502.869844 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193502.869844 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35878.189726 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35878.189726 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32725.315061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32725.315061 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201663.363315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201663.363315 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.805539 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.805539 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193504.036516 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193504.036516 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2896771 # number of replacements -system.cpu.icache.tags.tagsinuse 511.208867 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54659323 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897283 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.865718 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2897049 # number of replacements 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-system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60453912 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60453912 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54659323 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54659323 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54659323 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54659323 # number of demand (read+write) hits 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demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40482979500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40482979500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57556618 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57556618 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57556618 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57556618 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57556618 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57556618 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050338 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050338 # miss rate for ReadReq accesses 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2897573 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40485768000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40485768000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40485768000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40485768000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40485768000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40485768000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57559619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57559619 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57559619 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57559619 # number of demand (read+write) accesses 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latency +system.cpu.icache.demand_avg_miss_latency::total 13972.303027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13972.303027 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,218 +758,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 2896771 # number of writebacks -system.cpu.icache.writebacks::total 2896771 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897295 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897295 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897295 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897295 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897295 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897295 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 2897049 # number of writebacks +system.cpu.icache.writebacks::total 2897049 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897573 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2897573 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2897573 # number of demand (read+write) MSHR misses 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-system.cpu.icache.demand_mshr_miss_latency::total 37585685500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37585685500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37585685500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37588196000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37588196000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37588196000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37588196000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37588196000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37588196000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050338 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050338 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050338 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050338 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050338 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050338 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12972.681587 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12972.681587 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12972.681587 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12972.681587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12972.681587 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12972.681587 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050340 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for demand accesses 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129131.411108 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96429 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65020.981729 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7029446 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 161675 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 43.478868 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96446 # number of replacements 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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000212 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001647 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982085 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982085 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10654969000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11082187000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001651 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982765 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442309 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442309 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007915 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025759 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025759 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001740 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000212 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172048 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044047 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001740 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000212 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007915 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172048 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044047 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131578.740157 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.205399 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.205399 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442303 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007916 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025777 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025777 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044049 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044049 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131854.330709 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68005.115090 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68005.115090 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118202.558700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118202.558700 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120436.573347 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120436.573347 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122368.818730 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122368.818730 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120436.573347 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118607.271587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118866.533260 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131650.793651 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120436.573347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118607.271587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118866.533260 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189159.877931 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181003.782994 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172793.956642 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172793.956642 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181471.122731 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177379.091506 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 7512196 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3771568 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 7513127 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58799 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 134847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3579536 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 134810 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579896 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 824044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2845126 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 144354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2791 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 824175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2897049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151656 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897295 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 547417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897573 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 547535 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8647216 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2645494 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161772 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11469766 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 367754112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98971817 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18836 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 289572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 467034337 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192407 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4075202 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021767 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145921 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8699695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2653154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15282 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161550 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11529681 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 371094976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98987561 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18780 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288880 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 470390197 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192578 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4075586 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021763 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145909 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3986498 97.82% 97.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 88704 2.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3986889 97.82% 97.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 88697 2.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4075202 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7433298000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4075586 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7434078000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 379376 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4352139390 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4352565871 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311523184 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1311717177 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10577994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10589994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89414413 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89368907 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1213,7 +1212,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46508500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46502500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1225,7 +1224,7 @@ system.iobus.reqLayer4.occupancy 14500 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 576500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1247,25 +1246,25 @@ system.iobus.reqLayer20.occupancy 9500 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6069000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6064500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 33518500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186322027 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187144507 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.036865 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.036750 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274891173000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036865 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064804 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064804 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 274891170000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.036750 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1279,14 +1278,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29064376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29064376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4718637651 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4718637651 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29064376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29064376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29064376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29064376 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4549676630 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4549676630 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29054877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29054877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29054877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29054877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1303,19 +1302,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124206.735043 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124206.735043 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130262.744341 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130262.744341 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124206.735043 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124206.735043 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124206.735043 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124206.735043 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 864 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124166.141026 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124166.141026 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 82 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.536585 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1329,14 +1328,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17364376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17364376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907437651 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2907437651 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17364376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17364376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17364376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17364376 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737053618 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2737053618 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17354877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17354877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17354877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17354877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1345,68 +1344,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74206.735043 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74206.735043 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80262.744341 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80262.744341 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74206.735043 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74206.735043 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74206.735043 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74206.735043 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34893 # Transaction distribution -system.membus.trans_dist::ReadResp 72281 # Transaction distribution +system.membus.trans_dist::ReadResp 72299 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124040 # Transaction distribution -system.membus.trans_dist::CleanEvict 8592 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124052 # Transaction distribution +system.membus.trans_dist::CleanEvict 8818 # Transaction distribution system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution -system.membus.trans_dist::ReadExReq 129141 # Transaction distribution -system.membus.trans_dist::ReadExResp 129141 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37388 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 129140 # Transaction distribution +system.membus.trans_dist::ReadExResp 129140 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37406 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 455331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562899 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671799 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631243 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16507232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16671017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16509088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16672873 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18988137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18989993 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 505 # Total snoops (count) -system.membus.snoop_fanout::samples 402696 # Request fanout histogram +system.membus.snoop_fanout::samples 402733 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402696 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402733 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402696 # Request fanout histogram -system.membus.reqLayer0.occupancy 87390000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402733 # Request fanout histogram +system.membus.reqLayer0.occupancy 87415500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1706000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 878074394 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 878266116 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 999225638 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 990100000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64122797 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 36baf0032..3b5f8f2cc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832913 # Number of seconds simulated -sim_ticks 2832912592000 # Number of ticks simulated -final_tick 2832912592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832892 # Number of seconds simulated +sim_ticks 2832892490000 # Number of ticks simulated +final_tick 2832892490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73621 # Simulator instruction rate (inst/s) -host_op_rate 89295 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1844379035 # Simulator tick rate (ticks/s) -host_mem_usage 584220 # Number of bytes of host memory used -host_seconds 1535.97 # Real time elapsed on the host -sim_insts 113079343 # Number of instructions simulated -sim_ops 137154534 # Number of ops (including micro ops) simulated +host_inst_rate 98762 # Simulator instruction rate (inst/s) +host_op_rate 119789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2474201806 # Simulator tick rate (ticks/s) +host_mem_usage 585008 # Number of bytes of host memory used +host_seconds 1144.97 # Real time elapsed on the host +sim_insts 113079496 # Number of instructions simulated +sim_ops 137154742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1316096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1315968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9383464 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10702120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1316096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1316096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7997312 # Number of bytes written to this memory +system.physmem.bytes_read::total 10702248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1315968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1315968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7997504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8014836 # Number of bytes written to this memory +system.physmem.bytes_written::total 8015028 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147137 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169988 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124958 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169990 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124961 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129339 # Number of write requests responded to by this memory +system.physmem.num_writes::total 129342 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 464573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3312212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 464532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3312326 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3777780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2823000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3777852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2823088 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2829186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2823000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2829274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2823088 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3318398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3318512 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6606966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169989 # Number of read requests accepted -system.physmem.writeReqs 129339 # Number of write requests accepted -system.physmem.readBursts 169989 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129339 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10867584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue -system.physmem.bytesWritten 8027584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10702184 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8014836 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6607125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169991 # Number of read requests accepted +system.physmem.writeReqs 129342 # Number of write requests accepted +system.physmem.readBursts 169991 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129342 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10867968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue +system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10702312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8015028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48490 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11395 # Per bank write bursts -system.physmem.perBankRdBursts::1 10615 # Per bank write bursts +system.physmem.perBankRdBursts::1 10614 # Per bank write bursts system.physmem.perBankRdBursts::2 11052 # Per bank write bursts system.physmem.perBankRdBursts::3 11362 # Per bank write bursts system.physmem.perBankRdBursts::4 12761 # Per bank write bursts system.physmem.perBankRdBursts::5 10093 # Per bank write bursts -system.physmem.perBankRdBursts::6 10904 # Per bank write bursts -system.physmem.perBankRdBursts::7 11084 # Per bank write bursts -system.physmem.perBankRdBursts::8 10554 # Per bank write bursts -system.physmem.perBankRdBursts::9 10523 # Per bank write bursts -system.physmem.perBankRdBursts::10 10030 # Per bank write bursts +system.physmem.perBankRdBursts::6 10908 # Per bank write bursts +system.physmem.perBankRdBursts::7 11081 # Per bank write bursts +system.physmem.perBankRdBursts::8 10555 # Per bank write bursts +system.physmem.perBankRdBursts::9 10526 # Per bank write bursts +system.physmem.perBankRdBursts::10 10031 # Per bank write bursts system.physmem.perBankRdBursts::11 8841 # Per bank write bursts -system.physmem.perBankRdBursts::12 9967 # Per bank write bursts -system.physmem.perBankRdBursts::13 10661 # Per bank write bursts -system.physmem.perBankRdBursts::14 9878 # Per bank write bursts +system.physmem.perBankRdBursts::12 9969 # Per bank write bursts +system.physmem.perBankRdBursts::13 10658 # Per bank write bursts +system.physmem.perBankRdBursts::14 9880 # Per bank write bursts system.physmem.perBankRdBursts::15 10086 # Per bank write bursts system.physmem.perBankWrBursts::0 8599 # Per bank write bursts system.physmem.perBankWrBursts::1 7964 # Per bank write bursts @@ -85,37 +85,37 @@ system.physmem.perBankWrBursts::2 8486 # Pe system.physmem.perBankWrBursts::3 8679 # Per bank write bursts system.physmem.perBankWrBursts::4 7544 # Per bank write bursts system.physmem.perBankWrBursts::5 7468 # Per bank write bursts -system.physmem.perBankWrBursts::6 8077 # Per bank write bursts -system.physmem.perBankWrBursts::7 8182 # Per bank write bursts -system.physmem.perBankWrBursts::8 8055 # Per bank write bursts -system.physmem.perBankWrBursts::9 7911 # Per bank write bursts -system.physmem.perBankWrBursts::10 7496 # Per bank write bursts +system.physmem.perBankWrBursts::6 8076 # Per bank write bursts +system.physmem.perBankWrBursts::7 8179 # Per bank write bursts +system.physmem.perBankWrBursts::8 8056 # Per bank write bursts +system.physmem.perBankWrBursts::9 7908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7497 # Per bank write bursts system.physmem.perBankWrBursts::11 6568 # Per bank write bursts system.physmem.perBankWrBursts::12 7556 # Per bank write bursts -system.physmem.perBankWrBursts::13 8042 # Per bank write bursts -system.physmem.perBankWrBursts::14 7357 # Per bank write bursts +system.physmem.perBankWrBursts::13 8041 # Per bank write bursts +system.physmem.perBankWrBursts::14 7359 # Per bank write bursts system.physmem.perBankWrBursts::15 7447 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2832912360000 # Total gap between requests +system.physmem.totGap 2832892258000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166437 # Read request sizes (log2) +system.physmem.readPktSize::6 166439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124958 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150468 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124961 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 16446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 723 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,113 +159,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.283685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.850271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.574400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23280 37.49% 37.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14997 24.15% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6479 10.43% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3584 5.77% 77.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 4.07% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1603 2.58% 84.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1574 2.53% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1048 1.69% 88.72% # Bytes accessed per row activation +system.physmem.wrQLenPdf::15 1893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.427918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.985587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.629395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23230 37.43% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15016 24.19% 61.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6492 10.46% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3585 5.78% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2536 4.09% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1572 2.53% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1564 2.52% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1071 1.73% 88.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7002 11.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62097 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.116097 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.155612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6261 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 62068 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.640729 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.576579 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6142 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6262 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.030501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.464444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.039261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5446 86.97% 86.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 116 1.85% 88.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 36 0.57% 89.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 167 2.67% 92.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.35% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 138 2.20% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 54 0.86% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.30% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.26% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.56% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.10% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.14% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.40% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6262 # Writes before turning the bus around for reads -system.physmem.totQLat 2134847750 # Total ticks spent queuing -system.physmem.totMemAccLat 5318710250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12572.28 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6143 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.417874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.493305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.002502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5451 88.74% 88.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 111 1.81% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 0.55% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.72% 91.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 0.54% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.24% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 54 0.88% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.18% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 132 2.15% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.28% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.18% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 78 1.27% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.34% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 92 1.50% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6143 # Writes before turning the bus around for reads +system.physmem.totQLat 2131723500 # Total ticks spent queuing +system.physmem.totMemAccLat 5315698500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12553.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31322.28 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31303.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s @@ -276,39 +278,39 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing -system.physmem.readRowHits 139313 # Number of row buffer hits during reads -system.physmem.writeRowHits 93826 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.79 # Row buffer hit rate for writes -system.physmem.avgGap 9464241.10 # Average gap between requests -system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247680720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135143250 # Energy for precharge commands per rank (pJ) +system.physmem.readRowHits 139329 # Number of row buffer hits during reads +system.physmem.writeRowHits 93841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes +system.physmem.avgGap 9464015.86 # Average gap between requests +system.physmem.pageHitRate 78.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 247484160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135036000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 696267000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 421193520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83693103705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626331305750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896556621545 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.472831 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705407276500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states +system.physmem_0.writeEnergy 421167600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83639897910 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626363962250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896534216840 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.470442 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705464523500 # Time in different power states +system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32908202000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32831633000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 628212000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 221749920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 120994500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 628258800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 391599360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 81799663455 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627992218250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896186400140 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.342145 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2708183660500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states +system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81914804595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627877202000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896185011095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.347174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2707992537250 # Time in different power states +system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30129768250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30298312750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -328,15 +330,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46857763 # Number of BP lookups -system.cpu.branchPred.condPredicted 24018162 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233841 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29502900 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21322687 # Number of BTB hits +system.cpu.branchPred.lookups 46858247 # Number of BP lookups +system.cpu.branchPred.condPredicted 24018458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233894 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29504756 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21322919 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.273190 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11723693 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33902 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.269430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11723897 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33908 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -387,9 +389,9 @@ system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7540 system.cpu.checker.dtb.walker.walkRequestOrigin::total 17244 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24571778 # DTB read hits +system.cpu.checker.dtb.read_hits 24571828 # DTB read hits system.cpu.checker.dtb.read_misses 8287 # DTB read misses -system.cpu.checker.dtb.write_hits 19630535 # DTB write hits +system.cpu.checker.dtb.write_hits 19630538 # DTB write hits system.cpu.checker.dtb.write_misses 1417 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -400,12 +402,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 1642 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24580065 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19631952 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24580115 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19631955 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44202313 # DTB hits +system.cpu.checker.dtb.hits 44202366 # DTB hits system.cpu.checker.dtb.misses 9704 # DTB misses -system.cpu.checker.dtb.accesses 44212017 # DTB accesses +system.cpu.checker.dtb.accesses 44212070 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -453,7 +455,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3170 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7995 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115776285 # ITB inst hits +system.cpu.checker.itb.inst_hits 115776459 # ITB inst hits system.cpu.checker.itb.inst_misses 4825 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -470,11 +472,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115781110 # ITB inst accesses -system.cpu.checker.itb.hits 115776285 # DTB hits +system.cpu.checker.itb.inst_accesses 115781284 # ITB inst accesses +system.cpu.checker.itb.hits 115776459 # DTB hits system.cpu.checker.itb.misses 4825 # DTB misses -system.cpu.checker.itb.accesses 115781110 # DTB accesses -system.cpu.checker.numCycles 139003519 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115781284 # DTB accesses +system.cpu.checker.numCycles 139003748 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -506,69 +508,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 71876 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71876 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29748 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22357 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19771 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52105 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 423.395068 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2574.283993 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50327 96.59% 96.59% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 71892 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71892 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29751 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22366 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19775 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52117 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 422.184700 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2564.754173 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50340 96.59% 96.59% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.12% 97.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.01% 98.72% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 526 1.01% 98.72% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::12288-16383 339 0.65% 99.37% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 221 0.42% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52105 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17499 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9158.153521 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8139.378931 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17316 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 52117 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17509 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11528.471072 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9159.485910 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8140.517404 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17326 98.95% 98.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17499 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131377054816 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.616890 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.493493 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131322424316 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 37436500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7011000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6169000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkCompletionTime::total 17509 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131356952816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.616906 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493482 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131302352316 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37456000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6990000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6140500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::8-9 1200000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131377054816 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6345 82.32% 82.32% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1363 17.68% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7708 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71876 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131356952816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6353 82.36% 82.36% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1361 17.64% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7714 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71892 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71876 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7708 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71892 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7714 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7708 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79584 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7714 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79606 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25445789 # DTB read hits -system.cpu.dtb.read_misses 61974 # DTB read misses -system.cpu.dtb.write_hits 19906281 # DTB write hits -system.cpu.dtb.write_misses 9902 # DTB write misses +system.cpu.dtb.read_hits 25445841 # DTB read hits +system.cpu.dtb.read_misses 61989 # DTB read misses +system.cpu.dtb.write_hits 19906354 # DTB write hits +system.cpu.dtb.write_misses 9903 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID @@ -578,12 +580,12 @@ system.cpu.dtb.align_faults 357 # Nu system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25507763 # DTB read accesses -system.cpu.dtb.write_accesses 19916183 # DTB write accesses +system.cpu.dtb.read_accesses 25507830 # DTB read accesses +system.cpu.dtb.write_accesses 19916257 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45352070 # DTB hits -system.cpu.dtb.misses 71876 # DTB misses -system.cpu.dtb.accesses 45423946 # DTB accesses +system.cpu.dtb.hits 45352195 # DTB hits +system.cpu.dtb.misses 71892 # DTB misses +system.cpu.dtb.accesses 45424087 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -613,18 +615,18 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11893 # Table walker walks requested -system.cpu.itb.walker.walksShort 11893 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walks 11896 # Table walker walks requested +system.cpu.itb.walker.walksShort 11896 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3936 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7739 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11672 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 618.017478 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2885.502200 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 11116 95.24% 95.24% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 98.24% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::samples 11675 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 618.158458 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2886.319815 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11119 95.24% 95.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 158 1.35% 96.59% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.61% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::20480-24575 33 0.28% 99.90% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency @@ -632,36 +634,36 @@ system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.9 system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11672 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3547 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12874.259938 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 8701.526273 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2599 73.27% 73.27% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.09% 98.36% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11675 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3548 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12874.295378 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10192.055773 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8701.296219 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.28% 73.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.08% 98.37% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::32768-49151 56 1.58% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3547 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 24002810416 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.962951 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.189029 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 889895500 3.71% 3.71% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 23112364416 96.29% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 3548 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23982708416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.963466 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.187762 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 876788500 3.66% 3.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 23105369416 96.34% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 24002810416 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3008 90.44% 90.44% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 318 9.56% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 23982708416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3008 90.41% 90.41% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 319 9.59% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3327 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11893 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11893 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11896 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11896 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15219 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66221269 # ITB inst hits -system.cpu.itb.inst_misses 11893 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3327 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3327 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15223 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66221900 # ITB inst hits +system.cpu.itb.inst_misses 11896 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -670,98 +672,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2209 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66233162 # ITB inst accesses -system.cpu.itb.hits 66221269 # DTB hits -system.cpu.itb.misses 11893 # DTB misses -system.cpu.itb.accesses 66233162 # DTB accesses -system.cpu.numCycles 278796094 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66233796 # ITB inst accesses +system.cpu.itb.hits 66221900 # DTB hits +system.cpu.itb.misses 11896 # DTB misses +system.cpu.itb.accesses 66233796 # DTB accesses +system.cpu.numCycles 278773245 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104750737 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184597310 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46857763 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33046380 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 161828011 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6150220 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 189816 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 10180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 357136 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 560173 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104752235 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184598573 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46858247 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33046816 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161804794 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6150362 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189820 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 10294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 357135 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 560172 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66221459 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1133676 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5180 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270771349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.831471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.217911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66222091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1133757 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5184 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270749817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.831543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.217938 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171553381 63.36% 63.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29224188 10.79% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14067085 5.20% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55926695 20.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171531140 63.35% 63.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29224382 10.79% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14067275 5.20% 79.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55927020 20.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270771349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168072 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.662123 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77850364 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 121893157 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64586539 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3844068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2597221 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3423151 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486287 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157328219 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3698916 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2597221 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83695488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11783440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76673328 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62587040 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33434832 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146701505 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 957116 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 452960 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63776 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16375 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30685156 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150380164 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678249075 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164321181 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 270749817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168087 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662182 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77852001 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121869294 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64587229 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3844010 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2597283 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486289 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157329382 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3698909 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2597283 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83697131 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11783559 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76650059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62587653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33434132 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146702491 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 957120 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 451934 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63799 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16325 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30684565 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150381225 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678253528 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164322158 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141709271 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8670890 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2840534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2644382 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13862021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26394587 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21292605 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1688978 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2214312 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143440731 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2121629 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143228275 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270765 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8407822 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14697300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125774 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270771349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.528964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.865543 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141709530 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8671692 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2840546 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644403 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13862058 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26394800 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21292698 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1688864 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2213691 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143441668 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121624 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143228772 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270823 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8408546 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14699465 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125775 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270749817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.529008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865566 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182535287 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45134238 16.67% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32022031 11.83% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10269230 3.79% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 810530 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182513589 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45134220 16.67% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32022113 11.83% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10269287 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 810575 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -769,43 +771,43 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270771349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270749817 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7336420 32.74% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5631672 25.13% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9443165 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7336339 32.73% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631595 25.13% 57.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9443725 42.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95929589 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95929894 66.98% 66.98% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 113798 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued @@ -834,94 +836,94 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26176168 18.28% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20997807 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26176243 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20997924 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143228275 # Type of FU issued -system.cpu.iq.rate 0.513738 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22411289 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156473 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579874368 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153975557 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140119306 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 143228772 # Type of FU issued +system.cpu.iq.rate 0.513782 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22411691 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579854290 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153977213 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140119725 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165613882 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 165614781 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 322775 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 322762 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1495918 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18543 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 704297 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1496089 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 504 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18542 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 704390 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87859 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6368 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2597221 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1240950 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 535645 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145763292 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2597283 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1242021 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 536402 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145764225 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26394587 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21292605 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17982 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 501480 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18543 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317940 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471176 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142285522 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25773547 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 870984 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26394800 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21292698 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096198 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 502218 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18542 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317968 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471203 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142285969 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25773594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 871017 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200932 # number of nop insts executed -system.cpu.iew.exec_refs 46642466 # number of memory reference insts executed -system.cpu.iew.exec_branches 26501161 # Number of branches executed -system.cpu.iew.exec_stores 20868919 # Number of stores executed -system.cpu.iew.exec_rate 0.510357 # Inst execution rate -system.cpu.iew.wb_sent 141899022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140130673 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63222272 # num instructions producing a value -system.cpu.iew.wb_consumers 95712658 # num instructions consuming a value -system.cpu.iew.wb_rate 0.502628 # insts written-back per cycle +system.cpu.iew.exec_nop 200933 # number of nop insts executed +system.cpu.iew.exec_refs 46642596 # number of memory reference insts executed +system.cpu.iew.exec_branches 26501312 # Number of branches executed +system.cpu.iew.exec_stores 20869002 # Number of stores executed +system.cpu.iew.exec_rate 0.510400 # Inst execution rate +system.cpu.iew.wb_sent 141899463 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140131092 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63222174 # num instructions producing a value +system.cpu.iew.wb_consumers 95712525 # num instructions consuming a value +system.cpu.iew.wb_rate 0.502671 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660542 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7606616 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995855 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755952 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267837215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.512660 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.117818 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7607261 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995849 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755996 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267815570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.512702 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.117847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194442706 72.60% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43232016 16.14% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15468771 5.78% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4394333 1.64% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6341721 2.37% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1685699 0.63% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 801066 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412117 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1058786 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194420599 72.59% 72.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43232205 16.14% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15469123 5.78% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4394347 1.64% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6341720 2.37% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1685703 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 801057 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412110 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1058706 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267837215 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113234248 # Number of instructions committed -system.cpu.commit.committedOps 137309439 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267815570 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113234401 # Number of instructions committed +system.cpu.commit.committedOps 137309647 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45486977 # Number of memory references committed -system.cpu.commit.loads 24898669 # Number of loads committed -system.cpu.commit.membars 814916 # Number of memory barriers committed -system.cpu.commit.branches 26015904 # Number of branches committed +system.cpu.commit.refs 45487019 # Number of memory references committed +system.cpu.commit.loads 24898711 # Number of loads committed +system.cpu.commit.membars 814912 # Number of memory barriers committed +system.cpu.commit.branches 26016004 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120139692 # Number of committed integer instructions. -system.cpu.commit.function_calls 4881505 # Number of function calls committed. +system.cpu.commit.int_insts 120139877 # Number of committed integer instructions. +system.cpu.commit.function_calls 4881537 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91701155 66.78% 66.78% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91701321 66.78% 66.78% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112732 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -950,36 +952,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24898669 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24898711 18.13% 85.01% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 20588308 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137309439 # Class of committed instruction -system.cpu.commit.bw_lim_events 1058786 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389537878 # The number of ROB reads -system.cpu.rob.rob_writes 292763814 # The number of ROB writes -system.cpu.timesIdled 892824 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8024745 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387029091 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113079343 # Number of Instructions Simulated -system.cpu.committedOps 137154534 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.465491 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.465491 # CPI: Total CPI of All Threads -system.cpu.ipc 0.405599 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.405599 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155725297 # number of integer regfile reads -system.cpu.int_regfile_writes 88564294 # number of integer regfile writes +system.cpu.commit.op_class_0::total 137309647 # Class of committed instruction +system.cpu.commit.bw_lim_events 1058706 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389516895 # The number of ROB reads +system.cpu.rob.rob_writes 292765635 # The number of ROB writes +system.cpu.timesIdled 892830 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8023428 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387011736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113079496 # Number of Instructions Simulated +system.cpu.committedOps 137154742 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.465286 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.465286 # CPI: Total CPI of All Threads +system.cpu.ipc 0.405633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.405633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155725818 # number of integer regfile reads +system.cpu.int_regfile_writes 88564533 # number of integer regfile writes system.cpu.fp_regfile_reads 9527 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502644824 # number of cc regfile reads -system.cpu.cc_regfile_writes 53156150 # number of cc regfile writes -system.cpu.misc_regfile_reads 348441241 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521640 # number of misc regfile writes +system.cpu.cc_regfile_reads 502646313 # number of cc regfile reads +system.cpu.cc_regfile_writes 53156218 # number of cc regfile writes +system.cpu.misc_regfile_reads 348169816 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521639 # number of misc regfile writes system.cpu.dcache.tags.replacements 837355 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40093226 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40093288 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 837867 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.851540 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.851614 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy @@ -989,120 +991,120 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179262562 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179262562 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23296906 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23296906 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15545467 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15545467 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345973 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345973 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441682 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441682 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 179262934 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179262934 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23297038 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23297038 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15545406 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15545406 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345967 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345967 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441679 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441679 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38842373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38842373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39188346 # number of overall hits -system.cpu.dcache.overall_hits::total 39188346 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 708692 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 708692 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3602140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3602140 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177879 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177879 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 27097 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 27097 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 38842444 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38842444 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39188411 # number of overall hits +system.cpu.dcache.overall_hits::total 39188411 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 708652 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 708652 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3602204 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3602204 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177882 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177882 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 27101 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 27101 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4310832 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4310832 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4488711 # number of overall misses -system.cpu.dcache.overall_misses::total 4488711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11726844500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11726844500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 232349107178 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373049000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 373049000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 244075951678 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 244075951678 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 244075951678 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 244075951678 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24005598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24005598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19147607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19147607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523852 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523852 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4310856 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4310856 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4488738 # number of overall misses +system.cpu.dcache.overall_misses::total 4488738 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11718587000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11718587000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 232348383185 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 232348383185 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373073000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 373073000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 302000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 302000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 244066970185 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 244066970185 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 244066970185 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 244066970185 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24005690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24005690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19147610 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19147610 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468780 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468780 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43153205 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43153205 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43677057 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43677057 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029522 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029522 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188125 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188125 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339560 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339560 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057803 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057803 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 43153300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43153300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43677149 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43677149 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029520 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029520 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188128 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188128 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339567 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339567 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057812 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.099896 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.099896 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102770 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102770 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56619.221458 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54375.510403 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 870696 # number of cycles access was blocked +system.cpu.dcache.overall_miss_rate::cpu.data 0.102771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16536.448073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16536.448073 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64501.728160 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64501.728160 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.023394 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.023394 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56616.822781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56616.822781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54373.182437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54373.182437 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 869617 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6851 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6831 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.090352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.304494 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695416 # number of writebacks -system.cpu.dcache.writebacks::total 695416 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295634 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 295634 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302552 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3302552 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18703 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18703 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3598186 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3598186 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3598186 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3598186 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 413058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299588 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299588 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119604 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119604 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 695423 # number of writebacks +system.cpu.dcache.writebacks::total 695423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295601 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295601 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3302610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18707 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18707 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3598211 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3598211 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3598211 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3598211 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 413051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299594 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299594 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119605 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119605 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8394 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8394 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 712646 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 712646 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 712645 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 712645 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 832250 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 832250 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable @@ -1111,32 +1113,32 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972155480 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972155480 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1700460500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1700460500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391361500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391361500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19958097481 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19958097481 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699868500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699868500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126799500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126799500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26364056480 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26364056480 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064516980 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28064516980 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075770951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075770951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098451 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098451 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017207 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017207 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015646 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015646 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228316 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228316 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 295000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 295000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26349458981 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26349458981 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28049327481 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28049327481 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276320000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276320000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075778951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075778951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017206 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017206 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015647 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015647 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228320 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228320 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses @@ -1145,34 +1147,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016514 system.cpu.dcache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019055 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.019055 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658 # average SoftPFReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15473.540798 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15473.540798 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66617.146809 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66617.146809 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14212.353162 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14212.353162 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15105.968549 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15105.968549 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329 # average overall mshr uncacheable latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36974.172247 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36974.172247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33703.006886 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33703.006886 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201622.923962 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.923962 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184005.037194 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184005.037194 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.691845 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.691845 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1886675 # number of replacements -system.cpu.icache.tags.tagsinuse 511.154168 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64239376 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1887187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34.039751 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1886695 # number of replacements +system.cpu.icache.tags.tagsinuse 511.154169 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64239998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1887207 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34.039720 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.154168 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.154169 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1181,76 +1183,76 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 197 system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68105664 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68105664 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64239376 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64239376 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64239376 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64239376 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64239376 # number of overall hits -system.cpu.icache.overall_hits::total 64239376 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1979079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1979079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1979079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1979079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1979079 # number of overall misses -system.cpu.icache.overall_misses::total 1979079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28144068491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28144068491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28144068491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28144068491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28144068491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28144068491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66218455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66218455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66218455 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66218455 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66218455 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66218455 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 68106315 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68106315 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64239998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64239998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64239998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64239998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64239998 # number of overall hits +system.cpu.icache.overall_hits::total 64239998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1979089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1979089 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1979089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1979089 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1979089 # number of overall misses +system.cpu.icache.overall_misses::total 1979089 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28142009491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28142009491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28142009491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28142009491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28142009491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28142009491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66219087 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66219087 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66219087 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66219087 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66219087 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66219087 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029887 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.029887 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.029887 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.029887 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.029887 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.029887 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14220.790828 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14220.790828 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14220.790828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14220.790828 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14220.790828 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5080 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14219.678595 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14219.678595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14219.678595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14219.678595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14219.678595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14219.678595 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4519 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 161 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.358025 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.068323 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1886675 # number of writebacks -system.cpu.icache.writebacks::total 1886675 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91868 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 91868 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 91868 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 91868 # number of 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accesses system.cpu.l2cache.demand_accesses::cpu.data 837890 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2791510 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54602 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1887169 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2791540 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54613 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11850 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1887187 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 837890 # number of overall (read+write) accesses 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ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010515 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010515 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.455926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010514 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010514 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024858 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024858 # miss rate for ReadSharedReq accesses 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129968.506961 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132359.389174 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132359.389174 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135243.455303 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135243.455303 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 146714.285714 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 130720.170707 # average overall miss latency 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of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits @@ -1474,22 +1476,22 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135393 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 135393 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13331 # 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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887205500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756953000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756953000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887198000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227315000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756961000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756961000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644158500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984275500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644159000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984276000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000436 # mshr miss rate for ReadReq accesses @@ -1536,108 +1538,108 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010501 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024645 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024645 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024649 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024649 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.060387 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060387 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.862918 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.862918 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119968.506961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119968.506961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122395.084881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122395.084881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125346.958674 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125346.958674 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.618780 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.650807 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.380823 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.380823 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.261743 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.242231 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5483387 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758318 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5483442 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758353 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 128004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2556278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 128030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556317 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 820384 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1846676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 142776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 820394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1886695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 149869 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 541178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541172 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627062 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8416504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239014016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323369 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47396 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 337603189 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 196948 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3052801 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.158805 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667118 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636221 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31264 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8463699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241576384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323817 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218452 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340166053 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 196965 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025894 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.158818 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2973766 97.41% 97.41% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 79035 2.59% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2973799 97.41% 97.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 79049 2.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3052801 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5399625997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5399685497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2834640846 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834668847 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1303359054 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1303356559 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19415986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19420986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74513896 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74535395 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution @@ -1689,7 +1691,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43090500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1727,21 +1729,21 @@ system.iobus.reqLayer23.occupancy 6193500 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 33084000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186380025 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187182974 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 1.005380 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.005274 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256605907000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005380 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062836 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062836 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256605904000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005274 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062830 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1757,14 +1759,14 @@ system.iocache.demand_misses::realview.ide 249 # system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31316876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31316876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717082149 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717082149 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31316876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31316876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31316876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31316876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31308877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31308877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4546803097 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4546803097 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31308877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31308877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31308877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31308877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1781,19 +1783,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125770.586345 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125770.586345 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125770.586345 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 902 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125738.461847 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125738.461847 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125619.646277 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125619.646277 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125738.461847 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125738.461847 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 96 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.395833 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1807,14 +1809,14 @@ system.iocache.demand_mshr_misses::realview.ide 249 system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18866876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18866876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907332149 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2907332149 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18866876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18866876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18866876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18866876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18858877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18858877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2735602611 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2735602611 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18858877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18858877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18858877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18858877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses @@ -1823,68 +1825,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75738.461847 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75738.461847 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75579.572068 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.572068 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34133 # Transaction distribution system.membus.trans_dist::ReadResp 67559 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124958 # Transaction distribution -system.membus.trans_dist::CleanEvict 7701 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124961 # Transaction distribution +system.membus.trans_dist::CleanEvict 7937 # Transaction distribution system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution -system.membus.trans_dist::ReadExReq 133521 # Transaction distribution -system.membus.trans_dist::ReadExResp 133521 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 133523 # Transaction distribution +system.membus.trans_dist::ReadExResp 133523 # Transaction distribution system.membus.trans_dist::ReadSharedReq 33427 # Transaction distribution system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 454663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562233 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450075 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630513 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16401756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565161 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402076 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18880361 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18880681 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 513 # Total snoops (count) -system.membus.snoop_fanout::samples 402363 # Request fanout histogram +system.membus.snoop_fanout::samples 402367 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402363 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402367 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402363 # Request fanout histogram -system.membus.reqLayer0.occupancy 83709500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402367 # Request fanout histogram +system.membus.reqLayer0.occupancy 83710000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1749000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1748000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 873720378 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 873736629 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 987389399 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 978197500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64116283 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 2941c59e8..17d61a09e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,162 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827515 # Number of seconds simulated -sim_ticks 2827514981500 # Number of ticks simulated -final_tick 2827514981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827476 # Number of seconds simulated +sim_ticks 2827475548000 # Number of ticks simulated +final_tick 2827475548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72486 # Simulator instruction rate (inst/s) -host_op_rate 87933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1706351372 # Simulator tick rate (ticks/s) -host_mem_usage 605296 # Number of bytes of host memory used -host_seconds 1657.05 # Real time elapsed on the host -sim_insts 120112531 # Number of instructions simulated -sim_ops 145708890 # Number of ops (including micro ops) simulated +host_inst_rate 107187 # Simulator instruction rate (inst/s) +host_op_rate 130034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2524753544 # Simulator tick rate (ticks/s) +host_mem_usage 623308 # Number of bytes of host memory used +host_seconds 1119.90 # Real time elapsed on the host +sim_insts 120039450 # Number of instructions simulated +sim_ops 145624845 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1298880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1333736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8603840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 183536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 661460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 448448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1281000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8477568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 174256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 561876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 361024 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12533612 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1298880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 183536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1482416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8896000 # Number of bytes written to this memory +system.physmem.bytes_read::total 12157612 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 174256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1472816 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8578432 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8913564 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22542 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10356 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 7007 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8595996 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20536 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 132462 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2791 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8800 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5641 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198694 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139000 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192819 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 134038 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143391 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 459372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 471699 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3042898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64911 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 233937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 158601 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 138429 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 91 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 459265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 453054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2998282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 61630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 127684 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4432731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 459372 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64911 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 524282 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3146226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4299812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 459265 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 61630 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520894 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3033954 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3152437 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3146226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 459372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 477897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3042898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 233951 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 158601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3040166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3033954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 91 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 459265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 459252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2998282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 61630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 198734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 127684 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7585168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198695 # Number of read requests accepted -system.physmem.writeReqs 143391 # Number of write requests accepted -system.physmem.readBursts 198695 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 143391 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12706944 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue -system.physmem.bytesWritten 8926464 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12533676 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8913564 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7339978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 192820 # Number of read requests accepted +system.physmem.writeReqs 138429 # Number of write requests accepted +system.physmem.readBursts 192820 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 138429 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12329536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10880 # Total number of bytes read from write queue +system.physmem.bytesWritten 8609152 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12157676 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8595996 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 170 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 66310 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12511 # Per bank write bursts -system.physmem.perBankRdBursts::1 12409 # Per bank write bursts -system.physmem.perBankRdBursts::2 13005 # Per bank write bursts -system.physmem.perBankRdBursts::3 12914 # Per bank write bursts -system.physmem.perBankRdBursts::4 14688 # Per bank write bursts -system.physmem.perBankRdBursts::5 12279 # Per bank write bursts -system.physmem.perBankRdBursts::6 12659 # Per bank write bursts -system.physmem.perBankRdBursts::7 12545 # Per bank write bursts -system.physmem.perBankRdBursts::8 12216 # Per bank write bursts -system.physmem.perBankRdBursts::9 11968 # Per bank write bursts -system.physmem.perBankRdBursts::10 11724 # Per bank write bursts -system.physmem.perBankRdBursts::11 10899 # Per bank write bursts -system.physmem.perBankRdBursts::12 12000 # Per bank write bursts -system.physmem.perBankRdBursts::13 12901 # Per bank write bursts -system.physmem.perBankRdBursts::14 12154 # Per bank write bursts -system.physmem.perBankRdBursts::15 11674 # Per bank write bursts -system.physmem.perBankWrBursts::0 9120 # Per bank write bursts -system.physmem.perBankWrBursts::1 9128 # Per bank write bursts -system.physmem.perBankWrBursts::2 9608 # Per bank write bursts -system.physmem.perBankWrBursts::3 9301 # Per bank write bursts -system.physmem.perBankWrBursts::4 8579 # Per bank write bursts -system.physmem.perBankWrBursts::5 8797 # Per bank write bursts -system.physmem.perBankWrBursts::6 8898 # Per bank write bursts -system.physmem.perBankWrBursts::7 8634 # Per bank write bursts -system.physmem.perBankWrBursts::8 8555 # Per bank write bursts -system.physmem.perBankWrBursts::9 8430 # Per bank write bursts -system.physmem.perBankWrBursts::10 8386 # Per bank write bursts -system.physmem.perBankWrBursts::11 7930 # Per bank write bursts -system.physmem.perBankWrBursts::12 8700 # Per bank write bursts -system.physmem.perBankWrBursts::13 8975 # Per bank write bursts -system.physmem.perBankWrBursts::14 8498 # Per bank write bursts -system.physmem.perBankWrBursts::15 7937 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11576 # Per bank write bursts +system.physmem.perBankRdBursts::1 11126 # Per bank write bursts +system.physmem.perBankRdBursts::2 12008 # Per bank write bursts +system.physmem.perBankRdBursts::3 12324 # Per bank write bursts +system.physmem.perBankRdBursts::4 14472 # Per bank write bursts +system.physmem.perBankRdBursts::5 12248 # Per bank write bursts +system.physmem.perBankRdBursts::6 12234 # Per bank write bursts +system.physmem.perBankRdBursts::7 12314 # Per bank write bursts +system.physmem.perBankRdBursts::8 11863 # Per bank write bursts +system.physmem.perBankRdBursts::9 12111 # Per bank write bursts +system.physmem.perBankRdBursts::10 11927 # Per bank write bursts +system.physmem.perBankRdBursts::11 10878 # Per bank write bursts +system.physmem.perBankRdBursts::12 11632 # Per bank write bursts +system.physmem.perBankRdBursts::13 12420 # Per bank write bursts +system.physmem.perBankRdBursts::14 12142 # Per bank write bursts +system.physmem.perBankRdBursts::15 11374 # Per bank write bursts +system.physmem.perBankWrBursts::0 8212 # Per bank write bursts +system.physmem.perBankWrBursts::1 8081 # Per bank write bursts +system.physmem.perBankWrBursts::2 8787 # Per bank write bursts +system.physmem.perBankWrBursts::3 8816 # Per bank write bursts +system.physmem.perBankWrBursts::4 8301 # Per bank write bursts +system.physmem.perBankWrBursts::5 8710 # Per bank write bursts +system.physmem.perBankWrBursts::6 8720 # Per bank write bursts +system.physmem.perBankWrBursts::7 8560 # Per bank write bursts +system.physmem.perBankWrBursts::8 8226 # Per bank write bursts +system.physmem.perBankWrBursts::9 8556 # Per bank write bursts +system.physmem.perBankWrBursts::10 8511 # Per bank write bursts +system.physmem.perBankWrBursts::11 8034 # Per bank write bursts +system.physmem.perBankWrBursts::12 8394 # Per bank write bursts +system.physmem.perBankWrBursts::13 8529 # Per bank write bursts +system.physmem.perBankWrBursts::14 8449 # Per bank write bursts +system.physmem.perBankWrBursts::15 7632 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2827514698000 # Total gap between requests +system.physmem.numWrRetry 14 # Number of times write queue was full causing retry +system.physmem.totGap 2827475264500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 195029 # Read request sizes (log2) +system.physmem.readPktSize::6 189154 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139000 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 75209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8590 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7482 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 246 # What read queue length does an incoming req see +system.physmem.writePktSize::6 134038 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 73950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 803 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see @@ -188,160 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91952 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.267792 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.235046 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 298.839280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50134 54.52% 54.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17916 19.48% 74.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5936 6.46% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3412 3.71% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2785 3.03% 87.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1606 1.75% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 997 1.08% 90.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 910 0.99% 91.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8256 8.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91952 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6854 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.967610 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.585770 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6852 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6854 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.349577 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.863128 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.733584 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5532 80.71% 80.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 528 7.70% 88.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 124 1.81% 90.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 151 2.20% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 37 0.54% 92.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 137 2.00% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.74% 95.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 13 0.19% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 30 0.44% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.25% 96.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.15% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.22% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.39% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.19% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6854 # Writes before turning the bus around for reads -system.physmem.totQLat 6593126991 # Total ticks spent queuing -system.physmem.totMemAccLat 10315864491 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 992730000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33207.05 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51957.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s +system.physmem.wrQLenPdf::60 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 86851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.087472 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 135.747966 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.663203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46826 53.92% 53.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16666 19.19% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5740 6.61% 79.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3326 3.83% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2736 3.15% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1522 1.75% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 967 1.11% 89.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 891 1.03% 90.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8177 9.41% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 86851 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6471 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.771133 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 578.111149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6469 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6471 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6471 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.787823 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.938766 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.675923 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5299 81.89% 81.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 491 7.59% 89.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 106 1.64% 91.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 48 0.74% 91.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 55 0.85% 92.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 30 0.46% 93.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 47 0.73% 93.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 20 0.31% 94.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 127 1.96% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.12% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.11% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.19% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 76 1.17% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.39% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 78 1.21% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.12% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.12% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6471 # Writes before turning the bus around for reads +system.physmem.totQLat 6248738813 # Total ticks spent queuing +system.physmem.totMemAccLat 9860907563 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 963245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 32435.71 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51185.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing -system.physmem.readRowHits 165438 # Number of row buffer hits during reads -system.physmem.writeRowHits 80631 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.80 # Row buffer hit rate for writes -system.physmem.avgGap 8265508.38 # Average gap between requests -system.physmem.pageHitRate 72.79 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 362418840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197748375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 803470200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466981200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80961093990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625490282750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892961490875 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.478934 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704041495487 # Time in different power states -system.physmem_0.memoryStateTime::REF 94416920000 # Time in different power states +system.physmem.avgWrQLen 25.73 # Average write queue length when enqueuing +system.physmem.readRowHits 160837 # Number of row buffer hits during reads +system.physmem.writeRowHits 79479 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.49 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.08 # Row buffer hit rate for writes +system.physmem.avgGap 8535800.15 # Average gap between requests +system.physmem.pageHitRate 73.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 333433800 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 181933125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 766755600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441851760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184676952720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80138844765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626188195250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892727967020 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.405562 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705208494482 # Time in different power states +system.physmem_0.memoryStateTime::REF 94415360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29056546513 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27851611768 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 332738280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181553625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 745180800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 436823280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80279403345 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626088257000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892743451850 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.401821 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705042490853 # Time in different power states -system.physmem_1.memoryStateTime::REF 94416920000 # Time in different power states +system.physmem_1.actEnergy 323159760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 176327250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 735906600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 429824880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184676952720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80034809220 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626279454500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892656434930 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.380263 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705361200169 # Time in different power states +system.physmem_1.memoryStateTime::REF 94415360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28055246647 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27698906081 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -367,15 +363,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53824650 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24914718 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1030270 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32581460 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 24224214 # Number of BTB hits +system.cpu0.branchPred.lookups 53905391 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24966840 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1032917 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32635895 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 24264793 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 74.349688 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15556762 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33886 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.350016 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15570273 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33772 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,81 +402,82 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 72482 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 72482 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26840 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21370 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24272 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 48210 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 483.737814 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3068.363590 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 46935 97.36% 97.36% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 960 1.99% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 127 0.26% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 144 0.30% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 24 0.05% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 72512 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 72512 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26965 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21131 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24416 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 48096 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 467.596058 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2968.857131 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 46825 97.36% 97.36% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 988 2.05% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 122 0.25% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 128 0.27% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 16 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 48210 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 19223 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 10866.878219 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9427.660612 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7974.318697 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 19122 99.47% 99.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 77 0.40% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 19223 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 87324939152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.584645 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.504578 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 87261759152 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 45052000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7883000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 5458000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1586500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 936000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1172500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1091000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walkWaitTime::total 48096 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 18855 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10765.367277 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9357.714559 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7448.182030 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 18771 99.55% 99.55% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 62 0.33% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.11% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 18855 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 82990542356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.627007 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.496515 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 82928307856 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 44597000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7454000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4958000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1796000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1081000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1137000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1210500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 87324939152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5998 77.94% 77.94% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1698 22.06% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7696 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72482 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::total 82990542356 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5809 78.88% 78.88% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1555 21.12% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7364 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72512 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72482 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7696 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72512 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7364 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7696 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 80178 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7364 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 79876 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24348850 # DTB read hits -system.cpu0.dtb.read_misses 61646 # DTB read misses -system.cpu0.dtb.write_hits 18136813 # DTB write hits -system.cpu0.dtb.write_misses 10836 # DTB write misses +system.cpu0.dtb.read_hits 24390364 # DTB read hits +system.cpu0.dtb.read_misses 61238 # DTB read misses +system.cpu0.dtb.write_hits 18168033 # DTB write hits +system.cpu0.dtb.write_misses 11274 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3858 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 293 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2461 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3796 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 307 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2501 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 958 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24410496 # DTB read accesses -system.cpu0.dtb.write_accesses 18147649 # DTB write accesses +system.cpu0.dtb.perms_faults 1008 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24451602 # DTB read accesses +system.cpu0.dtb.write_accesses 18179307 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42485663 # DTB hits -system.cpu0.dtb.misses 72482 # DTB misses -system.cpu0.dtb.accesses 42558145 # DTB accesses +system.cpu0.dtb.hits 42558397 # DTB hits +system.cpu0.dtb.misses 72512 # DTB misses +system.cpu0.dtb.accesses 42630909 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -510,56 +507,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 11063 # Table walker walks requested -system.cpu0.itb.walker.walksShort 11063 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4358 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6586 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 119 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10944 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 511.878655 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2393.914880 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 10440 95.39% 95.39% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 166 1.52% 96.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 245 2.24% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 55 0.50% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 14 0.13% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.13% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10944 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3006 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12466.400532 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11507.410615 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5482.679017 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2781 92.51% 92.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 206 6.85% 99.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.57% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 10837 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10837 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4138 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6571 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 128 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10709 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 537.118312 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2502.473477 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 10215 95.39% 95.39% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 152 1.42% 96.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 230 2.15% 98.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 65 0.61% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 22 0.21% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10709 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3004 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12684.087883 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11728.240532 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5609.984659 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2772 92.28% 92.28% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 204 6.79% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 24 0.80% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 3 0.10% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3006 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 18373803416 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.969102 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.173359 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 568612000 3.09% 3.09% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17804392916 96.90% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 690500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 108000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 18373803416 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2539 87.95% 87.95% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 348 12.05% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2887 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3004 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 18565989416 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.960744 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.194475 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 729735500 3.93% 3.93% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17835412416 96.06% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 771500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 18565989416 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2530 87.97% 87.97% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 346 12.03% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2876 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11063 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11063 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10837 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10837 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2887 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2887 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13950 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74042794 # ITB inst hits -system.cpu0.itb.inst_misses 11063 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13713 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74149475 # ITB inst hits +system.cpu0.itb.inst_misses 10837 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -568,145 +565,145 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2625 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2616 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74053857 # ITB inst accesses -system.cpu0.itb.hits 74042794 # DTB hits -system.cpu0.itb.misses 11063 # DTB misses -system.cpu0.itb.accesses 74053857 # DTB accesses -system.cpu0.numCycles 211047403 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74160312 # ITB inst accesses +system.cpu0.itb.hits 74149475 # DTB hits +system.cpu0.itb.misses 10837 # DTB misses +system.cpu0.itb.accesses 74160312 # DTB accesses +system.cpu0.numCycles 211083313 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21173136 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 200001666 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53824650 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39780976 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 180559136 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5880452 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 163694 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 71518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 416219 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 467581 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 105314 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 74043107 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 284080 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 205896824 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.187509 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.306152 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21223431 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 200300307 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53905391 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39835066 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 180535577 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5889142 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 161904 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 68557 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 388699 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 473615 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 104901 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 74149781 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 285289 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4990 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 205901255 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.189189 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.306256 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98736671 47.95% 47.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 31028549 15.07% 63.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14918972 7.25% 70.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 61212632 29.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98579580 47.88% 47.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 31081229 15.10% 62.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14947160 7.26% 70.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 61293286 29.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 205896824 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.255036 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.947662 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26444854 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 111284081 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 60438396 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 5147375 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2582118 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3181251 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 362597 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 158450982 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4186687 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2582118 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 35356822 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 13355442 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 85192856 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 56532551 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 12877035 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 141523079 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1131567 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1510730 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 170563 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 62525 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 8538727 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 145648252 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 652695637 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 157341344 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 11002 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 133402169 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12246080 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2729481 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2582524 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22941481 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 25362929 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19747073 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1756360 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2710793 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 138386443 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1765013 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 136262498 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 514521 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11554986 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23816746 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 127231 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 205896824 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.661800 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.962021 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 205901255 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.255375 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.948916 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26485725 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 111121300 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 60553458 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 5155672 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2585100 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3186918 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 364053 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 158727281 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4198172 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2585100 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 35410452 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13324080 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 85173312 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 56642777 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 12765534 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 141784227 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1134861 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1512506 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 171242 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 63990 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8419059 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 145923157 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 653859214 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 157615965 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 11018 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 133662052 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12261102 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2732054 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2584956 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22955704 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 25402528 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19781437 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1763657 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2641114 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 138643116 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1767872 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 136516412 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 515589 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11570507 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23858027 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 127265 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205901255 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.663019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.962571 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 127277158 61.82% 61.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 34398562 16.71% 78.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31970025 15.53% 94.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 11080468 5.38% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1170573 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 127147396 61.75% 61.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 34442708 16.73% 78.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 32032196 15.56% 94.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 11106549 5.39% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1172365 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 41 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 205896824 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205901255 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 11103787 43.69% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 71 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5926512 23.32% 67.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8382229 32.98% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 11130379 43.68% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 74 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.68% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5931854 23.28% 66.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8421894 33.05% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 91815128 67.38% 67.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 112435 0.08% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 91995657 67.39% 67.39% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 112676 0.08% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.47% # Type of FU issued @@ -728,650 +725,650 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.47% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8235 0.01% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 25085333 18.41% 85.88% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 19239052 14.12% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8005 0.01% 67.48% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.48% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.48% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.48% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 25126496 18.41% 85.88% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 19271262 14.12% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 136262498 # Type of FU issued -system.cpu0.iq.rate 0.645649 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 25412599 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.186497 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 504310819 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 151713950 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 132552939 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 38121 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 13270 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 11439 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 161648054 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 24728 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 380758 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 136516412 # Type of FU issued +system.cpu0.iq.rate 0.646742 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 25484201 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.186675 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 504896258 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 151989102 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 132800903 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 37611 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 13286 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 11444 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 161974001 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 24297 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 381848 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2120893 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2730 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20852 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1081680 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2124335 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2693 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20966 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1085688 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 121274 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 393141 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 122039 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 394742 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2582118 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1967503 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 225282 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 140361265 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2585100 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1946406 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 232120 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 140620014 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 25362929 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19747073 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 903285 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28583 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 172530 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20852 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 314241 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 420118 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 734359 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 135106830 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 24606381 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1083325 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 25402528 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19781437 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 904543 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28856 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 178897 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20966 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 314635 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 420768 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 735403 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 135358106 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 24646455 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1085945 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 209809 # number of nop insts executed -system.cpu0.iew.exec_refs 43646202 # number of memory reference insts executed -system.cpu0.iew.exec_branches 26044471 # Number of branches executed -system.cpu0.iew.exec_stores 19039821 # Number of stores executed -system.cpu0.iew.exec_rate 0.640173 # Inst execution rate -system.cpu0.iew.wb_sent 134503420 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 132564378 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 67577240 # num instructions producing a value -system.cpu0.iew.wb_consumers 109379746 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.628126 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.617822 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10448394 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1637782 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 672162 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202592939 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.635502 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.338703 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 209026 # number of nop insts executed +system.cpu0.iew.exec_refs 43717751 # number of memory reference insts executed +system.cpu0.iew.exec_branches 26098625 # Number of branches executed +system.cpu0.iew.exec_stores 19071296 # Number of stores executed +system.cpu0.iew.exec_rate 0.641254 # Inst execution rate +system.cpu0.iew.wb_sent 134752568 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 132812347 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 67711784 # num instructions producing a value +system.cpu0.iew.wb_consumers 109592899 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.629194 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.617848 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10460496 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1640607 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 673446 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202593421 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.636705 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.338464 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 141057849 69.63% 69.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33954375 16.76% 86.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12905235 6.37% 92.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3389250 1.67% 94.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4963565 2.45% 96.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2666475 1.32% 98.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1522321 0.75% 98.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 575799 0.28% 99.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1558070 0.77% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 140886474 69.54% 69.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 34073921 16.82% 86.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12920125 6.38% 92.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3397713 1.68% 94.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4982698 2.46% 96.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2731294 1.35% 98.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1467251 0.72% 98.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 577318 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1556627 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202592939 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 106280740 # Number of instructions committed -system.cpu0.commit.committedOps 128748309 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202593421 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 106498180 # Number of instructions committed +system.cpu0.commit.committedOps 128992320 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 41907429 # Number of memory references committed -system.cpu0.commit.loads 23242036 # Number of loads committed -system.cpu0.commit.membars 664627 # Number of memory barriers committed -system.cpu0.commit.branches 25370057 # Number of branches committed +system.cpu0.commit.refs 41973942 # Number of memory references committed +system.cpu0.commit.loads 23278193 # Number of loads committed +system.cpu0.commit.membars 666414 # Number of memory barriers committed +system.cpu0.commit.branches 25425121 # Number of branches committed system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 112383608 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4877012 # Number of function calls committed. +system.cpu0.commit.int_insts 112579800 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4882067 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 86722676 67.36% 67.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 109969 0.09% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8235 0.01% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 23242036 18.05% 85.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18665393 14.50% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 86900184 67.37% 67.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 110189 0.09% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8005 0.01% 67.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.46% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 23278193 18.05% 85.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18695749 14.49% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 128748309 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1558070 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 316922543 # The number of ROB reads -system.cpu0.rob.rob_writes 281696540 # The number of ROB writes -system.cpu0.timesIdled 138499 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5150579 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5443982755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 106128897 # Number of Instructions Simulated -system.cpu0.committedOps 128596466 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.988595 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.988595 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.502868 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.502868 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 146588252 # number of integer regfile reads -system.cpu0.int_regfile_writes 83723999 # number of integer regfile writes -system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu0.cc_regfile_reads 476941595 # number of cc regfile reads -system.cpu0.cc_regfile_writes 51071402 # number of cc regfile writes -system.cpu0.misc_regfile_reads 282603834 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1261450 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 749987 # number of replacements -system.cpu0.dcache.tags.tagsinuse 496.992457 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38690178 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 750499 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.552604 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 128992320 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1556627 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 317161742 # The number of ROB reads +system.cpu0.rob.rob_writes 282212626 # The number of ROB writes +system.cpu0.timesIdled 140171 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5182058 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5443868094 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 106346337 # Number of Instructions Simulated +system.cpu0.committedOps 128840477 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.984867 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.984867 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.503812 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.503812 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 146850094 # number of integer regfile reads +system.cpu0.int_regfile_writes 83860337 # number of integer regfile writes +system.cpu0.fp_regfile_reads 9519 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2721 # number of floating regfile writes +system.cpu0.cc_regfile_reads 477816426 # number of cc regfile reads +system.cpu0.cc_regfile_writes 51195786 # number of cc regfile writes +system.cpu0.misc_regfile_reads 282652550 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1263043 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 752117 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.742963 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38755611 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 752629 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.493646 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.992457 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970688 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.970688 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.742963 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.976060 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.976060 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83515372 # Number of tag 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-system.cpu0.dcache.demand_hits::total 37439875 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 37756578 # number of overall hits -system.cpu0.dcache.overall_hits::total 37756578 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 687176 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 687176 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1969830 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1969830 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153892 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 153892 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25692 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25692 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20263 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20263 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2657006 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2657006 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2810898 # number of overall misses -system.cpu0.dcache.overall_misses::total 2810898 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 10005125000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 10005125000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36953361360 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36953361360 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 414445500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 414445500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 533612500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 533612500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 572000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 572000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 46958486360 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 46958486360 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 46958486360 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 46958486360 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22741658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22741658 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17355223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17355223 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470595 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 470595 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 397630 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390495 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 390495 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 40096881 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40096881 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40567476 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40567476 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030217 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.030217 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.113501 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.327016 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.327016 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064613 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051891 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051891 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066265 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.066265 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069289 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069289 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14559.770714 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14559.770714 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18759.670307 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18759.670307 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16131.305465 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16131.305465 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26334.328579 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26334.328579 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83654415 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83654415 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22092656 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22092656 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15410060 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15410060 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316535 # number of SoftPFReq hits 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46494572372 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 46494572372 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46494572372 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46494572372 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22779894 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22779894 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17384432 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17384432 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470553 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 470553 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 398150 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 398150 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391008 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 391008 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 40164326 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40164326 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40634879 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40634879 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030169 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030169 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113571 # miss rate for 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StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17673.458908 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17673.458908 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16705.866367 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16705.866367 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5691402 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 46 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 211704 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.891304 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 26.883772 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17468.589452 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17468.589452 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16513.038076 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16513.038076 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1294 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5611564 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 45 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 212264 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 28.755556 # average number of cycles each access was blocked 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(read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1911401 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911401 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1911401 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 409916 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 409916 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335689 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 335689 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107270 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 107270 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6647 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6647 # number of 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-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60302 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60302 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149096500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149096500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7778892390 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7778892390 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1793614000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1793614000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 108165500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 108165500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 513361500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 513361500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 560000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 560000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12927988890 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12927988890 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14721602890 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14721602890 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623643500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623643500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395209000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395209000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12018852500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12018852500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018025 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018025 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019342 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227945 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227945 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016717 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051891 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051891 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018595 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018595 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021024 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.021024 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.345495 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.345495 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23172.914185 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23172.914185 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16720.555607 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16720.555607 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16272.829848 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16272.829848 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25334.920792 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25334.920792 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 752119 # number of writebacks +system.cpu0.dcache.writebacks::total 752119 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276058 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 276058 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1637615 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1637615 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19358 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19358 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1913673 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1913673 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1913673 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1913673 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 411180 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 411180 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 336757 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 336757 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107638 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 107638 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6783 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6783 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20265 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20265 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 747937 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 747937 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 855575 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 855575 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31813 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31813 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28497 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28497 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60310 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60310 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5148866500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5148866500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7661006402 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7661006402 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1794118000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1794118000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 109526500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109526500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 516121000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 516121000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 726000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 726000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12809872902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12809872902 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14603990902 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14603990902 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6624175500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6624175500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395535000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395535000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12019710500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12019710500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018050 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018050 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019371 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019371 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228748 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228748 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051828 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051828 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018622 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018622 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021055 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.021055 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12522.171555 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12522.171555 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22749.360524 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22749.360524 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16668.072614 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16668.072614 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16147.206251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.206251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25468.591167 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25468.591167 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17338.924618 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17338.924618 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17261.149512 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17261.149512 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208231.742589 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208231.742589 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189352.086477 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189352.086477 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199311.009585 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199311.009585 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17126.941042 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17126.941042 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17069.211819 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17069.211819 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208222.283343 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208222.283343 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189336.947749 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189336.947749 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199298.797878 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199298.797878 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1312325 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.728748 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 72670068 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1312837 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 55.353458 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8207375500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728748 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 1314552 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.728712 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 72774275 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1315064 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 55.338961 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8206989500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728712 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999470 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999470 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 134 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 149391678 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 149391678 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 72670068 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 72670068 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 72670068 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 72670068 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 72670068 # number of overall hits -system.cpu0.icache.overall_hits::total 72670068 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1369337 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1369337 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1369337 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1369337 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1369337 # number of overall misses -system.cpu0.icache.overall_misses::total 1369337 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942606327 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14942606327 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14942606327 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14942606327 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14942606327 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14942606327 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74039405 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 74039405 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74039405 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 74039405 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74039405 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 74039405 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018495 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.018495 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018495 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.018495 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018495 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.018495 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10912.292830 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10912.292830 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10912.292830 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10912.292830 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10912.292830 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10912.292830 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2029991 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 126413 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.058404 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 149607293 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 149607293 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 72774275 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 72774275 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 72774275 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 72774275 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 72774275 # number of overall hits +system.cpu0.icache.overall_hits::total 72774275 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1371825 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1371825 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1371825 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1371825 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1371825 # number of overall misses +system.cpu0.icache.overall_misses::total 1371825 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14990660882 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14990660882 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14990660882 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14990660882 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14990660882 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14990660882 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74146100 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 74146100 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74146100 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 74146100 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74146100 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 74146100 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018502 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018502 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018502 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018502 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018502 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018502 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10927.531487 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10927.531487 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10927.531487 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10927.531487 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10927.531487 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10927.531487 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2029638 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1805 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 126916 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.991979 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 112.812500 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1312325 # number of writebacks -system.cpu0.icache.writebacks::total 1312325 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56467 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 56467 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 56467 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 56467 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 56467 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 56467 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312870 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1312870 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1312870 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1312870 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1312870 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1312870 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1314552 # number of writebacks +system.cpu0.icache.writebacks::total 1314552 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56730 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 56730 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 56730 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 56730 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 56730 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 56730 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1315095 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1315095 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1315095 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1315095 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1315095 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1315095 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13422835685 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13422835685 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13422835685 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13422835685 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13422835685 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13422835685 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13463982231 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13463982231 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13463982231 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13463982231 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13463982231 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13463982231 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 420651998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 420651998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 420651998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 420651998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017732 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017732 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017732 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10224.040221 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017737 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017737 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017737 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017737 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017737 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017737 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10238.030128 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10238.030128 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10238.030128 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10238.030128 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10238.030128 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10238.030128 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1922264 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1925121 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2600 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1929258 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1932095 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2584 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 245295 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 283525 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16106.133558 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3424599 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 299662 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.428206 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 247841 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 284507 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16086.849244 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3431968 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 300678 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.414097 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14666.612197 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.987362 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.024801 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1424.509198 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.895179 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000854 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086945 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983040 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 969 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15162 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 307 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 430 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 205 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4568 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7930 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2049 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059143 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925415 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 69529329 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 69529329 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 59791 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14320 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 74111 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 505100 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 505100 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1523954 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1523954 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205881 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 205881 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1258248 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1258248 # number of ReadCleanReq hits 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of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 340 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 103 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 443 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55446 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55446 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20261 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20261 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 74580 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 74580 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 54597 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 54597 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97319 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 97319 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 340 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 103 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 54597 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 171899 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 226939 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 340 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 103 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 54597 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 171899 # number of overall misses -system.cpu0.l2cache.overall_misses::total 226939 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 12449000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2707500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 15156500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 180664000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 180664000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 42645500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 42645500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 540498 # 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-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178267462 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6369324000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6767444500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5178555462 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5178555462 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 398120500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547113462 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945233962 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.005929 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11547879462 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11945999962 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.005965 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999951 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999951 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148042 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148042 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041554 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184330 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184330 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171674 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088088 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005638 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.007141 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041554 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171674 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.151020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.151020 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042186 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184281 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184281 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172696 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.088851 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.005649 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.007305 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042186 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172696 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.206922 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28255.656109 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84762.290433 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26370.495617 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26370.495617 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17777.528207 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17777.528207 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 234249 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234249 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60278.082852 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60278.082852 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63253.262785 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28938.767033 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28938.767033 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45374.487804 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67994.717128 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.208598 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27309.593023 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25966.592428 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82410.767063 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82410.767063 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26130.289096 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26130.289096 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17910.809378 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17910.809378 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 152749.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 152749.250000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56739.632206 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56739.632206 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62641.722809 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28707.974399 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28707.974399 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27309.593023 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37246.367967 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44438.947365 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27309.593023 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21566.666667 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62641.722809 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37246.367967 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82410.767063 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66236.938536 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200221.509636 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194380.446959 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181738.232619 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181738.232619 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200211.360136 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194371.844214 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181722.829140 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181722.829140 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191488.067759 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188690.392096 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191475.368297 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188678.648672 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 4279317 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162325 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 327449 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 323077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 121937 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2006842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 739077 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1523954 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 209281 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 317808 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85654 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42585 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298662 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 295385 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312870 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595361 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3427 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3918545 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2723305 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31953 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129711 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6803514 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166426752 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103211806 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57692 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 240524 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 269936774 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1020233 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3250109 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.119815 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.328862 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 4287266 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2165878 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33429 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 330817 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 325927 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4890 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 121349 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2010442 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28497 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28497 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 741210 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1560498 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 209521 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 320891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86097 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42565 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113963 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298891 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 295589 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1315095 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595916 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3396 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3950726 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2739036 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31654 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130125 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6851541 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 168343936 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103984190 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57496 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 243592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 272629214 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1021824 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3257313 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.120341 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.329941 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2865068 88.15% 88.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 380669 11.71% 99.87% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4372 0.13% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2870216 88.12% 88.12% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 382207 11.73% 99.85% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4890 0.15% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3250109 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4279335949 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3257313 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4288108443 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113715191 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113808525 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1972888832 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1976208867 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1291542228 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1295252494 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 17537485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 17289481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 69622914 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 69274405 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4034173 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2335207 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 244345 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2038897 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1508183 # Number of BTB hits +system.cpu1.branchPred.lookups 3960492 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2278371 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 239603 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1992874 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1474633 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.970534 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 793679 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5620 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.995295 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 786361 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 6053 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1631,88 +1628,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 15746 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 15746 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8388 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3065 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4293 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 11453 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 595.826421 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3233.762475 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 10927 95.41% 95.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 176 1.54% 96.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 209 1.82% 98.77% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.31% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 3 0.03% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 42 0.37% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 20 0.17% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 11453 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 3271 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11706.970345 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10400.215389 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7344.366479 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 2791 85.33% 85.33% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 443 13.54% 98.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 31 0.95% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 3271 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 78450006060 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.184600 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.390418 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 63997466940 81.58% 81.58% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 14437247120 18.40% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 10341500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 2133500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 875500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 457000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 962000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 87500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 30500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 79000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walks 15222 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 15222 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 7935 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3046 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4241 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 10981 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 629.359803 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3543.870184 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-8191 10629 96.79% 96.79% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-16383 248 2.26% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-24575 28 0.25% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-32767 51 0.46% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-40959 21 0.19% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-90111 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::90112-98303 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 10981 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11717.562048 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10260.840497 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8597.667676 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2739 86.05% 86.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 395 12.41% 98.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 36 1.13% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-98303 1 0.03% 99.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-114687 6 0.19% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 2 0.06% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 78410323560 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.145148 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.354804 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 67057915756 85.52% 85.52% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 11337246804 14.46% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 10462000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 1830000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 951000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 350500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 990500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 120500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 94000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 139000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::10 14000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 54000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 17000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 17500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 175000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 78450006060 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1233 71.11% 71.11% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 501 28.89% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1734 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15746 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::11 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 12000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 153000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 78410323560 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1233 73.13% 73.13% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 453 26.87% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1686 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15222 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15746 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1734 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15222 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1686 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1734 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 17480 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1686 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 16908 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3564995 # DTB read hits -system.cpu1.dtb.read_misses 13832 # DTB read misses -system.cpu1.dtb.write_hits 3032176 # DTB write hits -system.cpu1.dtb.write_misses 1914 # DTB write misses +system.cpu1.dtb.read_hits 3499603 # DTB read hits +system.cpu1.dtb.read_misses 13349 # DTB read misses +system.cpu1.dtb.write_hits 2989645 # DTB write hits +system.cpu1.dtb.write_misses 1873 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 34 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1646 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 45 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 267 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3578827 # DTB read accesses -system.cpu1.dtb.write_accesses 3034090 # DTB write accesses +system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3512952 # DTB read accesses +system.cpu1.dtb.write_accesses 2991518 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6597171 # DTB hits -system.cpu1.dtb.misses 15746 # DTB misses -system.cpu1.dtb.accesses 6612917 # DTB accesses +system.cpu1.dtb.hits 6489248 # DTB hits +system.cpu1.dtb.misses 15222 # DTB misses +system.cpu1.dtb.accesses 6504470 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1742,55 +1739,56 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6257 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6257 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3920 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2276 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 61 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6196 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 206.181407 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1542.947362 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 6076 98.06% 98.06% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 60 0.97% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 39 0.63% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.11% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.08% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6196 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 896 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11471.540179 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10591.082273 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5713.555798 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 197 21.99% 21.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 72.54% 94.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 13 1.45% 95.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 24 2.68% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.56% 99.22% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.22% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.45% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 896 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 13992892620 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.945402 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.227238 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 764122764 5.46% 5.46% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 13228629356 94.54% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 140500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 13992892620 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 692 82.87% 82.87% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 143 17.13% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 835 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6092 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6092 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3792 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2256 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 44 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6048 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 194.031085 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1498.555311 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5941 98.23% 98.23% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 54 0.89% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.58% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.12% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 3 0.05% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6048 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 878 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11682.801822 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10808.720287 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5784.559551 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 174 19.82% 19.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 74.03% 93.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 15 1.71% 95.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 28 3.19% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.57% 99.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.34% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.11% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::73728-81919 1 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 878 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 13953243120 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.946198 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.225667 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 750840264 5.38% 5.38% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 13202275856 94.62% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 127000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 13953243120 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 691 82.85% 82.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 143 17.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 834 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6257 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6257 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6092 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6092 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 835 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 835 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7092 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 7247489 # ITB inst hits -system.cpu1.itb.inst_misses 6257 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 834 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 834 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6926 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 7131526 # ITB inst hits +system.cpu1.itb.inst_misses 6092 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1799,1015 +1797,1026 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 899 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 898 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 342 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 335 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7253746 # ITB inst accesses -system.cpu1.itb.hits 7247489 # DTB hits -system.cpu1.itb.misses 6257 # DTB misses -system.cpu1.itb.accesses 7253746 # DTB accesses -system.cpu1.numCycles 32825676 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7137618 # ITB inst accesses +system.cpu1.itb.hits 7131526 # DTB hits +system.cpu1.itb.misses 6092 # DTB misses +system.cpu1.itb.accesses 7137618 # DTB accesses +system.cpu1.numCycles 32153663 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8001289 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 21471337 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4034173 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2301862 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 23036367 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 699414 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 85773 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 29291 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 185520 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 275269 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 17468 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7247139 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 103562 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 31980684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.819942 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.194084 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7900141 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 21121078 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3960492 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2260994 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 22525520 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 690384 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 85873 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 36828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 183368 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 268596 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 16764 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7131220 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 101425 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2175 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 31362282 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.823323 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.195698 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 19847655 62.06% 62.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4393311 13.74% 75.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1390148 4.35% 80.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 6349570 19.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 19419839 61.92% 61.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4322960 13.78% 75.70% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1360110 4.34% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 6259373 19.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31980684 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.122897 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.654102 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6559156 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16660335 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 7594258 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 935690 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 231245 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 620374 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 121000 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 20120105 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 926045 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 231245 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7803762 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2337008 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11658570 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7267589 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2682510 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 19097640 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 153089 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 210195 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 28229 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 13307 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1810658 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 18872486 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 89304984 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 22006430 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 31362282 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.123174 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.656879 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6476013 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16288433 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 7449358 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 919688 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 228790 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 612596 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 118905 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 19752784 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 909327 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 228790 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7703782 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2255288 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11537440 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7124756 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2512226 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 18734047 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 149896 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 201471 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 27483 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 12915 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1654980 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 18476585 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 87682069 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 21592076 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 16903103 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1969383 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 373801 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 306197 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2490350 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3798024 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3334408 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 558239 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 459403 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 18396455 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 514218 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 18243143 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80370 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1798248 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4138161 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 41963 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31980684 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.570443 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.921832 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 16547143 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1929442 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 373208 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 305811 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2461191 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3733224 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3288117 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 552829 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 458093 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 18036557 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 513632 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 17896075 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81001 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1765820 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4051574 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 42199 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 31362282 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.570624 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.921463 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21156406 66.15% 66.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5430198 16.98% 83.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3595564 11.24% 94.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1572256 4.92% 99.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 226251 0.71% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 20726941 66.09% 66.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5363186 17.10% 83.19% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3506961 11.18% 94.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1541817 4.92% 99.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 223369 0.71% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31980684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 31362282 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1148262 27.95% 27.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 668 0.02% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.97% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1340987 32.64% 60.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1618003 39.39% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1114950 27.66% 27.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 668 0.02% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1322557 32.82% 60.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1592153 39.50% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 11255159 61.70% 61.70% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 26433 0.14% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3176 0.02% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3744432 20.53% 82.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3213919 17.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 11018686 61.57% 61.57% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 25379 0.14% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.71% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3144 0.02% 61.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.73% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3679682 20.56% 82.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3169160 17.71% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 18243143 # Type of FU issued -system.cpu1.iq.rate 0.555758 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4107920 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.225176 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 72655260 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 20717149 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 17851675 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 17896075 # Type of FU issued +system.cpu1.iq.rate 0.556580 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4030328 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.225207 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 71265761 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 20324002 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 17511405 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 22351039 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 21926379 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 72767 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 71343 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 344909 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 550 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 8264 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 279088 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 337548 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 8028 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 276059 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 35940 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 54533 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 35249 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 51219 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 231245 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 541574 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 157299 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 18927437 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 228790 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 526676 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 150264 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18566765 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3798024 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3334408 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 272337 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6587 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 145035 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 8264 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 30633 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 103644 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 134277 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 18042171 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3670535 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 185229 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 3733224 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3288117 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 271755 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6489 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 137973 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 8028 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 29675 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 101337 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 131012 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 17697567 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3606675 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 183289 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 16764 # number of nop insts executed -system.cpu1.iew.exec_refs 6830795 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2603132 # Number of branches executed -system.cpu1.iew.exec_stores 3160260 # Number of stores executed -system.cpu1.iew.exec_rate 0.549636 # Inst execution rate -system.cpu1.iew.wb_sent 17938795 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 17851675 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 8886835 # num instructions producing a value -system.cpu1.iew.wb_consumers 13789507 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.543833 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.644464 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1628624 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 472255 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 125883 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31615084 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.541371 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.295044 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 16576 # number of nop insts executed +system.cpu1.iew.exec_refs 6722071 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2541515 # Number of branches executed +system.cpu1.iew.exec_stores 3115396 # Number of stores executed +system.cpu1.iew.exec_rate 0.550406 # Inst execution rate +system.cpu1.iew.wb_sent 17598968 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 17511405 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 8692607 # num instructions producing a value +system.cpu1.iew.wb_consumers 13471004 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.544616 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.645283 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1597357 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 471433 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 123201 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31002866 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.541480 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.295585 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23337715 73.82% 73.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 4942860 15.63% 89.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1433345 4.53% 93.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 542164 1.71% 95.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 455708 1.44% 97.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 302171 0.96% 98.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 181914 0.58% 98.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 99381 0.31% 98.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 319826 1.01% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 22873291 73.78% 73.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 4864873 15.69% 89.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1409236 4.55% 94.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 529319 1.71% 95.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 438451 1.41% 97.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 294402 0.95% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 179192 0.58% 98.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 97652 0.31% 98.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 316450 1.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31615084 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 13986698 # Number of instructions committed -system.cpu1.commit.committedOps 17115488 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31002866 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13696177 # Number of instructions committed +system.cpu1.commit.committedOps 16787432 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 6508435 # Number of memory references committed -system.cpu1.commit.loads 3453115 # Number of loads committed -system.cpu1.commit.membars 191139 # Number of memory barriers committed -system.cpu1.commit.branches 2479082 # Number of branches committed +system.cpu1.commit.refs 6407734 # Number of memory references committed +system.cpu1.commit.loads 3395676 # Number of loads committed +system.cpu1.commit.membars 190902 # Number of memory barriers committed +system.cpu1.commit.branches 2419020 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 15267561 # Number of committed integer instructions. -system.cpu1.commit.function_calls 414980 # Number of function calls committed. +system.cpu1.commit.int_insts 14992163 # Number of committed integer instructions. +system.cpu1.commit.function_calls 410100 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 10578262 61.81% 61.81% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 25615 0.15% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3176 0.02% 61.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.97% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.97% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3453115 20.18% 82.15% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3055320 17.85% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 10351952 61.66% 61.66% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 24602 0.15% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3144 0.02% 61.83% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.83% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.83% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.83% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3395676 20.23% 82.06% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3012058 17.94% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 17115488 # Class of committed instruction -system.cpu1.commit.bw_lim_events 319826 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 49145756 # The number of ROB reads -system.cpu1.rob.rob_writes 37850174 # The number of ROB writes -system.cpu1.timesIdled 55034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 844992 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5621633430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 13983634 # Number of Instructions Simulated -system.cpu1.committedOps 17112424 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.347435 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.347435 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.425997 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.425997 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20215691 # number of integer regfile reads -system.cpu1.int_regfile_writes 11658166 # number of integer regfile writes -system.cpu1.cc_regfile_reads 64782198 # number of cc regfile reads -system.cpu1.cc_regfile_writes 5550427 # number of cc regfile writes -system.cpu1.misc_regfile_reads 46731168 # number of misc regfile reads -system.cpu1.misc_regfile_writes 350339 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 150744 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.669505 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5845075 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 151083 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.687840 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104824569000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.669505 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921230 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.921230 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 328 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12896760 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12896760 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3092594 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3092594 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2524465 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2524465 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42426 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42426 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70168 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70168 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61430 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61430 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5617059 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5617059 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5659485 # number of overall hits -system.cpu1.dcache.overall_hits::total 5659485 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 178952 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 178952 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 316827 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 316827 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23604 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 23604 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17348 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17348 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23299 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23299 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 495779 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 495779 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 519383 # number of overall misses -system.cpu1.dcache.overall_misses::total 519383 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3441746500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3441746500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11862734947 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 11862734947 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362002500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 362002500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 631001500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 631001500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1169000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1169000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15304481447 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15304481447 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15304481447 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15304481447 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3271546 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3271546 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2841292 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2841292 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66030 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66030 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87516 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87516 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84729 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84729 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6112838 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6112838 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6178868 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6178868 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054700 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.054700 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111508 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.111508 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.357474 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.357474 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.198227 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.198227 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274983 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274983 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081105 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.081105 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084058 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.084058 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19232.791475 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19232.791475 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37442.310621 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37442.310621 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20867.102836 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20867.102836 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27082.771793 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27082.771793 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 16787432 # Class of committed instruction +system.cpu1.commit.bw_lim_events 316450 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 48173976 # The number of ROB reads +system.cpu1.rob.rob_writes 37125010 # The number of ROB writes +system.cpu1.timesIdled 52987 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 791381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5622225995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13693113 # Number of Instructions Simulated +system.cpu1.committedOps 16784368 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.348163 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.348163 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.425865 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.425865 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 19830637 # number of integer regfile reads +system.cpu1.int_regfile_writes 11457060 # number of integer regfile writes +system.cpu1.cc_regfile_reads 63567667 # number of cc regfile reads +system.cpu1.cc_regfile_writes 5386626 # number of cc regfile writes +system.cpu1.misc_regfile_reads 46959699 # number of misc regfile reads +system.cpu1.misc_regfile_writes 351107 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 146387 # number of replacements +system.cpu1.dcache.tags.tagsinuse 464.874328 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5757831 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 146736 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.239389 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 89642414500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.874328 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907958 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.907958 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.681641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12687956 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12687956 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3034292 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3034292 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2492465 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2492465 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42455 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42455 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70401 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70401 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61757 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61757 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5526757 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5526757 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5569212 # number of overall hits +system.cpu1.dcache.overall_hits::total 5569212 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 176347 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 176347 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 307156 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 307156 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23291 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 23291 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17298 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17298 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23328 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23328 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 483503 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 483503 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 506794 # number of overall misses +system.cpu1.dcache.overall_misses::total 506794 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3277543500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3277543500 # number of ReadReq miss cycles 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demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 14087291945 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 14087291945 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3210639 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3210639 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2799621 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2799621 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65746 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 65746 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87699 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87699 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85085 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 85085 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6010260 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6010260 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6076006 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6076006 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054926 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.054926 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.109713 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.109713 # miss rate for WriteReq accesses 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18585.762729 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18585.762729 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35193.023887 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 35193.023887 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20611.602497 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20611.602497 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27100.951646 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27100.951646 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30869.563751 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30869.563751 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29466.658414 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29466.658414 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1808008 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 30216 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.548387 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 59.836113 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29135.893562 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29135.893562 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27796.879886 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 27796.879886 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1608332 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 29276 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.735294 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 54.936877 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 150744 # number of writebacks -system.cpu1.dcache.writebacks::total 150744 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62223 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 62223 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 237836 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 237836 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12586 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12586 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 300059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 300059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 300059 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 300059 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116729 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116729 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 78991 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22881 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 22881 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4762 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4762 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23299 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23299 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 195720 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 195720 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 218601 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 218601 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3069 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3069 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5480 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5480 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1778715000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1778715000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2939877456 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2939877456 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 425185000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 425185000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98534500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98534500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 607713500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 607713500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1158000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1158000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4718592456 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4718592456 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5143777456 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5143777456 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 437774500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 437774500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301405500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301405500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 739180000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 739180000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035680 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035680 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027801 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346524 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346524 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054413 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054413 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274983 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274983 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035379 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035379 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15237.987133 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15237.987133 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37217.878695 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 37217.878695 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18582.448320 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18582.448320 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 20691.831163 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 20691.831163 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26083.243916 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26083.243916 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 146387 # number of writebacks +system.cpu1.dcache.writebacks::total 146387 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 61765 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 61765 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 230665 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 230665 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12462 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12462 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 292430 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 292430 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 292430 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 292430 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 114582 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 114582 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 76491 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 76491 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22561 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 22561 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4836 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4836 # number of LoadLockedReq MSHR misses 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+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6128 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6128 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1708391000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1708391000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2716718455 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2716718455 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 399807500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 399807500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95324000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95324000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 608894000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 608894000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1051000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1051000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4425109455 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4425109455 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4824916955 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4824916955 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 456207000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 456207000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 319373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 319373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 775580000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 775580000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035688 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035688 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027322 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027322 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.343154 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.343154 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055143 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055143 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274173 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274173 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031791 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031791 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035160 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035160 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14909.767677 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14909.767677 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35516.837994 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35516.837994 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17721.178139 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17721.178139 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19711.331679 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19711.331679 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26101.423182 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26101.423182 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24108.892581 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24108.892581 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23530.438818 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23530.438818 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142644.020854 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142644.020854 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125012.650353 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125012.650353 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134886.861314 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134886.861314 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23159.260885 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23159.260885 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22584.967538 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22584.967538 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134455.349248 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 134455.349248 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 116772.577697 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 116772.577697 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 126563.315927 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 126563.315927 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 551908 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.384443 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6675021 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 552420 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.083236 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79408503500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.384443 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975360 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975360 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 545035 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.387406 # Cycle average of tags in use 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-system.cpu1.icache.demand_misses::total 571924 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 571924 # number of overall misses -system.cpu1.icache.overall_misses::total 571924 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5247903529 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5247903529 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5247903529 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5247903529 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5247903529 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5247903529 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7246945 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7246945 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7246945 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7246945 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7246945 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7246945 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078919 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.078919 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078919 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.078919 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078919 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.078919 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9175.875692 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9175.875692 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9175.875692 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9175.875692 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9175.875692 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9175.875692 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 518390 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 40965 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.654461 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 146 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 14807594 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14807594 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6566366 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6566366 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6566366 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6566366 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6566366 # number of overall hits +system.cpu1.icache.overall_hits::total 6566366 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 564657 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 564657 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 564657 # number of demand (read+write) misses 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accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7131023 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7131023 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7131023 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7131023 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.079183 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.079183 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.079183 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.079183 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.079183 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.079183 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9104.405088 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9104.405088 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9104.405088 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9104.405088 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9104.405088 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9104.405088 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 492404 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 97 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 39695 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.404686 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 97 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 551908 # number of writebacks -system.cpu1.icache.writebacks::total 551908 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19497 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 19497 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 19497 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 19497 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 19497 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 19497 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 552427 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 552427 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 552427 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 552427 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 552427 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 552427 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 545035 # number of writebacks +system.cpu1.icache.writebacks::total 545035 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19109 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 19109 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 19109 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 19109 # number of demand (read+write) MSHR hits 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uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 103 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4796273338 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4796273338 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4796273338 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4796273338 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4796273338 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4796273338 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076229 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.076229 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.076229 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8682.184864 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4699860850 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4699860850 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4699860850 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4699860850 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4699860850 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4699860850 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13703500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13703500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13703500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 13703500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076503 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076503 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076503 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.076503 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076503 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.076503 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8614.935533 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8614.935533 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8614.935533 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8614.935533 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133043.689320 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133043.689320 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133043.689320 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133043.689320 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 114901 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 115599 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 633 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 104122 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 104721 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 542 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 47913 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 38341 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15301.887572 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1226523 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53480 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 22.934237 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 47159 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 31230 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15089.646508 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1211194 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 46334 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 26.140502 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14854.525753 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 7.568708 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.883063 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 435.910048 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.906648 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000462 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000237 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026606 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.933953 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 923 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14155 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14617.935135 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.988168 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.811204 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 457.912000 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.892208 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000610 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000233 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027949 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.920999 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 989 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14057 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 616 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 296 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 639 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 339 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 33 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 802 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2695 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10658 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056335 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.863953 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 24288275 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 24288275 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 12056 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6824 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 18880 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 92484 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 92484 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 598066 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 598066 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16973 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 16973 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 541415 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 541415 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 78226 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 78226 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 12056 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6824 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 541415 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 95199 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 655494 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 12056 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6824 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 541415 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 95199 # number of overall hits -system.cpu1.l2cache.overall_hits::total 655494 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 455 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 292 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 747 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29477 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29477 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23299 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23299 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33181 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 33181 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 11002 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 11002 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66142 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 66142 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 455 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 292 # number of demand (read+write) misses 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-system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63278000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 63278000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 61670500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 61670500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1141500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1141500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1906360500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1906360500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658538999 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658538999 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1560865998 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1560865998 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10030500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5845500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658538999 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3467226498 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4141641497 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10030500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5845500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658538999 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3467226498 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4141641497 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 12511 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7116 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 19627 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 92484 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 92484 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 598066 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 598066 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29477 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29477 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23299 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23299 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50154 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 50154 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 552417 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 552417 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 144368 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 144368 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 12511 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7116 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 552417 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 194522 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 766566 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 12511 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7116 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 552417 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 194522 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 766566 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036368 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041034 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.038060 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 795 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2682 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 10580 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.060364 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.857971 # 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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504174 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.143235 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.036288 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038645 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019907 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504174 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638748 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638748 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018424 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018424 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.453456 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.453456 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035570 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.039554 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018424 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500557 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140454 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035570 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.039554 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018424 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500557 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170899 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15459.533608 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63486.677450 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20368.388913 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20368.388913 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18552.813425 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18552.813425 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50389.116561 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50389.116561 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53873.419933 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17578.962863 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17578.962863 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30752.074217 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36050.879577 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134577.712610 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134414.880202 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117410.408959 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117410.408959 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127024.725547 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127071.555794 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.165478 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15285.310734 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56508.442098 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56508.442098 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20261.416638 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20261.416638 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18573.137272 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18573.137272 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 484250 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 484250 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46945.824841 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46945.824841 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54545.169535 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16810.473866 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16810.473866 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26585.614107 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29160.141220 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16048.723898 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14097.472924 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54545.169535 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26585.614107 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56508.442098 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33295.843646 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125543.689320 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126367.079281 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 126342.820366 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109185.007678 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 109185.007678 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125543.689320 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 118698.514360 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 118811.666827 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1510050 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 763127 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12108 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 172945 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 171137 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1808 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 26162 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 760461 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 125070 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 598066 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 92914 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 26023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70036 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41455 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85358 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57012 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 54811 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 552427 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220569 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 25 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1646728 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729194 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15588 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27029 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2418539 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70023728 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24695290 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28464 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50044 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94797526 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 371473 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1121639 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.173444 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.382865 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1486808 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 750931 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12198 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 171006 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 168745 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2261 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 25827 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 751423 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2735 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2735 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 116660 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 601248 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 88861 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 22992 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70535 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41533 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84868 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 55768 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 52923 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 545548 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220317 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 68 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1636337 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718931 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15307 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 26144 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2396719 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 69798960 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24301530 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28012 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 48468 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94176970 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 362810 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1100696 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.175235 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.385533 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 928905 82.82% 82.82% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 190926 17.02% 99.84% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1808 0.16% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 910077 82.68% 82.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 188358 17.11% 99.79% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2261 0.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1121639 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1469339490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1100696 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1446777487 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79587436 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80382983 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 828867751 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 818547754 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 323642126 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 317524641 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8481980 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8315477 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 14527980 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 14039475 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31018 # Transaction distribution system.iobus.trans_dist::ReadResp 31018 # Transaction distribution @@ -2859,59 +2868,59 @@ system.iobus.pkt_size_system.bridge.master::total 162812 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40431500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40401000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 111000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 91000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 591500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 49500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6146000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6158500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34110000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34127000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186335542 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187100472 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.549511 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.549835 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256320229000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.549511 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909344 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909344 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256259438000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.549835 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909365 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909365 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2925,14 +2934,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32965876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32965876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4737835666 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4737835666 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32965876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32965876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32965876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32965876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32651377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32651377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4576002095 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4576002095 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32651377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32651377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32651377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32651377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2949,19 +2958,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130816.968254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130816.968254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130792.724879 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130792.724879 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130816.968254 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130816.968254 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 713 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129568.956349 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129568.956349 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126325.146174 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126325.146174 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129568.956349 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129568.956349 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129568.956349 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129568.956349 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.835165 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2975,14 +2984,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20365876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20365876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2926635666 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2926635666 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20365876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20365876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20365876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20365876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20051377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20051377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763118347 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2763118347 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20051377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20051377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20051377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20051377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2991,602 +3000,576 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80816.968254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80816.968254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80792.724879 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80792.724879 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79568.956349 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79568.956349 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76278.664615 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76278.664615 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79568.956349 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79568.956349 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79568.956349 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79568.956349 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 131293 # number of replacements -system.l2c.tags.tagsinuse 63152.978828 # Cycle average of tags in use -system.l2c.tags.total_refs 442353 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195350 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.264413 # Average number of references to valid blocks. +system.l2c.tags.replacements 124416 # number of replacements +system.l2c.tags.tagsinuse 63285.129344 # Cycle average of tags in use +system.l2c.tags.total_refs 440296 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 188523 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.335503 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13838.997413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.349981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.060621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8045.868087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2735.320064 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33659.346102 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.413836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909660 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1799.024775 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 856.706825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2190.981465 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.211166 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.122770 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513601 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.027451 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013072 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.963638 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30319 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33712 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6038 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24164 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 13134.904875 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.362165 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.695219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8133.848343 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2874.315443 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35508.928641 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.483607 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1685.782920 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 491.980320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1432.827811 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.200423 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.124113 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043859 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.541823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.007507 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.021863 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.965654 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30961 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33119 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 318 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6018 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24625 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 622 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4436 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28625 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.462631 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000397 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.514404 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6100734 # Number of tag accesses -system.l2c.tags.data_accesses 6100734 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 264718 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 264718 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32582 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2383 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34965 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2172 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 943 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3115 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4024 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1119 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5143 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 183 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 74 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 34982 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 48772 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46702 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 30 # number of ReadSharedReq hits +system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 608 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4362 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28117 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.472427 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.505356 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6003066 # Number of tag accesses +system.l2c.tags.data_accesses 6003066 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 259699 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 259699 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32958 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1822 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34780 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2116 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 991 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3107 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4295 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1377 # number of ReadExReq hits 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+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.670271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.551829 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72719.810739 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72275.160600 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72633.698267 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74616.820093 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73782.352941 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74117.549507 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141707.033668 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123533.082993 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 134161.568729 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127444.444444 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 120250 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 122982.989050 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129170.252729 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147024.159517 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124264.084074 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131234.619958 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166779.352420 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 143513.738800 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127444.444444 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 120250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122982.989050 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136024.569746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147024.159517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124264.084074 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124358.811177 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166779.352420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 142581.511945 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127444.444444 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 120250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122982.989050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136024.569746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147024.159517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124264.084074 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124358.811177 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166779.352420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 142581.511945 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182221.195259 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116692.922374 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171386.248749 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164734.444881 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100401.287433 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159715.442726 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182210.213089 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107533.980583 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108463.275516 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 170176.664396 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164718.620872 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 92178.247166 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158366.228388 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173958.617260 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109521.271499 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 166150.430305 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173945.283502 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107533.980583 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 101191.511837 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 164872.480774 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 37982 # Transaction distribution -system.membus.trans_dist::ReadResp 212889 # Transaction distribution -system.membus.trans_dist::WriteReq 30904 # Transaction distribution -system.membus.trans_dist::WriteResp 30904 # Transaction distribution -system.membus.trans_dist::WritebackDirty 139000 # Transaction distribution -system.membus.trans_dist::CleanEvict 16061 # Transaction distribution -system.membus.trans_dist::UpgradeReq 72768 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40424 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14027 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40474 # Transaction distribution -system.membus.trans_dist::ReadExResp 20691 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174908 # Transaction distribution +system.membus.trans_dist::ReadReq 38310 # Transaction distribution +system.membus.trans_dist::ReadResp 209204 # Transaction distribution +system.membus.trans_dist::WriteReq 31232 # Transaction distribution +system.membus.trans_dist::WriteResp 31232 # Transaction distribution +system.membus.trans_dist::WritebackDirty 134038 # Transaction distribution +system.membus.trans_dist::CleanEvict 15311 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73680 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40459 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 38317 # Transaction distribution +system.membus.trans_dist::ReadExResp 18829 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 170895 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672318 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 793976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 902910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14998 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 641245 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 764215 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 837164 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19129032 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19319536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29996 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18435464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18628592 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21637680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 119522 # Total snoops (count) -system.membus.snoop_fanout::samples 588990 # Request fanout histogram +system.membus.pkt_size::total 20946736 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 119950 # Total snoops (count) +system.membus.snoop_fanout::samples 578486 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 588990 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 578486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 588990 # Request fanout histogram -system.membus.reqLayer0.occupancy 81993500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 578486 # Request fanout histogram +system.membus.reqLayer0.occupancy 82005000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11365991 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12415490 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1011151356 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 979073321 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1153249220 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1095686984 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64060493 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1343381 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3629,56 +3612,56 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 995943 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 537996 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 143832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21510 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20627 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 883 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 37985 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 476927 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 403719 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 92623 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107653 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43539 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 151192 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50791 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50791 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 438958 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 986513 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 532898 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 144750 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20257 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19380 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 877 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 38313 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 474331 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31232 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31232 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 393751 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 116065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 108396 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43566 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 151962 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 26 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 49800 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 49800 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 436034 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1238290 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1508314 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35030546 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4521886 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39552432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 444179 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 913848 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.335282 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474132 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1264986 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256361 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1521347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35072434 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3807934 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38880368 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 439648 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 904500 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.339928 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.475727 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 608334 66.57% 66.57% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 304631 33.33% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 883 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 597912 66.10% 66.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 305711 33.80% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 877 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 913848 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 880459353 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 904500 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 870687772 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 356618 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 654259891 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 657373534 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 211427270 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 203531555 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2705 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index aa70a7365..dcac35547 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.832913 # Number of seconds simulated -sim_ticks 2832912592000 # Number of ticks simulated -final_tick 2832912592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.832892 # Number of seconds simulated +sim_ticks 2832892490000 # Number of ticks simulated +final_tick 2832892490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98871 # Simulator instruction rate (inst/s) -host_op_rate 119922 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2476970660 # Simulator tick rate (ticks/s) -host_mem_usage 585504 # Number of bytes of host memory used -host_seconds 1143.70 # Real time elapsed on the host -sim_insts 113079343 # Number of instructions simulated -sim_ops 137154534 # Number of ops (including micro ops) simulated +host_inst_rate 124603 # Simulator instruction rate (inst/s) +host_op_rate 151132 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3121592879 # Simulator tick rate (ticks/s) +host_mem_usage 587312 # Number of bytes of host memory used +host_seconds 907.52 # Real time elapsed on the host +sim_insts 113079496 # Number of instructions simulated +sim_ops 137154742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1316096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9383208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1315968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9383464 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10702120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1316096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1316096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7997312 # Number of bytes written to this memory +system.physmem.bytes_read::total 10702248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1315968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1315968 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7997504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8014836 # Number of bytes written to this memory +system.physmem.bytes_written::total 8015028 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 147133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22809 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 147137 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169988 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124958 # Number of write requests responded to by this memory +system.physmem.num_reads::total 169990 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124961 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129339 # Number of write requests responded to by this memory +system.physmem.num_writes::total 129342 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 474 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 464573 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3312212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 464532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3312326 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3777780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464573 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2823000 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3777852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464532 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2823088 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2829186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2823000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2829274 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2823088 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 474 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3318398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3318512 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 339 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6606966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169989 # Number of read requests accepted -system.physmem.writeReqs 129339 # Number of write requests accepted -system.physmem.readBursts 169989 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129339 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10867584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue -system.physmem.bytesWritten 8027584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10702184 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8014836 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6607125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 169991 # Number of read requests accepted +system.physmem.writeReqs 129342 # Number of write requests accepted +system.physmem.readBursts 169991 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129342 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10867968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue +system.physmem.bytesWritten 8027328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10702312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8015028 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 48490 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 11395 # Per bank write bursts -system.physmem.perBankRdBursts::1 10615 # Per bank write bursts +system.physmem.perBankRdBursts::1 10614 # Per bank write bursts system.physmem.perBankRdBursts::2 11052 # Per bank write bursts system.physmem.perBankRdBursts::3 11362 # Per bank write bursts system.physmem.perBankRdBursts::4 12761 # Per bank write bursts system.physmem.perBankRdBursts::5 10093 # Per bank write bursts -system.physmem.perBankRdBursts::6 10904 # Per bank write bursts -system.physmem.perBankRdBursts::7 11084 # Per bank write bursts -system.physmem.perBankRdBursts::8 10554 # Per bank write bursts -system.physmem.perBankRdBursts::9 10523 # Per bank write bursts -system.physmem.perBankRdBursts::10 10030 # Per bank write bursts +system.physmem.perBankRdBursts::6 10908 # Per bank write bursts +system.physmem.perBankRdBursts::7 11081 # Per bank write bursts +system.physmem.perBankRdBursts::8 10555 # Per bank write bursts +system.physmem.perBankRdBursts::9 10526 # Per bank write bursts +system.physmem.perBankRdBursts::10 10031 # Per bank write bursts system.physmem.perBankRdBursts::11 8841 # Per bank write bursts -system.physmem.perBankRdBursts::12 9967 # Per bank write bursts -system.physmem.perBankRdBursts::13 10661 # Per bank write bursts -system.physmem.perBankRdBursts::14 9878 # Per bank write bursts +system.physmem.perBankRdBursts::12 9969 # Per bank write bursts +system.physmem.perBankRdBursts::13 10658 # Per bank write bursts +system.physmem.perBankRdBursts::14 9880 # Per bank write bursts system.physmem.perBankRdBursts::15 10086 # Per bank write bursts system.physmem.perBankWrBursts::0 8599 # Per bank write bursts system.physmem.perBankWrBursts::1 7964 # Per bank write bursts @@ -85,37 +85,37 @@ system.physmem.perBankWrBursts::2 8486 # Pe system.physmem.perBankWrBursts::3 8679 # Per bank write bursts system.physmem.perBankWrBursts::4 7544 # Per bank write bursts system.physmem.perBankWrBursts::5 7468 # Per bank write bursts -system.physmem.perBankWrBursts::6 8077 # Per bank write bursts -system.physmem.perBankWrBursts::7 8182 # Per bank write bursts -system.physmem.perBankWrBursts::8 8055 # Per bank write bursts -system.physmem.perBankWrBursts::9 7911 # Per bank write bursts -system.physmem.perBankWrBursts::10 7496 # Per bank write bursts +system.physmem.perBankWrBursts::6 8076 # Per bank write bursts +system.physmem.perBankWrBursts::7 8179 # Per bank write bursts +system.physmem.perBankWrBursts::8 8056 # Per bank write bursts +system.physmem.perBankWrBursts::9 7908 # Per bank write bursts +system.physmem.perBankWrBursts::10 7497 # Per bank write bursts system.physmem.perBankWrBursts::11 6568 # Per bank write bursts system.physmem.perBankWrBursts::12 7556 # Per bank write bursts -system.physmem.perBankWrBursts::13 8042 # Per bank write bursts -system.physmem.perBankWrBursts::14 7357 # Per bank write bursts +system.physmem.perBankWrBursts::13 8041 # Per bank write bursts +system.physmem.perBankWrBursts::14 7359 # Per bank write bursts system.physmem.perBankWrBursts::15 7447 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2832912360000 # Total gap between requests +system.physmem.totGap 2832892258000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 2996 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166437 # Read request sizes (log2) +system.physmem.readPktSize::6 166439 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124958 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 150468 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124961 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150475 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 16446 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 723 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,113 +159,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.283685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.850271 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.574400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23280 37.49% 37.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14997 24.15% 61.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6479 10.43% 72.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3584 5.77% 77.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2530 4.07% 81.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1603 2.58% 84.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1574 2.53% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1048 1.69% 88.72% # Bytes accessed per row activation +system.physmem.wrQLenPdf::15 1893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 33 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 304.427918 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.985587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.629395 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23230 37.43% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15016 24.19% 61.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6492 10.46% 72.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3585 5.78% 77.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2536 4.09% 81.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1572 2.53% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1564 2.52% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1071 1.73% 88.72% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7002 11.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62097 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.116097 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.155612 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6261 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 62068 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.640729 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.576579 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6142 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6262 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.030501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.464444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.039261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5446 86.97% 86.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 116 1.85% 88.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 36 0.57% 89.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 167 2.67% 92.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.35% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 138 2.20% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 54 0.86% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 12 0.19% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.30% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.26% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.10% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.05% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 160 2.56% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.10% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.14% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.40% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.21% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6262 # Writes before turning the bus around for reads -system.physmem.totQLat 2134847750 # Total ticks spent queuing -system.physmem.totMemAccLat 5318710250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12572.28 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6143 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.417874 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.493305 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.002502 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5451 88.74% 88.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 111 1.81% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 0.55% 91.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.72% 91.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 0.54% 92.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.24% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 54 0.88% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 11 0.18% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 132 2.15% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.28% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.18% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 78 1.27% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 21 0.34% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 92 1.50% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6143 # Writes before turning the bus around for reads +system.physmem.totQLat 2131723500 # Total ticks spent queuing +system.physmem.totMemAccLat 5315698500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12553.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31322.28 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31303.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.83 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.78 # Average system read bandwidth in MiByte/s @@ -276,39 +278,39 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing -system.physmem.readRowHits 139313 # Number of row buffer hits during reads -system.physmem.writeRowHits 93826 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.79 # Row buffer hit rate for writes -system.physmem.avgGap 9464241.10 # Average gap between requests -system.physmem.pageHitRate 78.96 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247680720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135143250 # Energy for precharge commands per rank (pJ) +system.physmem.readRowHits 139329 # Number of row buffer hits during reads +system.physmem.writeRowHits 93841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.80 # Row buffer hit rate for writes +system.physmem.avgGap 9464015.86 # Average gap between requests +system.physmem.pageHitRate 78.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 247484160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135036000 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 696267000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 421193520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83693103705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1626331305750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1896556621545 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.472831 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2705407276500 # Time in different power states -system.physmem_0.memoryStateTime::REF 94597100000 # Time in different power states +system.physmem_0.writeEnergy 421167600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83639897910 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626363962250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1896534216840 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.470442 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705464523500 # Time in different power states +system.physmem_0.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32908202000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32831633000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 221772600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121006875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 628212000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 221749920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 120994500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 628258800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 391599360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185031927600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 81799663455 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1627992218250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1896186400140 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.342145 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2708183660500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94597100000 # Time in different power states +system.physmem_1.refreshEnergy 185030401920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 81914804595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1627877202000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1896185011095 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.347174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2707992537250 # Time in different power states +system.physmem_1.memoryStateTime::REF 94596320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30129768250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30298312750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -328,15 +330,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46857763 # Number of BP lookups -system.cpu.branchPred.condPredicted 24018162 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233841 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29502900 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21322687 # Number of BTB hits +system.cpu.branchPred.lookups 46858247 # Number of BP lookups +system.cpu.branchPred.condPredicted 24018458 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233894 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29504756 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21322919 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.273190 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11723693 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33902 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.269430 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11723897 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33908 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -367,69 +369,69 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 71876 # Table walker walks requested -system.cpu.dtb.walker.walksShort 71876 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29748 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22357 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 19771 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52105 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 423.395068 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2574.283993 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50327 96.59% 96.59% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 71892 # Table walker walks requested +system.cpu.dtb.walker.walksShort 71892 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29751 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22366 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 19775 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52117 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 422.184700 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2564.754173 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50340 96.59% 96.59% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::4096-8191 585 1.12% 97.71% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 525 1.01% 98.72% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 526 1.01% 98.72% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::12288-16383 339 0.65% 99.37% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::16384-20479 52 0.10% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 221 0.42% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 220 0.42% 99.89% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.92% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::28672-32767 10 0.02% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 8 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52105 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17499 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11526.115778 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9158.153521 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8139.378931 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 17316 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 52117 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17509 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11528.471072 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9159.485910 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8140.517404 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 17326 98.95% 98.95% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::32768-65535 177 1.01% 99.97% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 5 0.03% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17499 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 131377054816 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.616890 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.493493 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 131322424316 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 37436500 0.03% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7011000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6169000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walkCompletionTime::total 17509 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 131356952816 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.616906 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.493482 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 131302352316 99.96% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37456000 0.03% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 6990000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6140500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::8-9 1200000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::10-11 643000 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::12-13 1366500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::14-15 794500 0.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 131377054816 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6345 82.32% 82.32% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1363 17.68% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7708 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71876 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::total 131356952816 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6353 82.36% 82.36% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1361 17.64% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7714 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 71892 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71876 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7708 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 71892 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7714 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7708 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 79584 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7714 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 79606 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25445789 # DTB read hits -system.cpu.dtb.read_misses 61974 # DTB read misses -system.cpu.dtb.write_hits 19906281 # DTB write hits -system.cpu.dtb.write_misses 9902 # DTB write misses +system.cpu.dtb.read_hits 25445841 # DTB read hits +system.cpu.dtb.read_misses 61989 # DTB read misses +system.cpu.dtb.write_hits 19906354 # DTB write hits +system.cpu.dtb.write_misses 9903 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID @@ -439,12 +441,12 @@ system.cpu.dtb.align_faults 357 # Nu system.cpu.dtb.prefetch_faults 2185 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25507763 # DTB read accesses -system.cpu.dtb.write_accesses 19916183 # DTB write accesses +system.cpu.dtb.read_accesses 25507830 # DTB read accesses +system.cpu.dtb.write_accesses 19916257 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45352070 # DTB hits -system.cpu.dtb.misses 71876 # DTB misses -system.cpu.dtb.accesses 45423946 # DTB accesses +system.cpu.dtb.hits 45352195 # DTB hits +system.cpu.dtb.misses 71892 # DTB misses +system.cpu.dtb.accesses 45424087 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -474,18 +476,18 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11893 # Table walker walks requested -system.cpu.itb.walker.walksShort 11893 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3935 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7737 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walks 11896 # Table walker walks requested +system.cpu.itb.walker.walksShort 11896 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3936 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7739 # Level at which table walker walks with short descriptors terminate system.cpu.itb.walker.walksSquashedBefore 221 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11672 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 618.017478 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2885.502200 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-4095 11116 95.24% 95.24% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::4096-8191 159 1.36% 96.60% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-12287 192 1.64% 98.24% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::samples 11675 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 618.158458 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2886.319815 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-4095 11119 95.24% 95.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::4096-8191 158 1.35% 96.59% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-12287 193 1.65% 98.24% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::12288-16383 62 0.53% 98.78% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::16384-20479 98 0.84% 99.61% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::20480-24575 33 0.28% 99.90% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.91% # Table walker wait (enqueue to first request) latency @@ -493,36 +495,36 @@ system.cpu.itb.walker.walkWaitTime::28672-32767 7 0.06% 99.9 system.cpu.itb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-61439 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11672 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3547 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12874.259938 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10191.545390 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 8701.526273 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2599 73.27% 73.27% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.09% 98.36% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11675 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3548 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12874.295378 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10192.055773 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 8701.296219 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2600 73.28% 73.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 890 25.08% 98.37% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::32768-49151 56 1.58% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3547 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 24002810416 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.962951 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.189029 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 889895500 3.71% 3.71% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 23112364416 96.29% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 3548 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23982708416 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.963466 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.187762 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 876788500 3.66% 3.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 23105369416 96.34% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::2 493000 0.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::3 57500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 24002810416 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3008 90.44% 90.44% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 318 9.56% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3326 # Table walker page sizes translated +system.cpu.itb.walker.walksPending::total 23982708416 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3008 90.41% 90.41% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 319 9.59% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3327 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11893 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11893 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11896 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11896 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3326 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15219 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66221269 # ITB inst hits -system.cpu.itb.inst_misses 11893 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3327 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3327 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15223 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66221900 # ITB inst hits +system.cpu.itb.inst_misses 11896 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -531,98 +533,98 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2209 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2205 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66233162 # ITB inst accesses -system.cpu.itb.hits 66221269 # DTB hits -system.cpu.itb.misses 11893 # DTB misses -system.cpu.itb.accesses 66233162 # DTB accesses -system.cpu.numCycles 278796094 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66233796 # ITB inst accesses +system.cpu.itb.hits 66221900 # DTB hits +system.cpu.itb.misses 11896 # DTB misses +system.cpu.itb.accesses 66233796 # DTB accesses +system.cpu.numCycles 278773245 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104750737 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184597310 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46857763 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33046380 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 161828011 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6150220 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 189816 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 10180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 357136 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 560173 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.icacheStallCycles 104752235 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184598573 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46858247 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33046816 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 161804794 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6150362 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 189820 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 10294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 357135 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 560172 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66221459 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1133676 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5180 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 270771349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.831471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.217911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 66222091 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1133757 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5184 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 270749817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.831543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.217938 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 171553381 63.36% 63.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29224188 10.79% 74.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14067085 5.20% 79.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55926695 20.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 171531140 63.35% 63.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29224382 10.79% 74.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14067275 5.20% 79.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55927020 20.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 270771349 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.168072 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.662123 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 77850364 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 121893157 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64586539 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3844068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2597221 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3423151 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486287 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157328219 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3698916 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2597221 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83695488 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11783440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 76673328 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62587040 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 33434832 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146701505 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 957116 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 452960 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 63776 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16375 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 30685156 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150380164 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678249075 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164321181 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 270749817 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.168087 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.662182 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77852001 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 121869294 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64587229 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3844010 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2597283 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3423147 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486289 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157329382 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3698909 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2597283 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83697131 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11783559 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 76650059 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62587653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 33434132 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146702491 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 957120 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 451934 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 63799 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 16325 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 30684565 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150381225 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678253528 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164322158 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10889 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141709271 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8670890 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2840534 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2644382 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13862021 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26394587 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21292605 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1688978 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2214312 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143440731 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2121629 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143228275 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 270765 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8407822 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14697300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125774 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 270771349 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.528964 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.865543 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 141709530 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8671692 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2840546 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2644403 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13862058 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26394800 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21292698 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1688864 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2213691 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143441668 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2121624 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143228772 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 270823 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8408546 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14699465 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125775 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 270749817 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.529008 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.865566 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 182535287 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45134238 16.67% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32022031 11.83% 95.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10269230 3.79% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 810530 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 182513589 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45134220 16.67% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32022113 11.83% 95.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10269287 3.79% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 810575 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -630,43 +632,43 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 270771349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 270749817 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7336420 32.74% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5631672 25.13% 57.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9443165 42.14% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7336339 32.73% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 32 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5631595 25.13% 57.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9443725 42.14% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 95929589 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95929894 66.98% 66.98% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 113798 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued @@ -695,94 +697,94 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8576 0.01% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26176168 18.28% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 20997807 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26176243 18.28% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 20997924 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143228275 # Type of FU issued -system.cpu.iq.rate 0.513738 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22411289 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.156473 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 579874368 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 153975557 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140119306 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 143228772 # Type of FU issued +system.cpu.iq.rate 0.513782 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22411691 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156475 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 579854290 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 153977213 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140119725 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35585 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13122 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11367 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165613882 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 165614781 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23345 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 322775 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 322762 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1495918 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18543 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 704297 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1496089 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 504 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18542 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 704390 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87804 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87859 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6368 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2597221 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1240950 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 535645 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145763292 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2597283 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1242021 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 536402 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145764225 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26394587 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21292605 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096200 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17982 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 501480 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18543 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317940 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471176 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142285522 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25773547 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 870984 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26394800 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21292698 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1096198 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17994 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 502218 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18542 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317968 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471203 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789171 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142285969 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25773594 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 871017 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200932 # number of nop insts executed -system.cpu.iew.exec_refs 46642466 # number of memory reference insts executed -system.cpu.iew.exec_branches 26501161 # Number of branches executed -system.cpu.iew.exec_stores 20868919 # Number of stores executed -system.cpu.iew.exec_rate 0.510357 # Inst execution rate -system.cpu.iew.wb_sent 141899022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140130673 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63222272 # num instructions producing a value -system.cpu.iew.wb_consumers 95712658 # num instructions consuming a value -system.cpu.iew.wb_rate 0.502628 # insts written-back per cycle +system.cpu.iew.exec_nop 200933 # number of nop insts executed +system.cpu.iew.exec_refs 46642596 # number of memory reference insts executed +system.cpu.iew.exec_branches 26501312 # Number of branches executed +system.cpu.iew.exec_stores 20869002 # Number of stores executed +system.cpu.iew.exec_rate 0.510400 # Inst execution rate +system.cpu.iew.wb_sent 141899463 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140131092 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63222174 # num instructions producing a value +system.cpu.iew.wb_consumers 95712525 # num instructions consuming a value +system.cpu.iew.wb_rate 0.502671 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660542 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 7606616 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995855 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755952 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 267837215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.512660 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.117818 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7607261 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1995849 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755996 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 267815570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.512702 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.117847 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 194442706 72.60% 72.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43232016 16.14% 88.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15468771 5.78% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4394333 1.64% 96.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6341721 2.37% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1685699 0.63% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 801066 0.30% 99.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 412117 0.15% 99.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1058786 0.40% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 194420599 72.59% 72.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43232205 16.14% 88.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15469123 5.78% 94.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4394347 1.64% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6341720 2.37% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1685703 0.63% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 801057 0.30% 99.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 412110 0.15% 99.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1058706 0.40% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 267837215 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113234248 # Number of instructions committed -system.cpu.commit.committedOps 137309439 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 267815570 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113234401 # Number of instructions committed +system.cpu.commit.committedOps 137309647 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45486977 # Number of memory references committed -system.cpu.commit.loads 24898669 # Number of loads committed -system.cpu.commit.membars 814916 # Number of memory barriers committed -system.cpu.commit.branches 26015904 # Number of branches committed +system.cpu.commit.refs 45487019 # Number of memory references committed +system.cpu.commit.loads 24898711 # Number of loads committed +system.cpu.commit.membars 814912 # Number of memory barriers committed +system.cpu.commit.branches 26016004 # Number of branches committed system.cpu.commit.fp_insts 11364 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120139692 # Number of committed integer instructions. -system.cpu.commit.function_calls 4881505 # Number of function calls committed. +system.cpu.commit.int_insts 120139877 # Number of committed integer instructions. +system.cpu.commit.function_calls 4881537 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91701155 66.78% 66.78% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91701321 66.78% 66.78% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 112732 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction @@ -811,36 +813,36 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8575 0.01% 66.87% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24898669 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24898711 18.13% 85.01% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 20588308 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137309439 # Class of committed instruction -system.cpu.commit.bw_lim_events 1058786 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 389537878 # The number of ROB reads -system.cpu.rob.rob_writes 292763814 # The number of ROB writes -system.cpu.timesIdled 892824 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8024745 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5387029091 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113079343 # Number of Instructions Simulated -system.cpu.committedOps 137154534 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.465491 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.465491 # CPI: Total CPI of All Threads -system.cpu.ipc 0.405599 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.405599 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155725297 # number of integer regfile reads -system.cpu.int_regfile_writes 88564293 # number of integer regfile writes +system.cpu.commit.op_class_0::total 137309647 # Class of committed instruction +system.cpu.commit.bw_lim_events 1058706 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 389516895 # The number of ROB reads +system.cpu.rob.rob_writes 292765635 # The number of ROB writes +system.cpu.timesIdled 892830 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8023428 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5387011736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113079496 # Number of Instructions Simulated +system.cpu.committedOps 137154742 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.465286 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.465286 # CPI: Total CPI of All Threads +system.cpu.ipc 0.405633 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.405633 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155725818 # number of integer regfile reads +system.cpu.int_regfile_writes 88564532 # number of integer regfile writes system.cpu.fp_regfile_reads 9527 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502644821 # number of cc regfile reads -system.cpu.cc_regfile_writes 53156150 # number of cc regfile writes -system.cpu.misc_regfile_reads 348441241 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521640 # number of misc regfile writes +system.cpu.cc_regfile_reads 502646310 # number of cc regfile reads +system.cpu.cc_regfile_writes 53156218 # number of cc regfile writes +system.cpu.misc_regfile_reads 348169816 # number of misc regfile reads +system.cpu.misc_regfile_writes 1521639 # number of misc regfile writes system.cpu.dcache.tags.replacements 837355 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925653 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40093226 # Total number of references to valid blocks. +system.cpu.dcache.tags.total_refs 40093288 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 837867 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.851540 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.851614 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 441954500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.925653 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999855 # Average percentage of cache occupancy @@ -850,120 +852,120 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 120 system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179262562 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179262562 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23296906 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23296906 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15545467 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15545467 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345973 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345973 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441682 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441682 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 179262934 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179262934 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23297038 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23297038 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15545406 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15545406 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345967 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345967 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441679 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441679 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460325 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460325 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38842373 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38842373 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39188346 # number of overall hits -system.cpu.dcache.overall_hits::total 39188346 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 708692 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 708692 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3602140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3602140 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177879 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177879 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 27097 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 27097 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 38842444 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38842444 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39188411 # number of overall hits +system.cpu.dcache.overall_hits::total 39188411 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 708652 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 708652 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3602204 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3602204 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177882 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177882 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 27101 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 27101 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 7 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4310832 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4310832 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4488711 # number of overall misses -system.cpu.dcache.overall_misses::total 4488711 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11726844500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11726844500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 232349107178 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 232349107178 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373049000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 373049000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 305000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 305000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 244075951678 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 244075951678 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 244075951678 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 244075951678 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24005598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24005598 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19147607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19147607 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523852 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523852 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468779 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468779 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4310856 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4310856 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4488738 # number of overall misses +system.cpu.dcache.overall_misses::total 4488738 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11718587000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11718587000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 232348383185 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 232348383185 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 373073000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 373073000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 302000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 302000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 244066970185 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 244066970185 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 244066970185 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 244066970185 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24005690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24005690 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19147610 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19147610 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523849 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468780 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468780 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460332 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460332 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43153205 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43153205 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43677057 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43677057 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029522 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029522 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188125 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.188125 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339560 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339560 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057803 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057803 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 43153300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43153300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43677149 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43677149 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029520 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029520 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188128 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188128 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339567 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339567 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057812 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057812 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000015 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000015 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.099896 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.099896 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102770 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102770 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16547.166470 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16547.166470 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64503.075166 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64503.075166 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13767.169797 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13767.169797 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43571.428571 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56619.221458 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56619.221458 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54375.510403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54375.510403 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 870696 # number of cycles access was blocked +system.cpu.dcache.overall_miss_rate::cpu.data 0.102771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16536.448073 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16536.448073 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64501.728160 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64501.728160 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13766.023394 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13766.023394 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 43142.857143 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 43142.857143 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56616.822781 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56616.822781 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54373.182437 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54373.182437 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 869617 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6851 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6831 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.090352 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127.304494 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695416 # number of writebacks -system.cpu.dcache.writebacks::total 695416 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295634 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 295634 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302552 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3302552 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18703 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18703 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3598186 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3598186 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3598186 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3598186 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413058 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 413058 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299588 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299588 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119604 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119604 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 695423 # number of writebacks +system.cpu.dcache.writebacks::total 695423 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295601 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295601 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3302610 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3302610 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18707 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18707 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3598211 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3598211 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3598211 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3598211 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 413051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 413051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299594 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299594 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119605 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119605 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8394 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8394 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 7 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 712646 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 712646 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 712645 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 712645 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 832250 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 832250 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable @@ -972,32 +974,32 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27585 system.cpu.dcache.WriteReq_mshr_uncacheable::total 27585 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58714 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58714 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19972155480 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 19972155480 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1700460500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1700460500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6391361500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6391361500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19958097481 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 19958097481 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1699868500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1699868500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 126799500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 126799500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 298000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 298000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26364056480 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26364056480 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28064516980 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28064516980 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276327500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075770951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075770951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098451 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098451 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017207 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017207 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015646 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015646 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228316 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228316 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 295000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 295000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26349458981 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26349458981 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28049327481 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28049327481 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6276320000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6276320000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5075778951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5075778951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11352098951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11352098951 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017206 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017206 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015647 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015647 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228320 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228320 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017906 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000015 # mshr miss rate for StoreCondReq accesses @@ -1006,34 +1008,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016514 system.cpu.dcache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019055 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.019055 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15474.584683 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15474.584683 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66665.405423 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66665.405423 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14217.421658 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14217.421658 # average SoftPFReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15473.540798 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15473.540798 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66617.146809 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66617.146809 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14212.353162 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14212.353162 # average SoftPFReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15105.968549 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15105.968549 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36994.603885 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36994.603885 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33721.258011 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33721.258011 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201623.164894 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.164894 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184004.747181 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184004.747181 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.683329 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.683329 # average overall mshr uncacheable latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42142.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42142.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36974.172247 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36974.172247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33703.006886 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 33703.006886 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201622.923962 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.923962 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184005.037194 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184005.037194 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193345.691845 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193345.691845 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1886675 # number of replacements -system.cpu.icache.tags.tagsinuse 511.154168 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64239376 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1887187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34.039751 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1886695 # number of replacements +system.cpu.icache.tags.tagsinuse 511.154169 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64239998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1887207 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34.039720 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 16318088500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.154168 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.154169 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998348 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1042,76 +1044,76 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 197 system.cpu.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68105664 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68105664 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64239376 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64239376 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64239376 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64239376 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64239376 # number of overall hits -system.cpu.icache.overall_hits::total 64239376 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1979079 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1979079 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1979079 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1979079 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1979079 # number of overall misses -system.cpu.icache.overall_misses::total 1979079 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28144068491 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28144068491 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28144068491 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28144068491 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28144068491 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28144068491 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66218455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66218455 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66218455 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66218455 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66218455 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66218455 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 68106315 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68106315 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64239998 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64239998 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64239998 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64239998 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64239998 # number of overall hits +system.cpu.icache.overall_hits::total 64239998 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1979089 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1979089 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1979089 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1979089 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1979089 # number of overall misses +system.cpu.icache.overall_misses::total 1979089 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28142009491 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28142009491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28142009491 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28142009491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28142009491 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28142009491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66219087 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66219087 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66219087 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66219087 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66219087 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66219087 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029887 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.029887 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.029887 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.029887 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.029887 # miss rate for overall accesses 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14219.678595 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14219.678595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14219.678595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14219.678595 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4519 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 161 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.358025 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.068323 # average number of cycles each access was blocked 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296961 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1887169 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1887169 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 540929 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 540929 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54602 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11849 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1887169 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 296967 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 296967 # number of ReadExReq accesses(hits+misses) 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accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11849 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1887169 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2791540 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54613 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 11850 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1887187 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 837890 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2791510 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2791540 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000385 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000675 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.000436 # miss rate for ReadReq accesses @@ -1269,45 +1271,45 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988017 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988017 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.428571 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.428571 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455929 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.455929 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010515 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010515 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024854 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024854 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.455926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.455926 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010514 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010514 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024858 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024858 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000385 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000675 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010515 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.177633 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010514 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.177638 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.060437 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000385 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000675 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010515 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.177633 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010514 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.177638 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.060437 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 146714.285714 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 132750 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 142862.068966 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 800.992282 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 800.992282 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 775.266446 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 775.266446 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 54000 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 54000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 130019.424933 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 130019.424933 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132353.456964 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132353.456964 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 135340.300506 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 135340.300506 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 129968.506961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 129968.506961 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132359.389174 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132359.389174 # average ReadCleanReq miss latency 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miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 146714.285714 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 132750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132353.456964 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130500.043672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 130720.170707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132359.389174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 130445.035306 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 130672.314358 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1316,8 +1318,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88798 # number of writebacks -system.cpu.l2cache.writebacks::total 88798 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 88801 # number of writebacks +system.cpu.l2cache.writebacks::total 88801 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 26 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 26 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 113 # number of ReadSharedReq MSHR hits @@ -1335,22 +1337,22 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135393 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 135393 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19818 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19818 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 13331 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 13331 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 135395 # number of ReadExReq MSHR misses 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system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3004 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31129 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34133 # number of ReadReq MSHR uncacheable @@ -1362,34 +1364,34 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61718 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2871000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 982000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3853000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 192556500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 192556500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 212500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 212500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16249790000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16249790000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2425294500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2425294500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1672223500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1672223500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 185063000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 185063000 # number of UpgradeReq MSHR miss cycles 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overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425294500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17922013500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20351161000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2425381002 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17914387000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20343621002 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 340117000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887205500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756953000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756953000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5887198000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6227315000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4756961000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4756961000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 340117000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644158500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984275500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10644159000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10984276000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000436 # mshr miss rate for ReadReq accesses @@ -1397,108 +1399,108 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988017 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988017 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.428571 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455929 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010501 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024645 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024645 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.455926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.455926 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010500 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.024649 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024649 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.060387 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000385 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000675 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010501 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177498 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.177503 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.060387 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122750 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 132862.068966 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70766.813671 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70766.813671 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70833.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 120019.424933 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 120019.424933 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122378.368150 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122378.368150 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125438.714275 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125438.714275 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68012.862918 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68012.862918 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69833.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 119968.506961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 119968.506961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122395.084881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122395.084881 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125346.958674 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 125346.958674 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 136714.285714 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122378.368150 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120505.187461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120727.533206 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122395.084881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 120450.668334 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 120681.372474 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.859713 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.870536 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.090810 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.090810 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189122.618780 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 182442.650807 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172447.380823 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172447.380823 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113221.371505 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.253228 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.234129 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181288.261743 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177975.242231 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5483387 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758318 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5483442 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2758353 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 47114 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 382 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 382 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 381 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 381 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 128004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2556278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 128030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2556317 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27585 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27585 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 820384 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1846676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 142776 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 820394 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1886695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 149869 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296961 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 541178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1887230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 541172 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5627062 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2629120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129064 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8416504 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 239014016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323369 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47396 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 337603189 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 196948 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3052801 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.158805 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5667118 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2636221 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31264 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129096 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8463699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 241576384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98323817 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 47400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 218452 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 340166053 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 196965 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3052848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025894 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.158818 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2973766 97.41% 97.41% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 79035 2.59% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2973799 97.41% 97.41% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 79049 2.59% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3052801 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5399625997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3052848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5399685497 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 264877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2834640846 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2834668847 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1303359054 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1303356559 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19415986 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19420986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74513896 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74535395 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30198 # Transaction distribution system.iobus.trans_dist::ReadResp 30198 # Transaction distribution @@ -1550,7 +1552,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 43090500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 43091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 99500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1588,21 +1590,21 @@ system.iobus.reqLayer23.occupancy 6193500 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 33084000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186380025 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187182974 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36770000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 1.005380 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.005274 # Cycle average of tags in use system.iocache.tags.total_refs 30 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256605907000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005380 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062836 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062836 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256605904000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005274 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062830 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062830 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1618,14 +1620,14 @@ system.iocache.demand_misses::realview.ide 249 # system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31316876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31316876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717082149 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717082149 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31316876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31316876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31316876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31316876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31308877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31308877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4546803097 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4546803097 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31308877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31308877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31308877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31308877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1642,19 +1644,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125770.586345 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125770.586345 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130324.137284 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130324.137284 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125770.586345 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125770.586345 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125770.586345 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 902 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125738.461847 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125738.461847 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125619.646277 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125619.646277 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125738.461847 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125738.461847 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125738.461847 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 96 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.395833 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1668,14 +1670,14 @@ system.iocache.demand_mshr_misses::realview.ide 249 system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18866876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18866876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2907332149 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2907332149 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18866876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18866876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18866876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18866876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18858877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18858877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2735602611 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2735602611 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18858877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18858877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18858877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18858877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteLineReq accesses @@ -1684,68 +1686,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75770.586345 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75770.586345 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80324.137284 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80324.137284 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75770.586345 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75770.586345 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75738.461847 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75738.461847 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75579.572068 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75579.572068 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75738.461847 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75738.461847 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 34133 # Transaction distribution system.membus.trans_dist::ReadResp 67559 # Transaction distribution system.membus.trans_dist::WriteReq 27585 # Transaction distribution system.membus.trans_dist::WriteResp 27585 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124958 # Transaction distribution -system.membus.trans_dist::CleanEvict 7701 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124961 # Transaction distribution +system.membus.trans_dist::CleanEvict 7937 # Transaction distribution system.membus.trans_dist::UpgradeReq 4594 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution -system.membus.trans_dist::ReadExReq 133521 # Transaction distribution -system.membus.trans_dist::ReadExResp 133521 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 133523 # Transaction distribution +system.membus.trans_dist::ReadExResp 133523 # Transaction distribution system.membus.trans_dist::ReadSharedReq 33427 # Transaction distribution system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 454663 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 562233 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 671059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450075 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 557645 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 630513 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16401756 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565161 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16402076 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16565481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2315200 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2315200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18880361 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18880681 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 513 # Total snoops (count) -system.membus.snoop_fanout::samples 402363 # Request fanout histogram +system.membus.snoop_fanout::samples 402367 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402363 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402367 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402363 # Request fanout histogram -system.membus.reqLayer0.occupancy 83709500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402367 # Request fanout histogram +system.membus.reqLayer0.occupancy 83710000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1749000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1748000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 873720378 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 873736629 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 987389399 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 978197500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64116283 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1313623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8cd4c8c91..c1cc0c7a4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824799 # Number of seconds simulated -sim_ticks 2824799320500 # Number of ticks simulated -final_tick 2824799320500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824861 # Number of seconds simulated +sim_ticks 2824861157500 # Number of ticks simulated +final_tick 2824861157500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 252554 # Simulator instruction rate (inst/s) -host_op_rate 306369 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5799873287 # Simulator tick rate (ticks/s) -host_mem_usage 587696 # Number of bytes of host memory used -host_seconds 487.05 # Real time elapsed on the host -sim_insts 123005008 # Number of instructions simulated -sim_ops 149215388 # Number of ops (including micro ops) simulated +host_inst_rate 318305 # Simulator instruction rate (inst/s) +host_op_rate 386131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7310787662 # Simulator tick rate (ticks/s) +host_mem_usage 588068 # Number of bytes of host memory used +host_seconds 386.40 # Real time elapsed on the host +sim_insts 122991731 # Number of instructions simulated +sim_ops 149199638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 540900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4166756 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 103808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 925440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 328256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1677824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 415296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3014912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 541668 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4133796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 101440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 929920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 334208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1678016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 417280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3020416 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11180680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 540900 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 103808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 328256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 415296 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1388260 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8418624 # Number of bytes written to this memory +system.physmem.bytes_read::total 11164360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 541668 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 101440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 334208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 417280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1394596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8401024 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8436148 # Number of bytes written to this memory +system.physmem.bytes_written::total 8418548 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 65625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1622 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 14460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 29 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5129 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 26216 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 6489 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 47108 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16917 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 14530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 26219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 6520 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 47194 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183671 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131541 # Number of write requests responded to by this memory +system.physmem.num_reads::total 183416 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131266 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135922 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135647 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 68 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 191483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1475063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 36749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 327613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 116205 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 593962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1563 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 147018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1067301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1463363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35910 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 329191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 118310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 594017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 147717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1069226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3958044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 191483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 36749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 116205 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 147018 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2980256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2986459 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2980256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3952180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35910 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 118310 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 147717 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 493687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2973960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6203 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2980163 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2973960 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 68 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 191483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1481266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 36749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 327613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 116205 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 593962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 147018 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1067301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 191750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1469566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 329191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 118310 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 594017 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1541 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 147717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1069226 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6944503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 101122 # Number of read requests accepted -system.physmem.writeReqs 69399 # Number of write requests accepted -system.physmem.readBursts 101122 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 69399 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 6464000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 4440192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 6471808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4441536 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6932344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 101370 # Number of read requests accepted +system.physmem.writeReqs 69810 # Number of write requests accepted +system.physmem.readBursts 101370 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 69810 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 6481472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 4467008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 6487680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4467840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 22992 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7206 # Per bank write bursts -system.physmem.perBankRdBursts::1 6389 # Per bank write bursts -system.physmem.perBankRdBursts::2 6982 # Per bank write bursts -system.physmem.perBankRdBursts::3 6703 # Per bank write bursts -system.physmem.perBankRdBursts::4 6109 # Per bank write bursts -system.physmem.perBankRdBursts::5 6146 # Per bank write bursts -system.physmem.perBankRdBursts::6 6610 # Per bank write bursts -system.physmem.perBankRdBursts::7 6743 # Per bank write bursts -system.physmem.perBankRdBursts::8 6516 # Per bank write bursts -system.physmem.perBankRdBursts::9 6576 # Per bank write bursts -system.physmem.perBankRdBursts::10 6052 # Per bank write bursts -system.physmem.perBankRdBursts::11 5500 # Per bank write bursts -system.physmem.perBankRdBursts::12 5540 # Per bank write bursts -system.physmem.perBankRdBursts::13 6495 # Per bank write bursts -system.physmem.perBankRdBursts::14 6075 # Per bank write bursts -system.physmem.perBankRdBursts::15 5358 # Per bank write bursts -system.physmem.perBankWrBursts::0 4814 # Per bank write bursts -system.physmem.perBankWrBursts::1 4268 # Per bank write bursts -system.physmem.perBankWrBursts::2 4976 # Per bank write bursts -system.physmem.perBankWrBursts::3 4599 # Per bank write bursts -system.physmem.perBankWrBursts::4 4151 # Per bank write bursts -system.physmem.perBankWrBursts::5 4285 # Per bank write bursts -system.physmem.perBankWrBursts::6 4619 # Per bank write bursts -system.physmem.perBankWrBursts::7 4309 # Per bank write bursts -system.physmem.perBankWrBursts::8 4473 # Per bank write bursts -system.physmem.perBankWrBursts::9 4780 # Per bank write bursts -system.physmem.perBankWrBursts::10 4110 # Per bank write bursts -system.physmem.perBankWrBursts::11 3894 # Per bank write bursts -system.physmem.perBankWrBursts::12 3790 # Per bank write bursts -system.physmem.perBankWrBursts::13 4672 # Per bank write bursts -system.physmem.perBankWrBursts::14 4032 # Per bank write bursts -system.physmem.perBankWrBursts::15 3606 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6935 # Per bank write bursts +system.physmem.perBankRdBursts::1 6436 # Per bank write bursts +system.physmem.perBankRdBursts::2 6583 # Per bank write bursts +system.physmem.perBankRdBursts::3 6249 # Per bank write bursts +system.physmem.perBankRdBursts::4 6342 # Per bank write bursts +system.physmem.perBankRdBursts::5 6194 # Per bank write bursts +system.physmem.perBankRdBursts::6 6523 # Per bank write bursts +system.physmem.perBankRdBursts::7 6688 # Per bank write bursts +system.physmem.perBankRdBursts::8 6445 # Per bank write bursts +system.physmem.perBankRdBursts::9 6967 # Per bank write bursts +system.physmem.perBankRdBursts::10 6205 # Per bank write bursts +system.physmem.perBankRdBursts::11 5540 # Per bank write bursts +system.physmem.perBankRdBursts::12 5538 # Per bank write bursts +system.physmem.perBankRdBursts::13 6823 # Per bank write bursts +system.physmem.perBankRdBursts::14 6219 # Per bank write bursts +system.physmem.perBankRdBursts::15 5586 # Per bank write bursts +system.physmem.perBankWrBursts::0 4692 # Per bank write bursts +system.physmem.perBankWrBursts::1 4257 # Per bank write bursts +system.physmem.perBankWrBursts::2 4659 # Per bank write bursts +system.physmem.perBankWrBursts::3 4198 # Per bank write bursts +system.physmem.perBankWrBursts::4 4374 # Per bank write bursts +system.physmem.perBankWrBursts::5 4446 # Per bank write bursts +system.physmem.perBankWrBursts::6 4601 # Per bank write bursts +system.physmem.perBankWrBursts::7 4285 # Per bank write bursts +system.physmem.perBankWrBursts::8 4489 # Per bank write bursts +system.physmem.perBankWrBursts::9 5118 # Per bank write bursts +system.physmem.perBankWrBursts::10 4303 # Per bank write bursts +system.physmem.perBankWrBursts::11 3737 # Per bank write bursts +system.physmem.perBankWrBursts::12 3765 # Per bank write bursts +system.physmem.perBankWrBursts::13 4849 # Per bank write bursts +system.physmem.perBankWrBursts::14 4212 # Per bank write bursts +system.physmem.perBankWrBursts::15 3812 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2823233051500 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2823294888500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 101122 # Read request sizes (log2) +system.physmem.readPktSize::6 101370 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 69399 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 77320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 69810 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 77482 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -183,169 +183,168 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 68 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 67 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5011 # What write queue length does an incoming req see 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an incoming req see -system.physmem.wrQLenPdf::39 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3783 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 23 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39537 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 275.792296 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 163.681718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.680924 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16252 41.11% 41.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9627 24.35% 65.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3980 10.07% 75.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2061 5.21% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1623 4.11% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1029 2.60% 87.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 580 1.47% 88.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 548 1.39% 90.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3837 9.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39537 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3613 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.947135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 470.013093 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3611 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 39513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 277.080657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.075754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.106343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16212 41.03% 41.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9667 24.47% 65.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3869 9.79% 75.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2066 5.23% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1631 4.13% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 996 2.52% 87.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 644 1.63% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 576 1.46% 90.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3852 9.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39513 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3600 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.123611 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 470.848490 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3598 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3613 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3613 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.202325 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.997759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.552053 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 4 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.06% 0.17% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3600 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3600 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.388056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.044932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.866321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 5 0.14% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 2 0.06% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.14% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3178 87.96% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 101 2.80% 91.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 1.19% 92.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 66 1.83% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 15 0.42% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 1.52% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 32 0.89% 96.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.17% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 5 0.14% 97.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.33% 97.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.06% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.08% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 56 1.55% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 1 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 11 0.30% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.22% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3613 # Writes before turning the bus around for reads -system.physmem.totQLat 1315778000 # Total ticks spent queuing -system.physmem.totMemAccLat 3209528000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 505000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13027.50 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::12-15 4 0.11% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3199 88.86% 89.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 88 2.44% 91.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 45 1.25% 92.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 29 0.81% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 26 0.72% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.25% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 30 0.83% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.11% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 51 1.42% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.22% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.17% 97.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.22% 97.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 35 0.97% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.06% 98.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 15 0.42% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 27 0.75% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3600 # Writes before turning the bus around for reads +system.physmem.totQLat 1317228500 # Total ticks spent queuing +system.physmem.totMemAccLat 3216097250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 506365000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13006.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31777.50 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31756.71 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 30.16 # Average write queue length when enqueuing -system.physmem.readRowHits 81477 # Number of row buffer hits during reads -system.physmem.writeRowHits 49363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.13 # Row buffer hit rate for writes -system.physmem.avgGap 16556512.40 # Average gap between requests -system.physmem.pageHitRate 76.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 159508440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86917875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 412503000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 233416080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179779011360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73304297100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1624538062500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1878513716355 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.386003 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640260933000 # Time in different power states -system.physmem_0.memoryStateTime::REF 91911560000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.92 # Average write queue length when enqueuing +system.physmem.readRowHits 81828 # Number of row buffer hits during reads +system.physmem.writeRowHits 49728 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.80 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.23 # Row buffer hit rate for writes +system.physmem.avgGap 16493135.23 # Average gap between requests +system.physmem.pageHitRate 76.90 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 156575160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 85288500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 405210000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 230117760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179783588400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 73297208295 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1624589512500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1878547500615 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.380132 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640349085250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91913900000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20369491500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 20348745750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139391280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75900000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 375273600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 216153360 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179779011360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72455887440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616321661750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1869363278790 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.677649 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2641542244250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91911560000 # Time in different power states +system.physmem_1.actEnergy 142143120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 77405625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 384696000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 222166800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179783588400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 72817182225 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1617846694500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1871273876670 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.628012 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641092160250 # Time in different power states +system.physmem_1.memoryStateTime::REF 91913900000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19077733750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19603403000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -395,47 +394,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 4963 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 4963 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 4963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 4963 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 4963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 53087691330 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.356118 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -18905470420 -35.61% -35.61% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993161750 135.61% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 53087691330 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2701 66.40% 66.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1367 33.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4068 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4963 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 4961 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 4961 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 4961 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 4961 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 4961 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 53085056580 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.356184 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -18908069420 -35.62% -35.62% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993126000 135.62% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 53085056580 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2703 66.58% 66.58% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1357 33.42% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4060 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 4961 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4963 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4068 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 4961 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4060 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4068 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9031 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4060 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9021 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 11938297 # DTB read hits -system.cpu0.dtb.read_misses 4171 # DTB read misses -system.cpu0.dtb.write_hits 9295240 # DTB write hits -system.cpu0.dtb.write_misses 792 # DTB write misses +system.cpu0.dtb.read_hits 11954071 # DTB read hits +system.cpu0.dtb.read_misses 4163 # DTB read misses +system.cpu0.dtb.write_hits 9292740 # DTB write hits +system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 343 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2875 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2861 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 692 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 729 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 167 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 11942468 # DTB read accesses -system.cpu0.dtb.write_accesses 9296032 # DTB write accesses +system.cpu0.dtb.perms_faults 164 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 11958234 # DTB read accesses +system.cpu0.dtb.write_accesses 9293538 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21233537 # DTB hits -system.cpu0.dtb.misses 4963 # DTB misses -system.cpu0.dtb.accesses 21238500 # DTB accesses +system.cpu0.dtb.hits 21246811 # DTB hits +system.cpu0.dtb.misses 4961 # DTB misses +system.cpu0.dtb.accesses 21251772 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,650 +464,649 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2305 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2305 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2305 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2305 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 53087691330 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.356120 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -18905570920 -35.61% -35.61% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993262250 135.61% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 53087691330 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1266 73.91% 73.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 447 26.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1713 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2298 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2298 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2298 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2298 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2298 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 53085056580 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.356187 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -18908211420 -35.62% -35.62% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993268000 135.62% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 53085056580 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1259 73.88% 73.88% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 445 26.12% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1704 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2305 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2305 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2298 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2298 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1713 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1713 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4018 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 57022290 # ITB inst hits -system.cpu0.itb.inst_misses 2305 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1704 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4002 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 57099385 # ITB inst hits +system.cpu0.itb.inst_misses 2298 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 171 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 345 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 343 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1719 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1710 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 57024595 # ITB inst accesses -system.cpu0.itb.hits 57022290 # DTB hits -system.cpu0.itb.misses 2305 # DTB misses -system.cpu0.itb.accesses 57024595 # DTB accesses -system.cpu0.numCycles 68977361 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 57101683 # ITB inst accesses +system.cpu0.itb.hits 57099385 # DTB hits +system.cpu0.itb.misses 2298 # DTB misses +system.cpu0.itb.accesses 57101683 # DTB accesses +system.cpu0.numCycles 69056574 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3088 # number of quiesce instructions executed -system.cpu0.committedInsts 55612915 # Number of instructions committed -system.cpu0.committedOps 67456889 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 59167201 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4525 # Number of float alu accesses -system.cpu0.num_func_calls 5730859 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7383240 # number of instructions that are conditional controls -system.cpu0.num_int_insts 59167201 # number of integer instructions -system.cpu0.num_fp_insts 4525 # number of float instructions -system.cpu0.num_int_register_reads 109233677 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41018104 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3419 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1108 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 205348706 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25186036 # number of times the CC registers were written -system.cpu0.num_mem_refs 21795373 # number of memory refs -system.cpu0.num_load_insts 12079832 # Number of load instructions -system.cpu0.num_store_insts 9715541 # Number of store instructions -system.cpu0.num_idle_cycles 65194671.854537 # Number of idle cycles -system.cpu0.num_busy_cycles 3782689.145463 # Number of busy cycles -system.cpu0.not_idle_fraction 0.054840 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.945160 # Percentage of idle cycles -system.cpu0.Branches 13504260 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2176 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46697221 68.12% 68.13% # Class of executed instruction -system.cpu0.op_class::IntMult 49891 0.07% 68.20% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3798 0.01% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.20% # Class of executed instruction -system.cpu0.op_class::MemRead 12079832 17.62% 85.83% # Class of executed instruction -system.cpu0.op_class::MemWrite 9715541 14.17% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3089 # number of quiesce instructions executed +system.cpu0.committedInsts 55687288 # Number of instructions committed +system.cpu0.committedOps 67533449 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 59242376 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4494 # Number of float alu accesses +system.cpu0.num_func_calls 5745250 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7381553 # number of instructions that are conditional controls +system.cpu0.num_int_insts 59242376 # number of integer instructions +system.cpu0.num_fp_insts 4494 # number of float instructions +system.cpu0.num_int_register_reads 109364811 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41080412 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3324 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1172 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 205588674 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25205684 # number of times the CC registers were written +system.cpu0.num_mem_refs 21809022 # number of memory refs +system.cpu0.num_load_insts 12095983 # Number of load instructions +system.cpu0.num_store_insts 9713039 # Number of store instructions +system.cpu0.num_idle_cycles 65267085.823243 # Number of idle cycles +system.cpu0.num_busy_cycles 3789488.176757 # Number of busy cycles +system.cpu0.not_idle_fraction 0.054875 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.945125 # Percentage of idle cycles +system.cpu0.Branches 13519145 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46763414 68.14% 68.14% # Class of executed instruction +system.cpu0.op_class::IntMult 50008 0.07% 68.22% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3788 0.01% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.22% # Class of executed instruction +system.cpu0.op_class::MemRead 12095983 17.63% 85.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 9713039 14.15% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68548459 # Class of executed instruction -system.cpu0.dcache.tags.replacements 833427 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996688 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46067752 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 833939 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.241153 # Average number of references to valid blocks. +system.cpu0.op_class::total 68628410 # Class of executed instruction +system.cpu0.dcache.tags.replacements 834050 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996936 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 46064647 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834562 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.196195 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 476.386497 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.984373 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.249015 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.376803 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.930442 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023407 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012205 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.033939 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 476.071339 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 12.092828 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.251514 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 17.581255 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929827 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.023619 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.012210 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.034338 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193252454 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193252454 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11340872 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3665086 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4347150 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6492094 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25845202 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8951769 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2627923 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3357260 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 3986228 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18923180 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 168663 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 54737 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 74832 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87703 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 385935 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 206642 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 75155 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 78814 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 89773 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450384 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 207452 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 77217 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 81680 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 93734 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460083 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20292641 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6293009 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7704410 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 10478322 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44768382 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20461304 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6347746 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7779242 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 10566025 # number of overall hits -system.cpu0.dcache.overall_hits::total 45154317 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 159917 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 57186 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 95818 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 208300 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 521221 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 127063 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 30733 # number of WriteReq misses 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LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 18027 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 193245600 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 193245600 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11356239 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 3664672 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4328495 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 6495255 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25844661 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 8949597 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 2623161 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3363595 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 3984568 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 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-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3278344952 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6305646952 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015344 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018103 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016846 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009498 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011560 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015252 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017445 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008492 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.211302 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.227868 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.132218 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.014025 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.017656 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.026880 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.011063 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000309 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 87593 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 133992 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 201996 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 423581 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 105275 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 156882 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 230897 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 493054 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 3437 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 5496 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 8482 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17415 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 2787 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4251 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6706 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13744 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 6224 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 9747 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 15188 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31159 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 958493000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1169060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1757320500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3884873500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1854536500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3569217500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 6426569434 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11850323434 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 232220000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 318179000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 509429500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1059828500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 15415000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 25315500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 42891000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 83621500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 1111000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1111000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2813029500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 4738277500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 8183889934 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15735196934 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3045249500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 5056456500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 8693319434 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16795025434 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 605676500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1091329500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1833276500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3530282500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 494376000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 836760000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1430842452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2761978452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1100052500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1928089500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 3264118952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6292260952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015249 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018187 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016878 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009496 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011622 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015462 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017449 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008540 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244021 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.212910 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.227036 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.132363 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.013283 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.017913 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.027830 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.011183 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000308 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013767 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016856 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017105 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009061 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016372 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019457 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019351 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010430 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17047.371001 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14552.325654 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15524.770106 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15559.701701 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 59770.735041 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 67412.098030 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72324.014338 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68582.461293 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13307.854256 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13918.954162 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17577.227347 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15288.345680 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17125.915751 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17194.996573 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16125.047510 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16637.205712 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 37224.137931 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37224.137931 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 31994.177310 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35471.939868 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40542.790998 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37169.316238 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28844.006133 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32340.923393 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37660.970262 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34084.093609 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177105.361239 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198224.875988 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 215905.993432 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202640.545340 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178532.451499 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196258.271840 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213093.752149 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200852.630387 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 177745.215879 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197368.208212 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214663.760608 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201851.754282 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013739 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.016991 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.017125 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009080 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.016327 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019626 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019366 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010452 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16890.339748 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14528.801342 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15530.343603 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15516.715462 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60124.379964 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 66680.693855 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 72337.063934 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 68414.351230 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13133.129736 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13900.349498 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 17626.708418 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15255.257438 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15024.366472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 17139.810427 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15682.266910 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15964.394807 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 38310.344828 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 38310.344828 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 32114.775153 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 35362.391038 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 40515.108883 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 37148.023481 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 28926.616006 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 32230.953838 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 37650.205217 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34063.257643 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176222.432354 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 198567.958515 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 216137.290733 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202715.044502 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177386.437029 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196838.390967 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 213367.499553 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200958.851281 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176743.653599 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 197813.634965 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 214914.337108 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 201940.400911 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1980846 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-system.cpu0.icache.overall_mshr_misses::total 1259649 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2649785000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6659762500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7509042490 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 16818589990 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2649785000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6659762500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7509042490 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 16818589990 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2649785000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6659762500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7509042490 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 16818589990 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011276 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045943 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.056331 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013139 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011276 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045943 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.056331 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013139 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011276 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045943 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.056331 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013139 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12990.160993 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13265.772091 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13563.066348 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13351.806726 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12990.160993 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13265.772091 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13563.066348 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13351.806726 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12990.160993 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13265.772091 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13563.066348 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13351.806726 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 1988229 # number of writebacks +system.cpu0.icache.writebacks::total 1988229 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 44061 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 44061 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 44061 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 44061 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 44061 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 44061 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 206297 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 502765 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 556380 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1265442 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 206297 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 502765 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 556380 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1265442 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 206297 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 502765 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 556380 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1265442 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2674711500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6681541500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 7547458483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16903711483 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2674711500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6681541500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 7547458483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16903711483 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2674711500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6681541500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 7547458483 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16903711483 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.046080 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.056747 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013194 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.046080 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.056747 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013194 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011401 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.046080 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.056747 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013194 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12965.343655 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13289.591559 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13565.294373 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13357.950410 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12965.343655 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 13289.591559 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 13565.294373 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13357.950410 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12965.343655 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 13289.591559 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 13565.294373 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13357.950410 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1139,60 +1137,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1928 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1928 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 500 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1428 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1928 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1928 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1928 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1628 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13253.992629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11553.834233 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6560.213470 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 361 22.17% 22.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::6144-8191 74 4.55% 26.72% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 476 29.24% 55.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 145 8.91% 64.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 172 10.57% 75.43% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-18431 41 2.52% 77.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 347 21.31% 99.26% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-26623 12 0.74% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1628 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1881 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1881 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 484 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1881 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1881 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1881 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1593 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 14363.151287 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 12650.519591 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6659.719490 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 280 17.58% 17.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::6144-8191 51 3.20% 20.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 461 28.94% 49.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 64 4.02% 53.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 240 15.07% 68.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-18431 70 4.39% 73.20% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 406 25.49% 98.68% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-26623 21 1.32% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1593 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1130 69.41% 69.41% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 498 30.59% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1628 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1928 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1111 69.74% 69.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 482 30.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1593 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1881 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1928 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1628 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1881 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1593 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1628 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3556 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1593 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3474 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3876436 # DTB read hits -system.cpu1.dtb.read_misses 1705 # DTB read misses -system.cpu1.dtb.write_hits 2738772 # DTB write hits -system.cpu1.dtb.write_misses 223 # DTB write misses +system.cpu1.dtb.read_hits 3874640 # DTB read hits +system.cpu1.dtb.read_misses 1654 # DTB read misses +system.cpu1.dtb.write_hits 2733455 # DTB write hits +system.cpu1.dtb.write_misses 227 # DTB write misses system.cpu1.dtb.flush_tlb 150 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 133 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1110 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1091 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 221 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 64 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3878141 # DTB read accesses -system.cpu1.dtb.write_accesses 2738995 # DTB write accesses +system.cpu1.dtb.read_accesses 3876294 # DTB read accesses +system.cpu1.dtb.write_accesses 2733682 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6615208 # DTB hits -system.cpu1.dtb.misses 1928 # DTB misses -system.cpu1.dtb.accesses 6617136 # DTB accesses +system.cpu1.dtb.hits 6608095 # DTB hits +system.cpu1.dtb.misses 1881 # DTB misses +system.cpu1.dtb.accesses 6609976 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1222,130 +1220,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 970 # Table walker walks requested -system.cpu1.itb.walker.walksShort 970 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 790 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 970 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 970 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 970 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 698 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12663.323782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10953.370627 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6428.547911 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 206 29.51% 29.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.14% 29.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 176 25.21% 54.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 64 9.17% 64.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 123 17.62% 81.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 124 17.77% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-26623 4 0.57% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 698 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 931 # Table walker walks requested +system.cpu1.itb.walker.walksShort 931 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 754 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 931 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 931 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 674 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13750.741840 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12141.602155 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6305.334498 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 145 21.51% 21.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::6144-8191 1 0.15% 21.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 171 25.37% 47.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 42 6.23% 53.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 173 25.67% 78.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 137 20.33% 99.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-26623 5 0.74% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 674 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 518 74.21% 74.21% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 180 25.79% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 698 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 497 73.74% 73.74% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 177 26.26% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 674 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 970 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 970 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 931 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 931 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 698 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 698 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1668 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 18090241 # ITB inst hits -system.cpu1.itb.inst_misses 970 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1605 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 18095406 # ITB inst hits +system.cpu1.itb.inst_misses 931 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 150 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 133 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 729 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 705 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 18091211 # ITB inst accesses -system.cpu1.itb.hits 18090241 # DTB hits -system.cpu1.itb.misses 970 # DTB misses -system.cpu1.itb.accesses 18091211 # DTB accesses -system.cpu1.numCycles 144011692 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 18096337 # ITB inst accesses +system.cpu1.itb.hits 18095406 # DTB hits +system.cpu1.itb.misses 931 # DTB misses +system.cpu1.itb.accesses 18096337 # DTB accesses +system.cpu1.numCycles 144011073 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 17421387 # Number of instructions committed -system.cpu1.committedOps 20908811 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18586966 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1243 # Number of float alu accesses -system.cpu1.num_func_calls 1994388 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2228706 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18586966 # number of integer instructions -system.cpu1.num_fp_insts 1243 # number of float instructions -system.cpu1.num_int_register_reads 34395717 # number of times the integer registers were read -system.cpu1.num_int_register_writes 13039867 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1047 # number of times the floating registers were read +system.cpu1.committedInsts 17425922 # Number of instructions committed +system.cpu1.committedOps 20908303 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18576861 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1355 # Number of float alu accesses +system.cpu1.num_func_calls 1992339 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2240244 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18576861 # number of integer instructions +system.cpu1.num_fp_insts 1355 # number of float instructions +system.cpu1.num_int_register_reads 34373942 # number of times the integer registers were read +system.cpu1.num_int_register_writes 13031779 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1159 # number of times the floating registers were read system.cpu1.num_fp_register_writes 196 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 76120282 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7571334 # number of times the CC registers were written -system.cpu1.num_mem_refs 6808450 # number of memory refs -system.cpu1.num_load_insts 3918979 # Number of load instructions -system.cpu1.num_store_insts 2889471 # Number of store instructions -system.cpu1.num_idle_cycles 136781206.784887 # Number of idle cycles -system.cpu1.num_busy_cycles 7230485.215113 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050208 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949792 # Percentage of idle cycles -system.cpu1.Branches 4335876 # Number of branches fetched -system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14685914 68.27% 68.27% # Class of executed instruction -system.cpu1.op_class::IntMult 16370 0.08% 68.35% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 946 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.35% # Class of executed instruction -system.cpu1.op_class::MemRead 3918979 18.22% 86.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 2889471 13.43% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 76108520 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7595432 # number of times the CC registers were written +system.cpu1.num_mem_refs 6800589 # number of memory refs +system.cpu1.num_load_insts 3916596 # Number of load instructions +system.cpu1.num_store_insts 2883993 # Number of store instructions +system.cpu1.num_idle_cycles 136777457.840207 # Number of idle cycles +system.cpu1.num_busy_cycles 7233615.159793 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050230 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949770 # Percentage of idle cycles +system.cpu1.Branches 4344988 # Number of branches fetched +system.cpu1.op_class::No_OpClass 22 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14692274 68.30% 68.30% # Class of executed instruction +system.cpu1.op_class::IntMult 16424 0.08% 68.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.38% # Class of executed instruction +system.cpu1.op_class::MemRead 3916596 18.21% 86.59% # Class of executed instruction +system.cpu1.op_class::MemWrite 2883993 13.41% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21511704 # Class of executed instruction -system.cpu2.branchPred.lookups 5805237 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2994100 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 512421 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3358874 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2415611 # Number of BTB hits +system.cpu1.op_class::total 21510267 # Class of executed instruction +system.cpu2.branchPred.lookups 5796775 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2983658 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 509824 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3342660 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2404944 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.917285 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1615920 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 333124 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.947012 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1622496 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331360 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,55 +1373,54 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12664 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12664 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8020 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4644 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12664 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12664 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12664 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2157 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 12096.893834 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 10423.094509 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6904.169413 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-16383 1795 83.22% 83.22% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-32767 361 16.74% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-147455 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2157 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 13089 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 13089 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 8217 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4872 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 13089 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 13089 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 13089 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2190 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 13303.881279 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 11625.278622 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 8511.286061 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 2189 99.95% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2190 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000052000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000052000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000052000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1306 60.55% 60.55% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 851 39.45% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2157 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12664 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1357 61.96% 61.96% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 833 38.04% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2190 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 13089 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12664 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2157 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 13089 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2190 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2157 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14821 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2190 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 15279 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4677262 # DTB read hits -system.cpu2.dtb.read_misses 11320 # DTB read misses -system.cpu2.dtb.write_hits 3564595 # DTB write hits -system.cpu2.dtb.write_misses 1344 # DTB write misses -system.cpu2.dtb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 157 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 4658776 # DTB read hits +system.cpu2.dtb.read_misses 11701 # DTB read misses +system.cpu2.dtb.write_hits 3572503 # DTB write hits +system.cpu2.dtb.write_misses 1388 # DTB write misses +system.cpu2.dtb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1473 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 212 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 332 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1490 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 207 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 330 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 121 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4688582 # DTB read accesses -system.cpu2.dtb.write_accesses 3565939 # DTB write accesses +system.cpu2.dtb.perms_faults 125 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4670477 # DTB read accesses +system.cpu2.dtb.write_accesses 3573891 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 8241857 # DTB hits -system.cpu2.dtb.misses 12664 # DTB misses -system.cpu2.dtb.accesses 8254521 # DTB accesses +system.cpu2.dtb.hits 8231279 # DTB hits +system.cpu2.dtb.misses 13089 # DTB misses +system.cpu2.dtb.accesses 8244368 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1453,81 +1450,82 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1329 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1329 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 263 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1066 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1329 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1329 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1329 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 852 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12299.295775 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 10742.634902 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6145.721581 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 262 30.75% 30.75% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 255 29.93% 60.68% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 38 4.46% 65.14% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 163 19.13% 84.27% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 131 15.38% 99.65% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 1368 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1368 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 248 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1120 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1368 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 861 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 13222.996516 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 11667.249033 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6172.725517 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 213 24.74% 24.74% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::6144-8191 1 0.12% 24.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 235 27.29% 52.15% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 37 4.30% 56.45% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 216 25.09% 81.53% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 156 18.12% 99.65% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::24576-26623 3 0.35% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 852 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 861 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000037500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000037500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000037500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 589 69.13% 69.13% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 263 30.87% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 852 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 613 71.20% 71.20% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 248 28.80% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 861 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1329 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1329 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1368 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1368 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 852 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 852 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2181 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10929097 # ITB inst hits -system.cpu2.itb.inst_misses 1329 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 861 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 861 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2229 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10912675 # ITB inst hits +system.cpu2.itb.inst_misses 1368 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 154 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 157 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 153 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 862 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 871 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1732 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10930426 # ITB inst accesses -system.cpu2.itb.hits 10929097 # DTB hits -system.cpu2.itb.misses 1329 # DTB misses -system.cpu2.itb.accesses 10930426 # DTB accesses -system.cpu2.numCycles 1393382531 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10914043 # ITB inst accesses +system.cpu2.itb.hits 10912675 # DTB hits +system.cpu2.itb.misses 1368 # DTB misses +system.cpu2.itb.accesses 10914043 # DTB accesses +system.cpu2.numCycles 1393518293 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 20580093 # Number of instructions committed -system.cpu2.committedOps 24901206 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1467300 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 567 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4256226860 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 67.705356 # CPI: cycles per instruction -system.cpu2.ipc 0.014770 # IPC: instructions per cycle +system.cpu2.committedInsts 20499509 # Number of instructions committed +system.cpu2.committedOps 24824986 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1466668 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 563 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4256214875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 67.978130 # CPI: cycles per instruction +system.cpu2.ipc 0.014711 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 42624758 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1350757773 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13301320 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7249235 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 312069 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8284814 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6256612 # Number of BTB hits +system.cpu2.tickCycles 42617577 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1350900716 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13279535 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7247058 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 312507 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8265977 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6247053 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.519040 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3109270 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16225 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 75.575495 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3099050 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 16324 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1557,88 +1555,86 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 33037 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 33037 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11464 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7705 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 13868 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19169 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 496.400438 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 3535.731274 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19002 99.13% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 134 0.70% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 21 0.11% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::49152-65535 6 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19169 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6102 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 13023.926581 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10629.521640 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 8508.049417 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-16383 4638 76.01% 76.01% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1335 21.88% 97.89% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-49151 115 1.88% 99.77% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-65535 9 0.15% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-81919 1 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walks 33115 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33115 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11558 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7619 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 13938 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19177 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 468.973249 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 3138.682305 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-8191 18760 97.83% 97.83% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::8192-16383 261 1.36% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-24575 95 0.50% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::24576-32767 29 0.15% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-40959 11 0.06% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::40960-49151 11 0.06% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::49152-57343 5 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-73727 4 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 19177 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6222 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 13175.506268 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 10775.791198 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 8313.068780 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-16383 4548 73.10% 73.10% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-32767 1554 24.98% 98.07% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-49151 108 1.74% 99.81% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-65535 9 0.14% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu3.dtb.walker.walkCompletionTime::147456-163839 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6102 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8042044064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.800774 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::stdev 0.238438 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8088297564 100.58% 100.58% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32871500 -0.41% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7478500 -0.09% 100.07% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2286500 -0.03% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1244500 -0.02% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 730000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 408500 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 765000 -0.01% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 196000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 177000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 43000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 10500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 11000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 4500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walkCompletionTime::total 6222 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8045387064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 1.137184 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8091405064 100.57% 100.57% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 33349500 -0.41% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 6720000 -0.08% 100.07% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 2348000 -0.03% 100.04% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1216500 -0.02% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 680000 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 415500 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 841500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 133000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 159500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 77000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 11000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 34000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 10000 -0.00% 100.00% # Table walker pending requests distribution system.cpu3.dtb.walker.walksPending::28-29 3500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 23500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8042044064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1824 68.91% 68.91% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 823 31.09% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33037 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8045387064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1814 68.95% 68.95% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 817 31.05% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2631 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33115 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33037 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33115 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2631 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 35684 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2631 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 35746 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7253561 # DTB read hits -system.cpu3.dtb.read_misses 28594 # DTB read misses -system.cpu3.dtb.write_hits 5432397 # DTB write hits -system.cpu3.dtb.write_misses 4443 # DTB write misses -system.cpu3.dtb.flush_tlb 161 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA +system.cpu3.dtb.read_hits 7259419 # DTB read hits +system.cpu3.dtb.read_misses 28704 # DTB read misses +system.cpu3.dtb.write_hits 5430970 # DTB write hits +system.cpu3.dtb.write_misses 4411 # DTB write misses +system.cpu3.dtb.flush_tlb 162 # Number of times complete TLB was flushed +system.cpu3.dtb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1945 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 458 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 789 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1937 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 485 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 827 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 336 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7282155 # DTB read accesses -system.cpu3.dtb.write_accesses 5436840 # DTB write accesses +system.cpu3.dtb.perms_faults 313 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7288123 # DTB read accesses +system.cpu3.dtb.write_accesses 5435381 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 12685958 # DTB hits -system.cpu3.dtb.misses 33037 # DTB misses -system.cpu3.dtb.accesses 12718995 # DTB accesses +system.cpu3.dtb.hits 12690389 # DTB hits +system.cpu3.dtb.misses 33115 # DTB misses +system.cpu3.dtb.accesses 12723504 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1668,389 +1664,386 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4585 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4585 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1570 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2921 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 94 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4491 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1433.533734 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 6108.583355 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-8191 4220 93.97% 93.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::8192-16383 132 2.94% 96.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-24575 81 1.80% 98.71% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::24576-32767 32 0.71% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-40959 7 0.16% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::40960-49151 7 0.16% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-57343 2 0.04% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::57344-65535 2 0.04% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-73727 2 0.04% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-90111 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::90112-98303 2 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-106495 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4491 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 1402 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 13658.345221 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 11345.191727 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7983.067706 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 20 1.43% 1.43% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 28.74% 30.17% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 331 23.61% 53.78% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 266 18.97% 72.75% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 21 1.50% 74.25% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 301 21.47% 95.72% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 32 2.28% 98.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 5 0.36% 98.36% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 3 0.21% 98.57% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 5 0.36% 98.93% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 11 0.78% 99.71% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.14% 99.86% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 1402 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8073456064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.704569 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.455286 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -2382514092 29.51% 29.51% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -5692999972 70.52% 100.03% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1707500 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 179000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 115500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 56000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8073456064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 964 73.70% 73.70% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 344 26.30% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1308 # Table walker page sizes translated +system.cpu3.itb.walker.walks 4611 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4611 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1576 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2936 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 99 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4512 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1190.824468 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 4827.188758 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 4272 94.68% 94.68% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 112 2.48% 97.16% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 85 1.88% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 29 0.64% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 6 0.13% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 4 0.09% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4512 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 1416 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13825.918079 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 11456.247028 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 8136.352957 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 24 1.69% 1.69% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 390 27.54% 29.24% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 346 24.44% 53.67% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 256 18.08% 71.75% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 18 1.27% 73.02% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 314 22.18% 95.20% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 43 3.04% 98.23% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.28% 98.52% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 3 0.21% 98.73% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 3 0.21% 98.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 8 0.56% 99.51% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 3 0.21% 99.72% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.07% 99.79% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::61440-65535 1 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 1416 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -3903952768 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.701862 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.456296 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1162140296 29.77% 29.77% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -2743359472 70.27% 100.04% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1351500 -0.03% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 161000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 34500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -3903952768 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 967 73.42% 73.42% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 350 26.58% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1317 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4585 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4585 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4611 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4611 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1308 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1308 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5893 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9829313 # ITB inst hits -system.cpu3.itb.inst_misses 4585 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1317 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1317 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5928 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9805675 # ITB inst hits +system.cpu3.itb.inst_misses 4611 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 161 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 273 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb 162 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb_mva 274 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1305 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1315 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 736 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 717 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 9833898 # ITB inst accesses -system.cpu3.itb.hits 9829313 # DTB hits -system.cpu3.itb.misses 4585 # DTB misses -system.cpu3.itb.accesses 9833898 # DTB accesses -system.cpu3.numCycles 58255672 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9810286 # ITB inst accesses +system.cpu3.itb.hits 9805675 # DTB hits +system.cpu3.itb.misses 4611 # DTB misses +system.cpu3.itb.accesses 9810286 # DTB accesses +system.cpu3.numCycles 58198080 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20975785 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 52339111 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13301320 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9365882 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 34230578 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1600984 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 75110 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 679 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 249 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 165248 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 76892 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 429 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9828258 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 213311 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2192 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 56325440 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.124081 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.271401 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 21004644 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 52275874 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13279535 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9346103 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 34135840 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1598180 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 75752 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 771 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 231 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 170446 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 76408 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 496 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9804624 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 214264 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2206 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 56263657 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.123824 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.271758 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 42135738 74.81% 74.81% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1842427 3.27% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1174880 2.09% 80.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3692209 6.56% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 916764 1.63% 88.35% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 558692 0.99% 89.34% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2925255 5.19% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 602319 1.07% 95.60% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2477156 4.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 42100278 74.83% 74.83% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1838046 3.27% 78.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1170997 2.08% 80.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3679420 6.54% 86.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 917674 1.63% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 559385 0.99% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2919080 5.19% 94.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 600185 1.07% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2478592 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 56325440 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.228327 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.898438 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14665639 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 32213939 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 7840695 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 894660 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 710284 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 980840 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 91372 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 45017968 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 299154 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 710284 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15152191 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3825257 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 22150592 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8241060 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 6245828 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 43133854 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 881 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 923199 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 93585 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 4851932 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 44760576 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 198184537 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 48159961 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3993 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 37280661 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 7479915 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 724518 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 673070 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5055817 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 7747142 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6009339 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1097938 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1536830 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 41471519 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 515844 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 39457989 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 52603 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6038881 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 13851448 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 54585 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 56325440 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.700536 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.407802 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 56263657 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.228178 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.898241 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14695652 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 32129586 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 7839305 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 889993 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 708923 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 981902 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 91350 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 45004399 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 298008 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 708923 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15180574 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 3814501 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 22072917 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8236779 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 6249745 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 43123968 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 829 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 908553 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 90362 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4872933 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 44747932 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 198117330 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 48138419 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3926 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 37260005 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7487927 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 723224 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 671648 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5026285 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 7752515 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6007333 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1093193 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1517567 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 41462674 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 517140 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 39449683 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 52518 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6046914 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 13857480 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 54926 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 56263657 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.701157 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.409344 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 40673603 72.21% 72.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5189038 9.21% 81.42% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 3994905 7.09% 88.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3229029 5.73% 94.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1266179 2.25% 96.50% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 777932 1.38% 97.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 838695 1.49% 99.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 242964 0.43% 99.80% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 113095 0.20% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 40631196 72.22% 72.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5180458 9.21% 81.42% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 3984831 7.08% 88.51% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3217649 5.72% 94.22% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1270759 2.26% 96.48% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 778914 1.38% 97.87% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 843481 1.50% 99.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 242828 0.43% 99.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 113541 0.20% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 56325440 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 56263657 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 56406 9.38% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.38% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 283401 47.13% 56.51% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 261530 43.49% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 56843 9.40% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 285724 47.25% 56.65% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 262185 43.35% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 83 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 26250639 66.53% 66.53% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 29940 0.08% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.60% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2415 0.01% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7470638 18.93% 85.54% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 5704269 14.46% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 26236947 66.51% 66.51% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 29772 0.08% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.58% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2427 0.01% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.59% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7477838 18.96% 85.54% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 5702609 14.46% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 39457989 # Type of FU issued -system.cpu3.iq.rate 0.677324 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 601337 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015240 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 135886575 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 48050717 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 38292520 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 8783 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3829 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 40054524 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4719 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 171660 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 39449683 # Type of FU issued +system.cpu3.iq.rate 0.677852 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 604752 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015330 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 135811723 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 48051371 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 38283859 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 8570 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4586 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3750 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 40049753 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4598 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 172364 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1179297 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1335 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 29850 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 609995 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1182055 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1378 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 29890 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 609761 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 109451 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 43922 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 109360 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 44921 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 710284 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 3184032 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 520990 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 42035728 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 77277 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 7747142 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6009339 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 266862 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 22482 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 492410 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 29850 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 141082 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 125238 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 266320 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 39125976 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7338106 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 299066 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 708923 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 3187363 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 509464 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 42027375 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 77349 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 7752515 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6007333 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 267430 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 22605 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 480734 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 29890 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 141333 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 125701 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 267034 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 39117599 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7344612 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 299061 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 48365 # number of nop insts executed -system.cpu3.iew.exec_refs 12982427 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7264644 # Number of branches executed -system.cpu3.iew.exec_stores 5644321 # Number of stores executed -system.cpu3.iew.exec_rate 0.671625 # Inst execution rate -system.cpu3.iew.wb_sent 38838436 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 38296349 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 20014644 # num instructions producing a value -system.cpu3.iew.wb_consumers 34860024 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.657384 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.574143 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 6055415 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 461259 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 221839 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 55029535 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.653724 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.548863 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 47561 # number of nop insts executed +system.cpu3.iew.exec_refs 12987668 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7261479 # Number of branches executed +system.cpu3.iew.exec_stores 5643056 # Number of stores executed +system.cpu3.iew.exec_rate 0.672146 # Inst execution rate +system.cpu3.iew.wb_sent 38828070 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 38287609 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 20013510 # num instructions producing a value +system.cpu3.iew.wb_consumers 34846989 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.657884 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.574325 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 6062120 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 462214 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 222319 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 54968801 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.654162 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.550259 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 41164710 74.80% 74.80% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6174910 11.22% 86.03% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3105944 5.64% 91.67% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1319292 2.40% 94.07% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 711711 1.29% 95.36% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 496248 0.90% 96.26% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 960829 1.75% 98.01% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 230731 0.42% 98.43% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 865160 1.57% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 41122825 74.81% 74.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6168562 11.22% 86.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3091321 5.62% 91.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1317611 2.40% 94.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 712190 1.30% 95.35% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 498110 0.91% 96.26% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 959967 1.75% 98.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 230353 0.42% 98.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 867862 1.58% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 55029535 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 29416260 # Number of instructions committed -system.cpu3.commit.committedOps 35974129 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 54968801 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 29404628 # Number of instructions committed +system.cpu3.commit.committedOps 35958516 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 11967189 # Number of memory references committed -system.cpu3.commit.loads 6567845 # Number of loads committed -system.cpu3.commit.membars 179077 # Number of memory barriers committed -system.cpu3.commit.branches 6853829 # Number of branches committed -system.cpu3.commit.fp_insts 3808 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 31432423 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1245286 # Number of function calls committed. +system.cpu3.commit.refs 11968032 # Number of memory references committed +system.cpu3.commit.loads 6570460 # Number of loads committed +system.cpu3.commit.membars 179741 # Number of memory barriers committed +system.cpu3.commit.branches 6849330 # Number of branches committed +system.cpu3.commit.fp_insts 3728 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 31415410 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1242435 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 23975618 66.65% 66.65% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 28907 0.08% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2415 0.01% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.73% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6567845 18.26% 84.99% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5399344 15.01% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 23959277 66.63% 66.63% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 28780 0.08% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.71% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2427 0.01% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.72% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6570460 18.27% 84.99% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5397572 15.01% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 35974129 # Class of committed instruction -system.cpu3.commit.bw_lim_events 865160 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90545687 # The number of ROB reads -system.cpu3.rob.rob_writes 85357421 # The number of ROB writes -system.cpu3.timesIdled 228818 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1930232 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5160394940 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 29390613 # Number of Instructions Simulated -system.cpu3.committedOps 35948482 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.982118 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.982118 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.504511 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.504511 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 42625892 # number of integer regfile reads -system.cpu3.int_regfile_writes 24241203 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14445 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12329 # number of floating regfile writes -system.cpu3.cc_regfile_reads 138329125 # number of cc regfile reads -system.cpu3.cc_regfile_writes 14829178 # number of cc regfile writes -system.cpu3.misc_regfile_reads 76422783 # number of misc regfile reads -system.cpu3.misc_regfile_writes 345191 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.cpu3.commit.op_class_0::total 35958516 # Class of committed instruction +system.cpu3.commit.bw_lim_events 867862 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90498066 # The number of ROB reads +system.cpu3.rob.rob_writes 85338530 # The number of ROB writes +system.cpu3.timesIdled 230176 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1934423 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5160447116 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 29379012 # Number of Instructions Simulated +system.cpu3.committedOps 35932900 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.980941 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.980941 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.504811 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.504811 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 42612953 # number of integer regfile reads +system.cpu3.int_regfile_writes 24236017 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14441 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12266 # number of floating regfile writes +system.cpu3.cc_regfile_reads 138314528 # number of cc regfile reads +system.cpu3.cc_regfile_writes 14822107 # number of cc regfile writes +system.cpu3.misc_regfile_reads 76357386 # number of misc regfile reads +system.cpu3.misc_regfile_writes 345684 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30184 # Transaction distribution +system.iobus.trans_dist::ReadResp 30184 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution system.iobus.trans_dist::WriteResp 59010 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54148 # Packet count per connected master and slave (bytes) @@ -2073,9 +2066,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105436 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178388 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67865 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2096,20 +2089,20 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159093 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 27670500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480341 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 27687500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 101500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 205000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 207000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 16500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) @@ -2117,482 +2110,480 @@ system.iobus.reqLayer19.occupancy 3000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3858000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3849500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 22212000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 22107000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 78391042 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 78684521 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 48071000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 47950000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 15512000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 15518000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36409 # number of replacements -system.iocache.tags.tagsinuse 1.005312 # Cycle average of tags in use -system.iocache.tags.total_refs 30 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 249222416009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.005312 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062832 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062832 # Average percentage of cache occupancy +system.iocache.tags.replacements 36442 # number of replacements +system.iocache.tags.tagsinuse 1.005646 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 249220700509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.005646 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062853 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062853 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328227 # Number of tag accesses -system.iocache.tags.data_accesses 328227 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 29 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 29 # number of WriteLineReq hits -system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses -system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteLineReq_misses::realview.ide 36195 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 36195 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses -system.iocache.demand_misses::total 249 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 249 # number of overall misses -system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 17512919 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 17512919 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1978574123 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1978574123 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 17512919 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 17512919 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 17512919 # number of overall miss cycles -system.iocache.overall_miss_latency::total 17512919 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.iocache.tags.tag_accesses 328284 # Number of tag accesses +system.iocache.tags.data_accesses 328284 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses +system.iocache.ReadReq_misses::total 252 # number of ReadReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses +system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses +system.iocache.demand_misses::total 252 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 252 # number of overall misses +system.iocache.overall_misses::total 252 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 18163419 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 18163419 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1911698102 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1911698102 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 18163419 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 18163419 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 18163419 # number of overall miss cycles +system.iocache.overall_miss_latency::total 18163419 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999199 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999199 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 70333.008032 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 70333.008032 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 54664.294046 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 54664.294046 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 70333.008032 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 70333.008032 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 70333.008032 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 72077.059524 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 72077.059524 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52774.351314 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 52774.351314 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 72077.059524 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 72077.059524 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 72077.059524 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 46 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.217391 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36160 # number of writebacks -system.iocache.writebacks::total 36160 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 148 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 148 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 15187 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 15187 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 148 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 148 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 10112919 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 10112919 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1219224123 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1219224123 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 10112919 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10112919 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 10112919 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10112919 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.594378 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.419252 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.594378 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.594378 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.594378 # mshr miss rate for overall accesses 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+system.iocache.ReadReq_mshr_misses::realview.ide 151 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 15216 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 15216 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 151 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 151 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 151 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 10613419 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10613419 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 1150219969 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1150219969 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 10613419 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10613419 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 10613419 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10613419 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.599206 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.420053 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.420053 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.599206 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.599206 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.599206 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70287.543046 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70287.543046 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75592.795018 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75592.795018 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70287.543046 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70287.543046 # average overall mshr miss latency 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requestor +system.l2c.tags.occ_blocks::cpu1.data 812.278170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 23.892428 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2284.499706 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 774.800315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.745028 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 3338.045671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1675.605011 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.746258 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.064911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.033668 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.010917 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000340 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.012468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.051400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.025955 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993210 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 64 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65188 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 64 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7652 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55293 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994690 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45555294 # Number of tag accesses -system.l2c.tags.data_accesses 45555294 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1745 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 884 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 13470 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 20610 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4601 # number of ReadReq hits -system.l2c.ReadReq_hits::total 48616 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 692230 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 692230 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1942576 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1942576 # number of WritebackClean hits +system.l2c.tags.occ_percent::cpu0.inst 0.066057 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.033737 # Average percentage of cache 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ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 979 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 14517 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 1275 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 20680 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 4699 # number of ReadReq hits +system.l2c.ReadReq_hits::total 50403 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 691780 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 691780 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1950249 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1950249 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 12 # number of UpgradeReq hits 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ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 206624 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 73422 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 102469 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 140144 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 522659 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4129 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 713859 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 272579 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1745 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 884 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 202359 # number of demand (read+write) hits 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of overall hits -system.l2c.overall_hits::cpu0.data 272579 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1745 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 884 # number of overall hits -system.l2c.overall_hits::cpu1.inst 202359 # number of overall hits -system.l2c.overall_hits::cpu1.data 91617 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 13470 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 1127 # number of overall hits -system.l2c.overall_hits::cpu2.inst 496880 # number of overall hits -system.l2c.overall_hits::cpu2.data 129972 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 20610 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 4601 # number of overall hits -system.l2c.overall_hits::cpu3.inst 547040 # number of overall hits -system.l2c.overall_hits::cpu3.data 184835 # number of overall hits -system.l2c.overall_hits::total 2687757 # number of overall hits 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miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.168932 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.011721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.205063 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.035725 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007683 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.139942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002199 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.168932 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.011721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.205063 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035725 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 123240 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68022.471910 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68010.380623 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68008.510638 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 68545.454545 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68545.454545 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 118884.892961 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 117488.101512 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 122473.807083 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120395.867514 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122706.961443 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120180.834002 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 123385.642317 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 127037.237002 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124254.257858 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 119102.893565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 117927.341288 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 122881.844896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121027.546228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121451.735016 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 119102.893565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 123921.875000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 122360.696517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 117927.341288 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 122919.117647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 123289.647699 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 122881.844896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121027.546228 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163716.904277 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 186066.593886 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 203635.875973 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 190212.833764 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165879.440258 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 185338.038109 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201856.695497 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189452.051804 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 164685.250643 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 185748.845799 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 202850.309455 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 189877.258577 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 76341 # Transaction distribution +system.membus.trans_dist::ReadResp 76472 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131541 # Transaction distribution -system.membus.trans_dist::CleanEvict 8827 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4560 # Transaction distribution -system.membus.trans_dist::ReadExReq 138388 # Transaction distribution -system.membus.trans_dist::ReadExResp 138388 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36227 # Transaction distribution -system.membus.trans_dist::InvalidateReq 36194 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36194 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131266 # Transaction distribution +system.membus.trans_dist::CleanEvict 9256 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4564 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1783 # Transaction distribution +system.membus.trans_dist::ReadExReq 138006 # Transaction distribution +system.membus.trans_dist::ReadExResp 138006 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36358 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 21008 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 489795 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 597247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 706160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 486411 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 593863 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 687890 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17309820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17472945 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2320704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19793649 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 304 # Total snoops (count) -system.membus.snoop_fanout::samples 423653 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17273980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17437105 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2322624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2322624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19759729 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 308 # Total snoops (count) +system.membus.snoop_fanout::samples 423370 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 423653 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 423370 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 423653 # Request fanout histogram -system.membus.reqLayer0.occupancy 54148500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 423370 # Request fanout histogram +system.membus.reqLayer0.occupancy 54054500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 680000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 683000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 485362066 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 487802765 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 587517958 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 583127250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 27144297 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 785081 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2905,60 +2896,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5660019 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2844678 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 45590 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 617 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 617 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5675245 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2851889 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 45299 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 358 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 111923 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2630935 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 112467 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2639200 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 761630 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1942576 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 139089 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2842 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 761596 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1988229 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 147548 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2816 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 29 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2870 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296497 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296497 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1981401 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537613 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 15186 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5923303 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617283 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 100543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8667634 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 251163000 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97868601 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43100 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 349252557 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 193970 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4194071 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021768 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.145924 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2845 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296735 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296735 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1988790 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 538004 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 15216 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5983726 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2626321 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26876 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102356 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8739279 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 254557176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97876281 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 183100 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 352660973 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 192738 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4203717 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021388 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144675 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4102776 97.82% 97.82% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 91295 2.18% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4113806 97.86% 97.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 89911 2.14% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4194071 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3475552499 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4203717 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3488536999 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 260919 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 176919 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1890152632 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1898856602 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 768668207 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 770188700 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11579475 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11632976 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 47680705 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 48177210 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index ceb2dbc54..ccb7c08a5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823500 # Number of seconds simulated -sim_ticks 2823500372500 # Number of ticks simulated -final_tick 2823500372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823470 # Number of seconds simulated +sim_ticks 2823469739500 # Number of ticks simulated +final_tick 2823469739500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115105 # Simulator instruction rate (inst/s) -host_op_rate 139706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2779881687 # Simulator tick rate (ticks/s) -host_mem_usage 588972 # Number of bytes of host memory used -host_seconds 1015.69 # Real time elapsed on the host -sim_insts 116911425 # Number of instructions simulated -sim_ops 141898519 # Number of ops (including micro ops) simulated +host_inst_rate 118468 # Simulator instruction rate (inst/s) +host_op_rate 143788 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2861405792 # Simulator tick rate (ticks/s) +host_mem_usage 590036 # Number of bytes of host memory used +host_seconds 986.74 # Real time elapsed on the host +sim_insts 116897717 # Number of instructions simulated +sim_ops 141881589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 3648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 660992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5280544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 712768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4516872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 661824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5279456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 5184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 711040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4517256 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11180968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 660992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 712768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1373760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8429056 # Number of bytes written to this memory +system.physmem.bytes_read::total 11179432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 661824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 711040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1372864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8427776 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8446580 # Number of bytes written to this memory +system.physmem.bytes_written::total 8445300 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 57 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10328 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 83027 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 11137 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 70578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 83010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 81 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70584 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175223 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131704 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175199 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131684 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136085 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136065 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 1292 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 234104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1870212 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 252441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1599742 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 234401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1869847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 251832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1599895 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3959967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 234104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 252441 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 486545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2985321 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3959466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 234401 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 251832 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 486233 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2984900 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6204 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2991528 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2985321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2991107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2984900 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 1292 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 234104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1876416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 252441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1599745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 234401 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1876051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 251832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1599898 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6951495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175224 # Number of read requests accepted -system.physmem.writeReqs 136085 # Number of write requests accepted -system.physmem.readBursts 175224 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136085 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11205440 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue -system.physmem.bytesWritten 8458688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11181032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8446580 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6950573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175200 # Number of read requests accepted +system.physmem.writeReqs 136065 # Number of write requests accepted +system.physmem.readBursts 175200 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136065 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11204096 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8457920 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11179496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8445300 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 49641 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11401 # Per bank write bursts -system.physmem.perBankRdBursts::1 10979 # Per bank write bursts -system.physmem.perBankRdBursts::2 11428 # Per bank write bursts -system.physmem.perBankRdBursts::3 11300 # Per bank write bursts -system.physmem.perBankRdBursts::4 11019 # Per bank write bursts -system.physmem.perBankRdBursts::5 10545 # Per bank write bursts -system.physmem.perBankRdBursts::6 11444 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11402 # Per bank write bursts +system.physmem.perBankRdBursts::1 10980 # Per bank write bursts +system.physmem.perBankRdBursts::2 11431 # Per bank write bursts +system.physmem.perBankRdBursts::3 11297 # Per bank write bursts +system.physmem.perBankRdBursts::4 11015 # Per bank write bursts +system.physmem.perBankRdBursts::5 10541 # Per bank write bursts +system.physmem.perBankRdBursts::6 11443 # Per bank write bursts system.physmem.perBankRdBursts::7 11405 # Per bank write bursts -system.physmem.perBankRdBursts::8 11225 # Per bank write bursts +system.physmem.perBankRdBursts::8 11226 # Per bank write bursts system.physmem.perBankRdBursts::9 11073 # Per bank write bursts -system.physmem.perBankRdBursts::10 10490 # Per bank write bursts -system.physmem.perBankRdBursts::11 10075 # Per bank write bursts -system.physmem.perBankRdBursts::12 10628 # Per bank write bursts -system.physmem.perBankRdBursts::13 11391 # Per bank write bursts -system.physmem.perBankRdBursts::14 10678 # Per bank write bursts -system.physmem.perBankRdBursts::15 10004 # Per bank write bursts -system.physmem.perBankWrBursts::0 8636 # Per bank write bursts -system.physmem.perBankWrBursts::1 8268 # Per bank write bursts -system.physmem.perBankWrBursts::2 8882 # Per bank write bursts -system.physmem.perBankWrBursts::3 8813 # Per bank write bursts -system.physmem.perBankWrBursts::4 7855 # Per bank write bursts -system.physmem.perBankWrBursts::5 7878 # Per bank write bursts -system.physmem.perBankWrBursts::6 8477 # Per bank write bursts -system.physmem.perBankWrBursts::7 8545 # Per bank write bursts -system.physmem.perBankWrBursts::8 8487 # Per bank write bursts -system.physmem.perBankWrBursts::9 8481 # Per bank write bursts -system.physmem.perBankWrBursts::10 7867 # Per bank write bursts -system.physmem.perBankWrBursts::11 7716 # Per bank write bursts -system.physmem.perBankWrBursts::12 8202 # Per bank write bursts -system.physmem.perBankWrBursts::13 8761 # Per bank write bursts +system.physmem.perBankRdBursts::10 10487 # Per bank write bursts +system.physmem.perBankRdBursts::11 10069 # Per bank write bursts +system.physmem.perBankRdBursts::12 10629 # Per bank write bursts +system.physmem.perBankRdBursts::13 11393 # Per bank write bursts +system.physmem.perBankRdBursts::14 10671 # Per bank write bursts +system.physmem.perBankRdBursts::15 10002 # Per bank write bursts +system.physmem.perBankWrBursts::0 8635 # Per bank write bursts +system.physmem.perBankWrBursts::1 8267 # Per bank write bursts +system.physmem.perBankWrBursts::2 8885 # Per bank write bursts +system.physmem.perBankWrBursts::3 8812 # Per bank write bursts +system.physmem.perBankWrBursts::4 7853 # Per bank write bursts +system.physmem.perBankWrBursts::5 7875 # Per bank write bursts +system.physmem.perBankWrBursts::6 8475 # Per bank write bursts +system.physmem.perBankWrBursts::7 8544 # Per bank write bursts +system.physmem.perBankWrBursts::8 8488 # Per bank write bursts +system.physmem.perBankWrBursts::9 8484 # Per bank write bursts +system.physmem.perBankWrBursts::10 7865 # Per bank write bursts +system.physmem.perBankWrBursts::11 7711 # Per bank write bursts +system.physmem.perBankWrBursts::12 8199 # Per bank write bursts +system.physmem.perBankWrBursts::13 8763 # Per bank write bursts system.physmem.perBankWrBursts::14 7974 # Per bank write bursts system.physmem.perBankWrBursts::15 7325 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 2823500194500 # Total gap between requests +system.physmem.totGap 2823469561500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 174668 # Read request sizes (log2) +system.physmem.readPktSize::6 174644 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131704 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 107487 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131684 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 107528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 6570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -162,134 +162,137 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 87 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 299.646471 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.275715 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.864593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24692 37.63% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16213 24.71% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6759 10.30% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3713 5.66% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2878 4.39% 82.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1688 2.57% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1064 1.62% 86.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1117 1.70% 88.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7500 11.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65624 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.331227 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 483.912144 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65621 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 299.627985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.164139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.976570 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24746 37.71% 37.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16151 24.61% 62.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6763 10.31% 72.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3694 5.63% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2894 4.41% 82.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1678 2.56% 85.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1076 1.64% 86.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1118 1.70% 88.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7501 11.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65621 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6504 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.912515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 489.223467 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6502 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.880716 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.279022 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.177011 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 14 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6504 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6504 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.319034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.351442 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.828317 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 14 0.22% 0.22% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4-7 3 0.05% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 5 0.08% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 11 0.17% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5692 85.62% 86.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 171 2.57% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 60 0.90% 89.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 185 2.78% 92.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 34 0.51% 92.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 150 2.26% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 50 0.75% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.15% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 23 0.35% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.29% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.11% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 143 2.15% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.11% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.30% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads -system.physmem.totQLat 2744374251 # Total ticks spent queuing -system.physmem.totMemAccLat 6027218001 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 875425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15674.53 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::8-11 6 0.09% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.15% 0.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5684 87.39% 87.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 2.29% 90.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 43 0.66% 90.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 73 1.12% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 39 0.60% 92.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.32% 92.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 44 0.68% 93.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.12% 93.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 147 2.26% 95.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 14 0.22% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.15% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.25% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 67 1.03% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 97.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 97.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 29 0.45% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 91 1.40% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 3 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.11% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6504 # Writes before turning the bus around for reads +system.physmem.totQLat 2746267751 # Total ticks spent queuing +system.physmem.totMemAccLat 6028717751 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 875320000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15687.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34424.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34437.22 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.97 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.96 # Average system read bandwidth in MiByte/s @@ -299,40 +302,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.46 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.80 # Average write queue length when enqueuing -system.physmem.readRowHits 144084 # Number of row buffer hits during reads -system.physmem.writeRowHits 97542 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.78 # Row buffer hit rate for writes -system.physmem.avgGap 9069767.32 # Average gap between requests +system.physmem.avgWrQLen 12.82 # Average write queue length when enqueuing +system.physmem.readRowHits 144099 # Number of row buffer hits during reads +system.physmem.writeRowHits 97497 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.76 # Row buffer hit rate for writes +system.physmem.avgGap 9070951.00 # Average gap between requests system.physmem.pageHitRate 78.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 256420080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 139911750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698263800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 436453920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184417078560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80050894335 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1623878080500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1889877102945 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.339172 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2701352401000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94282760000 # Time in different power states +system.physmem_0.actEnergy 256253760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139821000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 698209200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 436402080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184415044320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80123978880 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1623795284250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1889864993490 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.342266 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2701214527000 # Time in different power states +system.physmem_0.memoryStateTime::REF 94281720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27861791500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27969560500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 239697360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 130787250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 667383600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 419988240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184417078560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79252079805 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1624578795000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1889705809815 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.278505 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2702525049250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94282760000 # Time in different power states +system.physmem_1.actEnergy 239841000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130865625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 667274400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 419962320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184415044320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79167823830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1624634016750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1889674828245 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.274915 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2702617863750 # Time in different power states +system.physmem_1.memoryStateTime::REF 94281720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26691828250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26569403250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory @@ -352,14 +355,14 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 26559789 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13713833 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 501635 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 15976864 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12419776 # Number of BTB hits +system.cpu0.branchPred.lookups 26557765 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13711788 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 500128 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 15985074 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12420856 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.736006 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6636189 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 77.702837 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6637719 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 27705 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -391,88 +394,87 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 56617 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 56617 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17206 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13819 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 25592 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 31025 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 854.665592 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 5277.318433 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-16383 30569 98.53% 98.53% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-32767 316 1.02% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-49151 76 0.24% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 56410 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 56410 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 17224 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 13674 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 25512 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 30898 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 845.750534 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 5234.094520 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 30449 98.55% 98.55% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 313 1.01% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 71 0.23% 99.79% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::49152-65535 28 0.09% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-81919 17 0.05% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-98303 4 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 18 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.95% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-147455 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::114688-131071 5 0.02% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 31025 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12676 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13504.851688 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 10947.656823 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 9228.518750 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 9308 73.43% 73.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3112 24.55% 97.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 228 1.80% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 10 0.08% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-81919 2 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 13 0.10% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12676 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 91900678744 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.634073 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.504786 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 91817596744 99.91% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 56432500 0.06% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 12685500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 5058000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2486500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1667000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 978500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 2452500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 399500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 440000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 77000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 47000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 115000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 31000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 185500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 91900678744 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3474 69.04% 69.04% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1558 30.96% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5032 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56617 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 30898 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 12695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13609.491926 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11056.421088 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 9278.462681 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 9267 73.00% 73.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 3157 24.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 251 1.98% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 12 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::147456-163839 3 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 12695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 96164849040 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.577862 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.515354 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 96082852540 99.91% 99.91% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 55229500 0.06% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 12746000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 5020500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2459000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1673000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1038500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 2619500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 401000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 384500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-21 78000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::22-23 35000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-25 82500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::26-27 33000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-29 25000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::30-31 171500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 96164849040 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3408 68.65% 68.65% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1556 31.35% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4964 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 56410 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56617 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5032 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 56410 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4964 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5032 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 61649 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4964 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 61374 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 13956888 # DTB read hits -system.cpu0.dtb.read_misses 47161 # DTB read misses -system.cpu0.dtb.write_hits 10502014 # DTB write hits -system.cpu0.dtb.write_misses 9456 # DTB write misses +system.cpu0.dtb.read_hits 13949693 # DTB read hits +system.cpu0.dtb.read_misses 47052 # DTB read misses +system.cpu0.dtb.write_hits 10497167 # DTB write hits +system.cpu0.dtb.write_misses 9358 # DTB write misses system.cpu0.dtb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 469 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3284 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 763 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1265 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3271 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 792 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1257 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 602 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14004049 # DTB read accesses -system.cpu0.dtb.write_accesses 10511470 # DTB write accesses +system.cpu0.dtb.perms_faults 589 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 13996745 # DTB read accesses +system.cpu0.dtb.write_accesses 10506525 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24458902 # DTB hits -system.cpu0.dtb.misses 56617 # DTB misses -system.cpu0.dtb.accesses 24515519 # DTB accesses +system.cpu0.dtb.hits 24446860 # DTB hits +system.cpu0.dtb.misses 56410 # DTB misses +system.cpu0.dtb.accesses 24503270 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -502,207 +504,210 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 7529 # Table walker walks requested -system.cpu0.itb.walker.walksShort 7529 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2281 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5094 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 154 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 7375 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1792 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 7463.239883 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-16383 7070 95.86% 95.86% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-32767 234 3.17% 99.04% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-49151 37 0.50% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-65535 16 0.22% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-81919 7 0.09% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::81920-98303 5 0.07% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-114687 1 0.01% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::114688-131071 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-147455 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 7375 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2396 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13984.557596 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11758.733193 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 8144.466175 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 1749 73.00% 73.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 606 25.29% 98.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 39 1.63% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2396 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 23180931508 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.845594 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.362375 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3585102000 15.47% 15.47% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 19591754508 84.52% 99.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 3051000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 602000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 249500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 124500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 23180931508 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1680 74.93% 74.93% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 562 25.07% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2242 # Table walker page sizes translated +system.cpu0.itb.walker.walks 7368 # Table walker walks requested +system.cpu0.itb.walker.walksShort 7368 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 2261 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 4959 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 148 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 7220 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1816.274238 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 7833.781399 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-16383 6926 95.93% 95.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-32767 219 3.03% 98.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-49151 37 0.51% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-65535 15 0.21% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-81919 11 0.15% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::81920-98303 3 0.04% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-114687 3 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::114688-131071 3 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-147455 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::147456-163839 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 7220 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2362 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 14046.570703 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11793.338706 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 8758.063441 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 1730 73.24% 73.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 589 24.94% 98.18% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 40 1.69% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2362 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 14560346416 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.888625 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.316568 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1627388500 11.18% 11.18% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 12929178416 88.80% 99.97% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2653000 0.02% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 688000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 200500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 118000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 93000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::7 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 14560346416 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1654 74.71% 74.71% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 560 25.29% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2214 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7529 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7529 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 7368 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 7368 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2242 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2242 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 9771 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20127989 # ITB inst hits -system.cpu0.itb.inst_misses 7529 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2214 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2214 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 9582 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20130827 # ITB inst hits +system.cpu0.itb.inst_misses 7368 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 179 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 479 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 469 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2165 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2134 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1248 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1230 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20135518 # ITB inst accesses -system.cpu0.itb.hits 20127989 # DTB hits -system.cpu0.itb.misses 7529 # DTB misses -system.cpu0.itb.accesses 20135518 # DTB accesses -system.cpu0.numCycles 111773750 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20138195 # ITB inst accesses +system.cpu0.itb.hits 20130827 # DTB hits +system.cpu0.itb.misses 7368 # DTB misses +system.cpu0.itb.accesses 20138195 # DTB accesses +system.cpu0.numCycles 111738620 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 39404734 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 103901347 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 26559789 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19055965 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 67172503 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3105480 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 123475 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 4254 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 446 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 188702 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 117718 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 813 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20126932 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 348923 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3603 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 108565347 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.150440 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.270106 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39370893 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 103893622 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26557765 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19058575 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 67178812 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3103708 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 121878 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4445 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 455 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 181503 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 118118 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 630 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20129808 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 348342 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3505 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 108528550 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.150700 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.270125 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 80009058 73.70% 73.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3809201 3.51% 77.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2394359 2.21% 79.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 7998409 7.37% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1537996 1.42% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1087909 1.00% 89.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6040532 5.56% 94.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1033019 0.95% 95.71% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4654864 4.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 79971422 73.69% 73.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3809838 3.51% 77.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2395726 2.21% 79.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8000248 7.37% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1536985 1.42% 88.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1087405 1.00% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6042952 5.57% 94.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1032695 0.95% 95.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4651279 4.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 108565347 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.237621 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.929568 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26883025 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 63349855 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15403629 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1519503 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1408994 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1872503 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 145749 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 86293156 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 470873 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1408994 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 27735944 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6700023 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 45856628 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16066730 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10796686 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 82579979 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2391 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1108634 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 252112 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 8668459 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 84779937 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 381537510 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 92587970 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5626 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72263854 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12516075 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1563295 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1465928 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8829402 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 14730052 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11675597 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 2115179 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2832097 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 79532292 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1117477 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 76533618 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 87406 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10386047 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23162950 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 102669 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 108565347 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.704954 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.405780 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 108528550 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.237678 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.929792 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26850691 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 63349616 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15400515 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1518743 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1408634 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1870918 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 145274 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 86265723 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 468688 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1408634 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 27702966 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6709898 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 45858480 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16063551 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10784636 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 82553580 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2255 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1112646 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 250108 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8658376 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 84742438 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 381431947 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 92563624 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5398 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72236094 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12506336 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1563816 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1466607 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8828288 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14723258 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11669783 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 2112846 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2835315 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 79509095 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1118195 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 76512604 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87402 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10382395 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23148584 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 102807 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 108528550 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.705000 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.405850 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 77871483 71.73% 71.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10453105 9.63% 81.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7708495 7.10% 88.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6443405 5.94% 94.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2343404 2.16% 96.55% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1520676 1.40% 97.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1477584 1.36% 99.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 486752 0.45% 99.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 260443 0.24% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 77845712 71.73% 71.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10446148 9.63% 81.35% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7706696 7.10% 88.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6443833 5.94% 94.39% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2340710 2.16% 96.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1522105 1.40% 97.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1475778 1.36% 99.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 487012 0.45% 99.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 260556 0.24% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 108565347 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 108528550 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 112393 9.83% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 527099 46.11% 55.94% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 503655 44.06% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112196 9.79% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 526196 45.92% 55.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 507404 44.28% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 225 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 50981056 66.61% 66.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 56862 0.07% 66.69% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 229 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 50972770 66.62% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 56817 0.07% 66.69% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.69% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued @@ -726,576 +731,576 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4067 0.01% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14347373 18.75% 85.44% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 11144026 14.56% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4037 0.01% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14339886 18.74% 85.44% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 11138856 14.56% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 76533618 # Type of FU issued -system.cpu0.iq.rate 0.684719 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1143148 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014937 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 262850677 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91081899 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 74283043 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12460 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6644 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5511 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 77669867 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6674 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 356195 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 76512604 # Type of FU issued +system.cpu0.iq.rate 0.684746 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1145797 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014975 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 262775124 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91056518 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 74263785 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11833 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6292 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5221 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 77651808 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6364 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 356016 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1995192 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2360 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53884 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1081117 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1994121 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2352 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54275 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1081195 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 202683 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 121039 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 202898 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 121276 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1408994 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5274240 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1210190 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 80780073 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 118682 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 14730052 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11675597 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571348 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 46022 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1152002 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53884 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 221496 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 202557 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 424053 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 75976302 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14126659 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 500836 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1408634 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5278024 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1213431 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80756832 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 118260 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14723258 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11669783 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571666 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 45870 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1155376 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54275 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 221116 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 201841 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 422957 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 75956383 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14119834 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 499950 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 130304 # number of nop insts executed -system.cpu0.iew.exec_refs 25168197 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14063788 # Number of branches executed -system.cpu0.iew.exec_stores 11041538 # Number of stores executed -system.cpu0.iew.exec_rate 0.679733 # Inst execution rate -system.cpu0.iew.wb_sent 75420123 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 74288554 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 38930485 # num instructions producing a value -system.cpu0.iew.wb_consumers 68286780 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.664633 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.570103 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10422530 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1014808 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 357851 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 106167071 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.662547 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.559914 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 129542 # number of nop insts executed +system.cpu0.iew.exec_refs 25156609 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14059078 # Number of branches executed +system.cpu0.iew.exec_stores 11036775 # Number of stores executed +system.cpu0.iew.exec_rate 0.679768 # Inst execution rate +system.cpu0.iew.wb_sent 75400529 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 74269006 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38924107 # num instructions producing a value +system.cpu0.iew.wb_consumers 68260827 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.664667 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.570226 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10419079 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1015388 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 356870 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 106130883 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.662591 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560067 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 78816600 74.24% 74.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12394656 11.67% 85.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6095585 5.74% 91.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2659364 2.50% 94.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1364551 1.29% 95.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 834490 0.79% 96.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1723865 1.62% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 420734 0.40% 98.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1857226 1.75% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 78790716 74.24% 74.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12390417 11.67% 85.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6092521 5.74% 91.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2656832 2.50% 94.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1363229 1.28% 95.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 834290 0.79% 96.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1725699 1.63% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 420589 0.40% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1856590 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 106167071 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57989505 # Number of instructions committed -system.cpu0.commit.committedOps 70340708 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 106130883 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57976816 # Number of instructions committed +system.cpu0.commit.committedOps 70321358 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23329340 # Number of memory references committed -system.cpu0.commit.loads 12734860 # Number of loads committed -system.cpu0.commit.membars 416180 # Number of memory barriers committed -system.cpu0.commit.branches 13372532 # Number of branches committed -system.cpu0.commit.fp_insts 5482 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61754724 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2627334 # Number of function calls committed. +system.cpu0.commit.refs 23317725 # Number of memory references committed +system.cpu0.commit.loads 12729137 # Number of loads committed +system.cpu0.commit.membars 416530 # Number of memory barriers committed +system.cpu0.commit.branches 13368661 # Number of branches committed +system.cpu0.commit.fp_insts 5158 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61739692 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2627704 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46951986 66.75% 66.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55316 0.08% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4066 0.01% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12734860 18.10% 84.94% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10594480 15.06% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46944316 66.76% 66.76% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55281 0.08% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4036 0.01% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.84% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12729137 18.10% 84.94% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10588588 15.06% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70340708 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1857226 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 172725039 # The number of ROB reads -system.cpu0.rob.rob_writes 163928651 # The number of ROB writes -system.cpu0.timesIdled 382167 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3208403 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2095470503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57912515 # Number of Instructions Simulated -system.cpu0.committedOps 70263718 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.930045 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.930045 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.518123 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.518123 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 82944906 # number of integer regfile reads -system.cpu0.int_regfile_writes 47313800 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16399 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13366 # number of floating regfile writes -system.cpu0.cc_regfile_reads 268363191 # number of cc regfile reads -system.cpu0.cc_regfile_writes 27733780 # number of cc regfile writes -system.cpu0.misc_regfile_reads 150032753 # number of misc regfile reads -system.cpu0.misc_regfile_writes 778510 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 855432 # number of replacements +system.cpu0.commit.op_class_0::total 70321358 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1856590 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 172663195 # The number of ROB reads +system.cpu0.rob.rob_writes 163882503 # The number of ROB writes +system.cpu0.timesIdled 381139 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3210070 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2095442854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 57900349 # Number of Instructions Simulated +system.cpu0.committedOps 70244891 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.929844 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.929844 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.518177 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.518177 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 82925717 # number of integer regfile reads +system.cpu0.int_regfile_writes 47305162 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16275 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13170 # number of floating regfile writes +system.cpu0.cc_regfile_reads 268288985 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27711504 # number of cc regfile writes +system.cpu0.misc_regfile_reads 149937912 # number of misc regfile reads +system.cpu0.misc_regfile_writes 778798 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 855446 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.968774 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42360074 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 855944 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.489305 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 42352962 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 855958 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.480187 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 186702500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 250.285909 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 261.682865 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.488840 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.511099 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 248.778719 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 263.190055 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.485896 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.514043 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999939 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189283631 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189283631 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12299336 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12887121 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25186457 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7940771 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 7960315 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15901086 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 183903 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180299 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 364202 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230031 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215903 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 445934 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236508 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 222797 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459305 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20240107 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20847436 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41087543 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20424010 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21027735 # number of overall hits -system.cpu0.dcache.overall_hits::total 41451745 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 436616 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 404052 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 840668 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1879075 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1817736 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3696811 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 117503 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 66969 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 184472 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13695 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14214 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27909 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 35 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 35 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 70 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2315691 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2221788 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4537479 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2433194 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2288757 # number of overall misses -system.cpu0.dcache.overall_misses::total 4721951 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7223531500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 7393293500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14616825000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137673616868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 114952576008 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 252626192876 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 218177000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 196691000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 414868000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 902000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 1175500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 2077500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 144897148368 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 122345869508 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 267243017876 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 144897148368 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 122345869508 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 267243017876 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 12735952 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13291173 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26027125 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9819846 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9778051 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19597897 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 301406 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 189257101 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189257101 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12292677 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12889220 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25181897 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7937758 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 7960928 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15898686 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184092 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180023 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 364115 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230395 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215508 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 445903 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236843 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 222450 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459293 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20230435 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20850148 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41080583 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20414527 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21030171 # number of overall hits +system.cpu0.dcache.overall_hits::total 41444698 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 435537 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 405293 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 840830 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1875767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1821477 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3697244 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 117122 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 67245 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 184367 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13669 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14208 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27877 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 34 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 32 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 66 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2311304 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2226770 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4538074 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2428426 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2294015 # number of overall misses +system.cpu0.dcache.overall_misses::total 4722441 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7243575000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 7414080000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14657655000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137609322451 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 115018271250 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 252627593701 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 217997500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 196866000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 414863500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 871500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 1111000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 1982500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 144852897451 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 122432351250 # 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accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 301214 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 247268 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 548674 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 243726 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 230117 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 473843 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236543 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 222832 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459375 # number of StoreCondReq accesses(hits+misses) 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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1140500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2007500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14534074885 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 13243056960 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 27777131845 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15648958385 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 13996744460 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 29645702845 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2963039000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3337977000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6301016000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2592772424 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2491429952 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5084202376 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5555811424 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5829406952 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11385218376 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016425 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016375 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016399 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015446 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015140 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015294 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.246170 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.197749 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224348 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019341 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019268 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019306 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000148 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000157 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000152 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015999 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015852 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015924 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019034 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017781 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018401 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15925.201857 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15565.667959 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15741.869733 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73858.078751 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66569.536489 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70258.016859 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15025.991617 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15413.777941 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15180.033145 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19906.024608 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13498.421290 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16800.284215 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24771.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 32585.714286 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 28678.571429 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40275.880002 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36213.690647 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38231.285787 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35969.655645 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33760.530212 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34891.705687 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200843.150546 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203833.475818 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202416.267789 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170285.854722 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201539.391037 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.357257 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185323.440542 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202846.647366 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193899.865048 # average overall mshr uncacheable latency +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3332077500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 3393296500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6725374000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11184886384 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9853624962 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21038511346 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1108891500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 759475500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1868367000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93281500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 59417500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 152699000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 837500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 1079000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1916500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 14516963884 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 13246921462 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 27763885346 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15625855384 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 14006396962 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 29632252346 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2963964500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3337097500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6301062000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2593528424 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2490666452 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5084194876 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5557492924 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5827763952 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11385256876 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016407 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016405 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016406 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015425 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015159 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015293 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.245410 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.199063 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224516 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019130 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019137 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019133 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000144 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000144 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000144 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015980 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015877 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.015928 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019005 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017819 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018406 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15955.398229 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15559.085428 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15752.946633 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 73887.132767 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 66446.999939 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70205.363035 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15001.034889 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15429.594490 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15172.336227 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 19978.903405 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13516.264786 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16844.897959 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24632.352941 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 33718.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 29037.878788 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 40300.831126 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 36155.840490 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38210.739825 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35992.996167 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 33701.142337 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 34872.058044 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200824.208957 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 203854.459377 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 202417.745511 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170279.589259 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 201559.152869 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184290.085399 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 185311.534645 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 202867.126814 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193900.520735 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1935670 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.471469 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 38837356 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1936182 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.058732 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1935383 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.471478 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 38825027 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1935895 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.055337 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 11154875500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 205.076991 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 306.394478 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.400541 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.598427 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 204.816833 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 306.654644 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.400033 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.598935 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998968 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42857903 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42857903 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19118560 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19718796 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 38837356 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19118560 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19718796 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 38837356 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19118560 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19718796 # number of overall hits -system.cpu0.icache.overall_hits::total 38837356 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1007700 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1076592 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2084292 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1007700 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1076592 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2084292 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1007700 # number of overall misses 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accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.051771 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050934 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050069 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.051771 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050934 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050069 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.051771 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050934 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14185.174135 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14305.847050 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14247.504890 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14185.174135 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14305.847050 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14247.504890 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14185.174135 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14305.847050 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14247.504890 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 21497 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 42844828 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 42844828 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19123752 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19701275 # number of ReadReq hits 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of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 15427948989 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 29697575471 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20129136 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20779730 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 40908866 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20129136 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20779730 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 40908866 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20129136 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20779730 # number of overall (read+write) accesses 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838 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 793 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.652745 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.484237 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1935670 # number of writebacks -system.cpu0.icache.writebacks::total 1935670 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71379 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 76657 # number of ReadReq MSHR hits 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MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 934069 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 1001894 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1935963 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 668 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 668 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 668 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 668 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12542067979 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13487008993 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 26029076972 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12542067979 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13487008993 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 26029076972 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12542067979 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13487008993 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 26029076972 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12517523985 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 13510096493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 26027620478 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12517523985 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 13510096493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 26027620478 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12517523985 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 13510096493 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 26027620478 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 86506500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 86506500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 86506500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 86506500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046522 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048084 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047316 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046522 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048084 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047316 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046522 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048084 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047316 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13395.051461 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13487.885706 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13442.993577 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13395.051461 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13487.885706 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13442.993577 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13395.051461 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13487.885706 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13442.993577 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.046404 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.048215 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047324 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.046404 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.048215 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047324 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.046404 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.048215 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047324 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13401.069926 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13484.556743 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13444.275783 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13401.069926 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13484.556743 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13444.275783 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13401.069926 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13484.556743 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13444.275783 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 129500.748503 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 129500.748503 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 129500.748503 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27854639 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14561380 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 548025 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17333975 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 13131194 # Number of BTB hits +system.cpu1.branchPred.lookups 27845769 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14562032 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 548670 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17327416 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 13125788 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.754084 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6850254 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29025 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 75.751560 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6844508 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29088 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1325,85 +1330,86 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 58019 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58019 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19126 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13648 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25245 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 32774 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 718.053945 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 4822.223013 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-16383 32332 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-32767 325 0.99% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-49151 64 0.20% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-65535 24 0.07% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-81919 11 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-114687 5 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::114688-131071 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 58263 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58263 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19122 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13746 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 25395 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 32868 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 735.822076 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 5166.451241 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 32439 98.69% 98.69% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 307 0.93% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 56 0.17% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 28 0.09% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 13 0.04% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-98303 5 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-114687 7 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::114688-131071 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-147455 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::147456-163839 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 32774 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 13276 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 14765.931003 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 12384.741759 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8664.538551 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 12938 97.45% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 331 2.49% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 4 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::total 32868 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 13303 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 14575.358942 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 12191.227269 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8603.178174 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 12998 97.71% 97.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 295 2.22% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 7 0.05% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 13276 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 91470687244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.764325 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.447298 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 91383080744 99.90% 99.90% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 61332500 0.07% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 13710000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 4721500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 2367000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1504000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 818000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 2160000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 464000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 210500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 81000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 75000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 60500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 18500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 69500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 91470687244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3730 68.50% 68.50% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1715 31.50% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5445 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58019 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 13303 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 91468436244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.768300 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.445212 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 91380739744 99.90% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 61381000 0.07% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 13682000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 4674500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 2423500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1725000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 730000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 2073000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 390500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 252000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 85000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 127500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 26000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 16000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 87500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 91468436244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3764 68.66% 68.66% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1718 31.34% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5482 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58263 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58019 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5445 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58263 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5482 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5445 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 63464 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5482 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 63745 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14422648 # DTB read hits -system.cpu1.dtb.read_misses 50091 # DTB read misses -system.cpu1.dtb.write_hits 10474825 # DTB write hits -system.cpu1.dtb.write_misses 7928 # DTB write misses +system.cpu1.dtb.read_hits 14429074 # DTB read hits +system.cpu1.dtb.read_misses 50206 # DTB read misses +system.cpu1.dtb.write_hits 10478740 # DTB write hits +system.cpu1.dtb.write_misses 8057 # DTB write misses system.cpu1.dtb.flush_tlb 185 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 448 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3615 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 797 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1273 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3590 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 793 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1278 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14472739 # DTB read accesses -system.cpu1.dtb.write_accesses 10482753 # DTB write accesses +system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14479280 # DTB read accesses +system.cpu1.dtb.write_accesses 10486797 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 24897473 # DTB hits -system.cpu1.dtb.misses 58019 # DTB misses -system.cpu1.dtb.accesses 24955492 # DTB accesses +system.cpu1.dtb.hits 24907814 # DTB hits +system.cpu1.dtb.misses 58263 # DTB misses +system.cpu1.dtb.accesses 24966077 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1433,381 +1439,381 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7961 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7961 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2709 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5049 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 203 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7758 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1605.503996 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 7035.957070 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 7284 93.89% 93.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 191 2.46% 96.35% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 155 2.00% 98.35% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 42 0.54% 98.89% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 32 0.41% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 13 0.17% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 14 0.18% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 8 0.10% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::73728-81919 4 0.05% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 5 0.06% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::90112-98303 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-106495 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7758 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2633 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 14904.291682 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12612.038197 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 8468.527051 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1843 70.00% 70.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 736 27.95% 97.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-49151 45 1.71% 99.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-65535 6 0.23% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::81920-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2633 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 35622983396 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.863018 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.344487 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 4885377500 13.71% 13.71% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 30733731396 86.28% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2597000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 833500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 365000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 79000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 35622983396 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1847 76.01% 76.01% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 583 23.99% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2430 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7966 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7966 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2733 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5041 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 192 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7774 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1441.214304 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6187.766292 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7329 94.28% 94.28% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 184 2.37% 96.64% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 160 2.06% 98.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 32 0.41% 99.11% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 22 0.28% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 15 0.19% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 13 0.17% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 10 0.13% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 5 0.06% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 2 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7774 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2664 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 14886.824324 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12507.436482 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 8471.321316 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 630 23.65% 23.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1227 46.06% 69.71% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 650 24.40% 94.11% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 95 3.57% 97.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 18 0.68% 98.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 35 1.31% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.15% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 3 0.11% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2664 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 31323904600 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.850464 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.357128 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 4688399000 14.97% 14.97% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 26632295600 85.02% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2300000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 720500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 157500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 32000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 31323904600 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1884 76.21% 76.21% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 588 23.79% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2472 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7961 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7961 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7966 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7966 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2430 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 10391 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20797463 # ITB inst hits -system.cpu1.itb.inst_misses 7961 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2472 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2472 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10438 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20781807 # ITB inst hits +system.cpu1.itb.inst_misses 7966 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 185 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 438 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 448 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2393 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2418 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1472 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1467 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20805424 # ITB inst accesses -system.cpu1.itb.hits 20797463 # DTB hits -system.cpu1.itb.misses 7961 # DTB misses -system.cpu1.itb.accesses 20805424 # DTB accesses -system.cpu1.numCycles 114307464 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20789773 # ITB inst accesses +system.cpu1.itb.hits 20781807 # DTB hits +system.cpu1.itb.misses 7966 # DTB misses +system.cpu1.itb.accesses 20789773 # DTB accesses +system.cpu1.numCycles 114304919 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 41243432 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 107322713 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27854639 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19981448 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 67441487 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3261241 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 132708 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 6649 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 428 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 247804 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 128164 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20795394 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 377977 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3632 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 110831676 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.164555 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.274676 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 41262739 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 107285498 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27845769 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19970296 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 67416194 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3259780 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 133608 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 6817 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 414 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 250513 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129856 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 415 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20779736 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 377856 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3597 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 110830408 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.164170 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.274550 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 81234051 73.29% 73.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3972250 3.58% 76.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2466525 2.23% 79.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8240157 7.43% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1682835 1.52% 88.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1118017 1.01% 89.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6328104 5.71% 94.78% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1164123 1.05% 95.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4625614 4.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 81247279 73.31% 73.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3969752 3.58% 76.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2463714 2.22% 79.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8233608 7.43% 86.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1683058 1.52% 88.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1119193 1.01% 89.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6323043 5.71% 94.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1165134 1.05% 95.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4625627 4.17% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 110831676 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.243682 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.938895 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 28301754 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 63497891 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15850723 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1704776 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1476204 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1967399 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 156467 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89087170 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 506464 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1476204 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 29234593 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 7013474 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 46686266 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16610559 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 9810257 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85239039 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4158 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1678441 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 295156 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 7089576 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88402024 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 391987455 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 94729150 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6205 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 74414781 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13987243 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1570718 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1473274 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9797771 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15295971 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11557906 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2126909 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2757513 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82041945 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1095184 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78547336 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91731 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 11502328 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25183489 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 115903 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 110831676 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.708708 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.399992 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 110830408 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.243610 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.938590 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 28323614 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 63478712 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15848046 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1704488 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1475224 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1967997 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 156746 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89079205 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 507140 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1475224 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 29256624 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 7018147 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46666766 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16607219 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 9806111 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85232877 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3842 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1674461 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 301333 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 7083529 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88409572 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 391941986 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 94718838 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6483 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 74424798 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13984774 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1569429 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1471935 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9797660 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15298042 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11560096 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2146916 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2735796 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82036026 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1094252 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78550725 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 92381 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 11493580 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25147781 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 115638 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 110830408 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.708747 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.399658 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 79311031 71.56% 71.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10467239 9.44% 81.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8143760 7.35% 88.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6716432 6.06% 94.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2458249 2.22% 96.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1495385 1.35% 97.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1551990 1.40% 99.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 479300 0.43% 99.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 208290 0.19% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 79265861 71.52% 71.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10536379 9.51% 81.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8138054 7.34% 88.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6692872 6.04% 94.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2461657 2.22% 96.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1496595 1.35% 97.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1550739 1.40% 99.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 480423 0.43% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 207828 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 110831676 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 110830408 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 101407 9.05% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 6 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 524965 46.83% 55.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 494582 44.12% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 101678 9.04% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.04% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 527402 46.88% 55.91% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 496001 44.09% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 2112 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52635037 67.01% 67.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59537 0.08% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4516 0.01% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14823039 18.87% 85.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11023089 14.03% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2108 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52628627 67.00% 67.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59575 0.08% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 2 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4540 0.01% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14828760 18.88% 85.96% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11027108 14.04% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78547336 # Type of FU issued -system.cpu1.iq.rate 0.687158 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1120960 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014271 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 269124936 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 94683536 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76208716 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14103 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7328 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6023 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79658545 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7639 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 355195 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78550725 # Type of FU issued +system.cpu1.iq.rate 0.687203 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1125087 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014323 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 269134534 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94666903 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76208953 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14792 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7758 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6343 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79665710 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7994 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 356293 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2229396 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2459 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 52609 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1115131 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2229171 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2454 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 52006 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1113437 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 209977 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 80421 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 210295 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 83250 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1476204 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5662909 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1045252 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 83270672 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132429 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15295971 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11557906 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 563484 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 44736 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 987233 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 52609 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 252467 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 221077 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 473544 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 77944038 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14582258 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 545399 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1475224 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5653041 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1062018 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83263917 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132733 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15298042 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11560096 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 563089 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 44760 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1004107 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 52006 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 252720 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 221535 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 474255 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 77947224 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14588142 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 545356 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 133543 # number of nop insts executed -system.cpu1.iew.exec_refs 25500080 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14792660 # Number of branches executed -system.cpu1.iew.exec_stores 10917822 # Number of stores executed -system.cpu1.iew.exec_rate 0.681881 # Inst execution rate -system.cpu1.iew.wb_sent 77398935 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76214739 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39907228 # num instructions producing a value -system.cpu1.iew.wb_consumers 69371500 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.666752 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575268 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 11478700 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 979281 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 393571 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 108251137 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.662466 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.546689 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 133639 # number of nop insts executed +system.cpu1.iew.exec_refs 25509801 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14792912 # Number of branches executed +system.cpu1.iew.exec_stores 10921659 # Number of stores executed +system.cpu1.iew.exec_rate 0.681924 # Inst execution rate +system.cpu1.iew.wb_sent 77399015 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76215296 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39901204 # num instructions producing a value +system.cpu1.iew.wb_consumers 69370380 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.666772 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575191 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 11469424 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 978614 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 393966 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 108251669 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.662485 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.545489 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 80272291 74.15% 74.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12448333 11.50% 85.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6524108 6.03% 91.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2657086 2.45% 94.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1374916 1.27% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 919571 0.85% 96.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1942028 1.79% 98.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 407210 0.38% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1705594 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 80229014 74.11% 74.11% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12491692 11.54% 85.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6522560 6.03% 91.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2655731 2.45% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1400574 1.29% 95.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 922085 0.85% 96.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1916585 1.77% 98.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 408524 0.38% 98.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1704904 1.57% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 108251137 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59076825 # Number of instructions committed -system.cpu1.commit.committedOps 71712716 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 108251669 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59075806 # Number of instructions committed +system.cpu1.commit.committedOps 71715136 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23509350 # Number of memory references committed -system.cpu1.commit.loads 13066575 # Number of loads committed -system.cpu1.commit.membars 397868 # Number of memory barriers committed -system.cpu1.commit.branches 14004120 # Number of branches committed -system.cpu1.commit.fp_insts 5946 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 62678118 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2708748 # Number of function calls committed. +system.cpu1.commit.refs 23515530 # Number of memory references committed +system.cpu1.commit.loads 13068871 # Number of loads committed +system.cpu1.commit.membars 397484 # Number of memory barriers committed +system.cpu1.commit.branches 14003876 # Number of branches committed +system.cpu1.commit.fp_insts 6270 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 62677784 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2707088 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48141082 67.13% 67.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57769 0.08% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4515 0.01% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 13066575 18.22% 85.44% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10442775 14.56% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48137267 67.12% 67.12% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57800 0.08% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4539 0.01% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.21% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13068871 18.22% 85.43% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10446659 14.57% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71712716 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1705594 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 176973973 # The number of ROB reads -system.cpu1.rob.rob_writes 168967567 # The number of ROB writes -system.cpu1.timesIdled 411783 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 3475788 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3325418218 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 58998910 # Number of Instructions Simulated -system.cpu1.committedOps 71634801 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.937450 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.937450 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.516142 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.516142 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84572142 # number of integer regfile reads -system.cpu1.int_regfile_writes 48524924 # number of integer regfile writes -system.cpu1.fp_regfile_reads 17041 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13376 # number of floating regfile writes -system.cpu1.cc_regfile_reads 275577121 # number of cc regfile reads -system.cpu1.cc_regfile_writes 29280900 # number of cc regfile writes -system.cpu1.misc_regfile_reads 152549282 # number of misc regfile reads -system.cpu1.misc_regfile_writes 741444 # number of misc regfile writes +system.cpu1.commit.op_class_0::total 71715136 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1704904 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 176979703 # The number of ROB reads +system.cpu1.rob.rob_writes 168952003 # The number of ROB writes +system.cpu1.timesIdled 412631 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 3474511 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3325420537 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 58997368 # Number of Instructions Simulated +system.cpu1.committedOps 71636698 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.937458 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.937458 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.516140 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.516140 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84576354 # number of integer regfile reads +system.cpu1.int_regfile_writes 48518132 # number of integer regfile writes +system.cpu1.fp_regfile_reads 17186 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13576 # number of floating regfile writes +system.cpu1.cc_regfile_reads 275590302 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29300189 # number of cc regfile writes +system.cpu1.misc_regfile_reads 152556946 # number of misc regfile reads +system.cpu1.misc_regfile_writes 741089 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30172 # Transaction distribution system.iobus.trans_dist::ReadResp 30172 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1858,11 +1864,11 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321016 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480141 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 49495000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 49499000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 100500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1870,7 +1876,7 @@ system.iobus.reqLayer4.occupancy 12000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 86000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 613000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1892,25 +1898,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6442000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6444000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38187000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38197000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186272549 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187138887 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36718000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36413 # number of replacements -system.iocache.tags.tagsinuse 1.069649 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.069482 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36429 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 236542797000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.069649 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.066853 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.066853 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 236543521000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.069482 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.066843 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.066843 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1926,8 +1932,8 @@ system.iocache.overall_misses::realview.ide 223 # system.iocache.overall_misses::total 223 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 28108377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 28108377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4720216172 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4720216172 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4550219510 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4550219510 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 28108377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 28108377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 28108377 # number of overall miss cycles @@ -1950,17 +1956,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 126046.533632 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 126046.533632 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130306.321003 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130306.321003 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125613.391950 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125613.391950 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 126046.533632 # average overall miss latency system.iocache.demand_avg_miss_latency::total 126046.533632 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 126046.533632 # average overall miss latency system.iocache.overall_avg_miss_latency::total 126046.533632 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 748 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 92 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.130435 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1976,8 +1982,8 @@ system.iocache.overall_mshr_misses::realview.ide 223 system.iocache.overall_mshr_misses::total 223 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 16958377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 16958377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2909016172 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2909016172 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737617166 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2737617166 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 16958377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 16958377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 16958377 # number of overall MSHR miss cycles @@ -1992,272 +1998,272 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76046.533632 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 76046.533632 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80306.321003 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80306.321003 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75574.678832 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75574.678832 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 76046.533632 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 76046.533632 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104282 # number of replacements -system.l2c.tags.tagsinuse 65109.864542 # Cycle average of tags in use -system.l2c.tags.total_refs 5144491 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169597 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 30.333620 # Average number of references to valid blocks. +system.l2c.tags.replacements 104258 # number of replacements +system.l2c.tags.tagsinuse 65109.968422 # Cycle average of tags in use +system.l2c.tags.total_refs 5143670 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169575 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.332714 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 74702530500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48974.636998 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 36.118428 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48981.284671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.148352 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4878.666588 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2907.615962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 60.909548 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5701.864987 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2550.051717 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.747294 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000551 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4875.960146 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2904.898694 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 61.768888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5697.678778 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2553.228578 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.747395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000536 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074443 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044367 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000929 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.087004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.038911 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993498 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074401 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044325 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000943 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.086940 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.038959 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993499 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65233 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 84 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3229 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8999 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52641 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3237 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9000 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52639 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.001282 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45471419 # Number of tag accesses -system.l2c.tags.data_accesses 45471419 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 34274 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7651 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 8292 # number of ReadReq hits -system.l2c.ReadReq_hits::total 87028 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 705176 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 705176 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1895159 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1895159 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 43 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 48 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 91 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 54 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 74922 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 82000 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156922 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 926497 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 988644 # number of ReadCleanReq hits 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# number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34274 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7651 # number of overall hits -system.l2c.overall_hits::cpu0.inst 926497 # number of overall hits -system.l2c.overall_hits::cpu0.data 354739 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36811 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 8292 # number of overall hits -system.l2c.overall_hits::cpu1.inst 988644 # number of overall hits -system.l2c.overall_hits::cpu1.data 345870 # number of overall hits -system.l2c.overall_hits::total 2702778 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.995377 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45464154 # Number of tag accesses +system.l2c.tags.data_accesses 45464154 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 34252 # number of ReadReq hits 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-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010333 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011139 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010750 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.028461 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.025878 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001660 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000131 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.190515 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002169 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.171711 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061189 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001660 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000131 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010333 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.190515 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002169 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.171711 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061189 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5195711500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5480937000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10752656497 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001661 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.002201 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.001601 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.969697 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.968521 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.969127 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.312500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.242424 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502234 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.440308 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.471584 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.010372 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011091 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010744 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.028506 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.025802 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.027192 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001661 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000133 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010372 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.190919 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.002201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011091 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.171299 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061195 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001661 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000133 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010372 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.190919 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.002201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011091 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.171299 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061195 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 126952.898551 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70823.384831 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70782.707728 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70803.917613 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70600 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70843.750000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123598.871257 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123721.764597 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 123655.666341 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123142.753773 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122754.960851 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122935.226515 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125259.726796 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128143.111808 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126588.915916 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 129737.410072 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68016.335227 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68012.849584 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68014.646650 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68350 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68406.250000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 123472.485592 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123695.372647 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 123575.488551 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 123282.440797 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122975.562736 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 123118.502957 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 125652.447577 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128291.012981 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126869.072157 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123142.753773 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123761.945536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122754.960851 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124154.047798 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 123826.407292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130236.842105 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 123282.440797 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123686.385502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122975.562736 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 124144.606230 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 123810.661044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135122.807018 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 122500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123142.753773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123761.945536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124668.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122754.960851 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124154.047798 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 123826.407292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 123282.440797 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123686.385502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126037.037037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122975.562736 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124144.606230 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 123810.661044 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188341.659324 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191332.162921 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188315.501368 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158646.886904 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190033.327940 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172710.943164 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188322.718341 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 191352.962737 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 188316.853697 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 158640.699888 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190053.330096 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172710.798173 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113784.426647 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173260.015344 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190773.453267 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 181066.220376 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173248.132711 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 190793.922094 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 181066.877107 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 31797 # Transaction distribution -system.membus.trans_dist::ReadResp 68179 # Transaction distribution +system.membus.trans_dist::ReadResp 68158 # Transaction distribution system.membus.trans_dist::WriteReq 27588 # Transaction distribution system.membus.trans_dist::WriteResp 27588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 131704 # Transaction distribution -system.membus.trans_dist::CleanEvict 8781 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4622 # Transaction distribution +system.membus.trans_dist::WritebackDirty 131684 # Transaction distribution +system.membus.trans_dist::CleanEvict 8987 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4621 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 16 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4638 # Transaction distribution -system.membus.trans_dist::ReadExReq 138120 # Transaction distribution -system.membus.trans_dist::ReadExResp 138120 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 36383 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 138118 # Transaction distribution +system.membus.trans_dist::ReadExResp 138118 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 36362 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 473019 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 580601 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 689490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 468311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 575893 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72875 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72875 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648768 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17310428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17474421 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17307612 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17471605 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19791541 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 494 # Total snoops (count) -system.membus.snoop_fanout::samples 415457 # Request fanout histogram +system.membus.pkt_size::total 19788725 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 495 # Total snoops (count) +system.membus.snoop_fanout::samples 415409 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 415457 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 415409 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 415457 # Request fanout histogram -system.membus.reqLayer0.occupancy 95427000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 415409 # Request fanout histogram +system.membus.reqLayer0.occupancy 95443000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 17812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1716000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 922382161 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 922132455 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1017668838 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1008187748 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64149362 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1182123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2553,60 +2558,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5623218 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2831016 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 48178 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 419 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 419 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5622550 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2830625 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 48155 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 418 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 418 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 148339 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2643775 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 147977 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2643178 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 836888 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1895159 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 151681 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2822 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 70 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2892 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296933 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296933 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1936256 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 559265 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 836971 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1935383 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 159154 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 66 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2884 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296889 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296889 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1935963 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 559323 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5768715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2683173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41220 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162488 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8655596 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 245234624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100105653 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 63776 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 345688941 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 206956 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3148204 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027216 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.162713 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5808360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2690765 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 40688 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 162297 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8702110 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 247790656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 100113141 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62776 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 284444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 348251017 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 206924 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3147531 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027177 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.162600 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 3062522 97.28% 97.28% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 85682 2.72% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 3061989 97.28% 97.28% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 85542 2.72% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3148204 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5535720994 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3147531 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5535076493 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 269377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2907347058 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2906930517 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1330807539 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1330817051 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25313424 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 25031921 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 91701122 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 91623614 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3037 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index b300e6060..d1b3d40ca 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,171 +1,171 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.381683 # Number of seconds simulated -sim_ticks 47381683294000 # Number of ticks simulated -final_tick 47381683294000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.461935 # Number of seconds simulated +sim_ticks 47461934895000 # Number of ticks simulated +final_tick 47461934895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169119 # Simulator instruction rate (inst/s) -host_op_rate 198983 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9178439782 # Simulator tick rate (ticks/s) -host_mem_usage 757568 # Number of bytes of host memory used -host_seconds 5162.28 # Real time elapsed on the host -sim_insts 873041938 # Number of instructions simulated -sim_ops 1027205539 # Number of ops (including micro ops) simulated +host_inst_rate 231788 # Simulator instruction rate (inst/s) +host_op_rate 272612 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12136870284 # Simulator tick rate (ticks/s) +host_mem_usage 762440 # Number of bytes of host memory used +host_seconds 3910.56 # Real time elapsed on the host +sim_insts 906421729 # Number of instructions simulated +sim_ops 1066065309 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 75648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7273408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37833736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 11654720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 106816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 96448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3691584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 15254352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 10772160 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 424448 # Number of bytes read from this memory -system.physmem.bytes_read::total 87268888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 7273408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3691584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10964992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68656704 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 128960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 112832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8192640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40731208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 14846528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 153920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 132096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3008640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 17045264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 15179584 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 435648 # Number of bytes read from this memory +system.physmem.bytes_read::total 99967320 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8192640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3008640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11201280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79350912 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 68677288 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 113647 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 591165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 182105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1669 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 57681 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 238362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 168315 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6632 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1363602 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1072761 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79371496 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1763 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 128010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 636438 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 231977 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2405 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2064 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 47010 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 266345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 237181 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1562015 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1239858 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1075335 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 153507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 798489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 245975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 77912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 321946 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 227349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1841828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 153507 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 77912 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 231418 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1449014 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1242432 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2377 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 172615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 858187 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 312809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 63391 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 359135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 319826 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9179 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2106263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 172615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 63391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 236006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1671885 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1449448 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1449014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 153507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 798923 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 245975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 77912 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 321946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 227349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8958 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3291276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1363603 # Number of read requests accepted -system.physmem.writeReqs 1075335 # Number of write requests accepted -system.physmem.readBursts 1363603 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1075335 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 87237120 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue -system.physmem.bytesWritten 68675712 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 87268952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68677288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1672319 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1671885 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2717 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2377 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 172615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 858620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 312809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3243 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2783 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 63391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 359136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 319826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9179 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3778582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1562015 # Number of read requests accepted +system.physmem.writeReqs 1242432 # Number of write requests accepted +system.physmem.readBursts 1562015 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1242432 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 99934848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 34112 # Total number of bytes read from write queue +system.physmem.bytesWritten 79370432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 99967320 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 79371496 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 533 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 497625 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 80650 # Per bank write bursts -system.physmem.perBankRdBursts::1 88729 # Per bank write bursts -system.physmem.perBankRdBursts::2 73569 # Per bank write bursts -system.physmem.perBankRdBursts::3 80330 # Per bank write bursts -system.physmem.perBankRdBursts::4 79168 # Per bank write bursts -system.physmem.perBankRdBursts::5 89219 # Per bank write bursts -system.physmem.perBankRdBursts::6 76757 # Per bank write bursts -system.physmem.perBankRdBursts::7 80146 # Per bank write bursts -system.physmem.perBankRdBursts::8 80110 # Per bank write bursts -system.physmem.perBankRdBursts::9 145487 # Per bank write bursts -system.physmem.perBankRdBursts::10 85462 # Per bank write bursts -system.physmem.perBankRdBursts::11 91495 # Per bank write bursts -system.physmem.perBankRdBursts::12 74671 # Per bank write bursts -system.physmem.perBankRdBursts::13 80575 # Per bank write bursts -system.physmem.perBankRdBursts::14 75276 # Per bank write bursts -system.physmem.perBankRdBursts::15 81436 # Per bank write bursts -system.physmem.perBankWrBursts::0 65415 # Per bank write bursts -system.physmem.perBankWrBursts::1 72062 # Per bank write bursts -system.physmem.perBankWrBursts::2 62920 # Per bank write bursts -system.physmem.perBankWrBursts::3 67234 # Per bank write bursts -system.physmem.perBankWrBursts::4 65543 # Per bank write bursts -system.physmem.perBankWrBursts::5 71204 # Per bank write bursts -system.physmem.perBankWrBursts::6 63108 # Per bank write bursts -system.physmem.perBankWrBursts::7 65618 # Per bank write bursts -system.physmem.perBankWrBursts::8 64627 # Per bank write bursts -system.physmem.perBankWrBursts::9 73983 # Per bank write bursts -system.physmem.perBankWrBursts::10 67070 # Per bank write bursts -system.physmem.perBankWrBursts::11 71654 # Per bank write bursts -system.physmem.perBankWrBursts::12 63584 # Per bank write bursts -system.physmem.perBankWrBursts::13 67795 # Per bank write bursts -system.physmem.perBankWrBursts::14 63419 # Per bank write bursts -system.physmem.perBankWrBursts::15 67822 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 93757 # Per bank write bursts +system.physmem.perBankRdBursts::1 100629 # Per bank write bursts +system.physmem.perBankRdBursts::2 93977 # Per bank write bursts +system.physmem.perBankRdBursts::3 99615 # Per bank write bursts +system.physmem.perBankRdBursts::4 97211 # Per bank write bursts +system.physmem.perBankRdBursts::5 108899 # Per bank write bursts +system.physmem.perBankRdBursts::6 95410 # Per bank write bursts +system.physmem.perBankRdBursts::7 95079 # Per bank write bursts +system.physmem.perBankRdBursts::8 84413 # Per bank write bursts +system.physmem.perBankRdBursts::9 140545 # Per bank write bursts +system.physmem.perBankRdBursts::10 87149 # Per bank write bursts +system.physmem.perBankRdBursts::11 92128 # Per bank write bursts +system.physmem.perBankRdBursts::12 89605 # Per bank write bursts +system.physmem.perBankRdBursts::13 97795 # Per bank write bursts +system.physmem.perBankRdBursts::14 91413 # Per bank write bursts +system.physmem.perBankRdBursts::15 93857 # Per bank write bursts +system.physmem.perBankWrBursts::0 74634 # Per bank write bursts +system.physmem.perBankWrBursts::1 80843 # Per bank write bursts +system.physmem.perBankWrBursts::2 76779 # Per bank write bursts +system.physmem.perBankWrBursts::3 81501 # Per bank write bursts +system.physmem.perBankWrBursts::4 79021 # Per bank write bursts +system.physmem.perBankWrBursts::5 86869 # Per bank write bursts +system.physmem.perBankWrBursts::6 77167 # Per bank write bursts +system.physmem.perBankWrBursts::7 78926 # Per bank write bursts +system.physmem.perBankWrBursts::8 71646 # Per bank write bursts +system.physmem.perBankWrBursts::9 75252 # Per bank write bursts +system.physmem.perBankWrBursts::10 73334 # Per bank write bursts +system.physmem.perBankWrBursts::11 76259 # Per bank write bursts +system.physmem.perBankWrBursts::12 74746 # Per bank write bursts +system.physmem.perBankWrBursts::13 79667 # Per bank write bursts +system.physmem.perBankWrBursts::14 75302 # Per bank write bursts +system.physmem.perBankWrBursts::15 78217 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 20 # Number of times write queue was full causing retry -system.physmem.totGap 47381681282500 # Total gap between requests +system.physmem.numWrRetry 64 # Number of times write queue was full causing retry +system.physmem.totGap 47461932782500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1363573 # Read request sizes (log2) +system.physmem.readPktSize::6 1561985 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1072761 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 866656 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 332331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 26767 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22591 # What read queue length does an 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does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see @@ -188,164 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 39692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 50721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 63294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 64512 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 69607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 74517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 69942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 75013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 68273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 64139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 61949 # What write queue length does an incoming req see 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write queue length does an incoming req see -system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 845070 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 184.496716 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 112.937858 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 245.074486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 518646 61.37% 61.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 158346 18.74% 80.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53030 6.28% 86.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28124 3.33% 89.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18210 2.15% 91.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11789 1.40% 93.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8638 1.02% 94.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8488 1.00% 95.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 39799 4.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 845070 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60101 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.679190 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 352.199560 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 60098 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 20126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 23872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 45415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 64128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 66477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 70043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 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queue length does an incoming req see +system.physmem.wrQLenPdf::46 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 150 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 991222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 180.892514 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.543893 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 240.536828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 614355 61.98% 61.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 184510 18.61% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61267 6.18% 86.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 32396 3.27% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21556 2.17% 92.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13955 1.41% 93.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9658 0.97% 94.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9476 0.96% 95.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 44049 4.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 991222 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69967 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.317164 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 326.421262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 69964 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60101 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60101 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.854245 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.273539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.223401 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56328 93.72% 93.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1584 2.64% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 235 0.39% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 339 0.56% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 81 0.13% 97.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 304 0.51% 97.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 166 0.28% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 108 0.18% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 84 0.14% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 101 0.17% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 39 0.06% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 59 0.10% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 433 0.72% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 41 0.07% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.05% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 91 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 69967 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69967 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.724970 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.179434 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.169336 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 65865 94.14% 94.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 2036 2.91% 97.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 254 0.36% 97.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 187 0.27% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 141 0.20% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 122 0.17% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 214 0.31% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 78 0.11% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 271 0.39% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 64 0.09% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 34 0.05% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 49 0.07% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 243 0.35% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 32 0.05% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 40 0.06% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 104 0.15% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60101 # Writes before turning the bus around for reads -system.physmem.totQLat 33864601554 # Total ticks spent queuing -system.physmem.totMemAccLat 59422351554 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6815400000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24844.18 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 14 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69967 # Writes before turning the bus around for reads +system.physmem.totQLat 43176438588 # Total ticks spent queuing +system.physmem.totMemAccLat 72454226088 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7807410000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27650.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43594.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46400.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.67 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing -system.physmem.readRowHits 1093420 # Number of row buffer hits during reads -system.physmem.writeRowHits 497646 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 46.38 # Row buffer hit rate for writes -system.physmem.avgGap 19427177.44 # Average gap between requests -system.physmem.pageHitRate 65.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3178488600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1734294375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5058697800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3454513920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1187868500820 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27387019861500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31683055542135 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.677294 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45560417443643 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582178520000 # Time in different power states +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing +system.physmem.readRowHits 1247973 # Number of row buffer hits during reads +system.physmem.writeRowHits 562447 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.92 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.35 # Row buffer hit rate for writes +system.physmem.avgGap 16923811.64 # Average gap between requests +system.physmem.pageHitRate 64.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3897081720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2126383875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6119692800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4119595200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1216381568355 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27410155454250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31742782180680 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.805156 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45598728268843 # Time in different power states +system.physmem_0.memoryStateTime::REF 1584858080000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 239087007607 # Time in different power states +system.physmem_0.memoryStateTime::ACT 278346651157 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3210233040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1751615250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5573178000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3498901920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094741185120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1203743481615 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27373094439750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31685613034695 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.731270 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45537111526279 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582178520000 # Time in different power states +system.physmem_1.actEnergy 3596556600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1962406875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6059788800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3916661040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3099982404480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1207691479170 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27417778331250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31740987628215 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.767346 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45611421903472 # Time in different power states +system.physmem_1.memoryStateTime::REF 1584858080000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 262392956221 # Time in different power states +system.physmem_1.memoryStateTime::ACT 265649419028 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -379,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1674 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 132357688 # Number of BP lookups -system.cpu0.branchPred.condPredicted 93633614 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5912907 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98988393 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 72530253 # Number of BTB hits +system.cpu0.branchPred.lookups 141158417 # Number of BP lookups +system.cpu0.branchPred.condPredicted 100207840 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6289341 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 105574499 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76948344 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.271472 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15763072 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1049472 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.885351 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 16552897 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1094870 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -418,64 +423,63 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 265700 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 265700 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9033 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73083 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 265700 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 265700 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 265700 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 82116 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22524.489746 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20895.928471 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16961.244602 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 81335 99.05% 99.05% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 195 0.24% 99.29% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 500 0.61% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 283140 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 283140 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9717 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79661 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 283140 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 283140 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 283140 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 89378 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23531.797534 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21398.159545 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 20518.573843 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 88174 98.65% 98.65% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 214 0.24% 98.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 839 0.94% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 38 0.04% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 35 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 82116 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 89378 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 73083 89.00% 89.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9033 11.00% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 82116 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 265700 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 79661 89.13% 89.13% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 9717 10.87% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 89378 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 283140 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 265700 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 82116 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 283140 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 89378 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 82116 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 347816 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 89378 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 372518 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 86394812 # DTB read hits -system.cpu0.dtb.read_misses 220998 # DTB read misses -system.cpu0.dtb.write_hits 74903999 # DTB write hits -system.cpu0.dtb.write_misses 44702 # DTB write misses +system.cpu0.dtb.read_hits 90921588 # DTB read hits +system.cpu0.dtb.read_misses 233548 # DTB read misses +system.cpu0.dtb.write_hits 80603054 # DTB write hits +system.cpu0.dtb.write_misses 49592 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 37665 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1452 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8673 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38267 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2134 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9015 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10301 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 86615810 # DTB read accesses -system.cpu0.dtb.write_accesses 74948701 # DTB write accesses +system.cpu0.dtb.perms_faults 11497 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91155136 # DTB read accesses +system.cpu0.dtb.write_accesses 80652646 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 161298811 # DTB hits -system.cpu0.dtb.misses 265700 # DTB misses -system.cpu0.dtb.accesses 161564511 # DTB accesses +system.cpu0.dtb.hits 171524642 # DTB hits +system.cpu0.dtb.misses 283140 # DTB misses +system.cpu0.dtb.accesses 171807782 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -505,191 +509,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 59769 # Table walker walks requested -system.cpu0.itb.walker.walksLong 59769 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 498 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49758 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 59769 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 59769 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 59769 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 50256 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25230.221267 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23083.004989 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19430.494891 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 46691 92.91% 92.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 2859 5.69% 98.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 7 0.01% 98.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 383 0.76% 99.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 254 0.51% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 9 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 4 0.01% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 25 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 50256 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 66290 # Table walker walks requested +system.cpu0.itb.walker.walksLong 66290 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 665 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 56612 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 66290 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 66290 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 66290 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 57277 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26707.997975 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23913.035188 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 23204.196076 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 56118 97.98% 97.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 13 0.02% 98.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1037 1.81% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 46 0.08% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 57277 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 49758 99.01% 99.01% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 498 0.99% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 50256 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 56612 98.84% 98.84% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 665 1.16% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57277 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59769 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59769 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66290 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66290 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50256 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50256 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 110025 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 238646690 # ITB inst hits -system.cpu0.itb.inst_misses 59769 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57277 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57277 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 123567 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 252665762 # ITB inst hits +system.cpu0.itb.inst_misses 66290 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 27225 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 27416 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203945 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203450 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 238706459 # ITB inst accesses -system.cpu0.itb.hits 238646690 # DTB hits -system.cpu0.itb.misses 59769 # DTB misses -system.cpu0.itb.accesses 238706459 # DTB accesses -system.cpu0.numCycles 1007854766 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 252732052 # ITB inst accesses +system.cpu0.itb.hits 252665762 # DTB hits +system.cpu0.itb.misses 66290 # DTB misses +system.cpu0.itb.accesses 252732052 # DTB accesses +system.cpu0.numCycles 1081051562 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 441362500 # Number of instructions committed -system.cpu0.committedOps 518398273 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43962057 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93756283149 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.283508 # CPI: cycles per instruction -system.cpu0.ipc 0.437923 # IPC: instructions per cycle +system.cpu0.committedInsts 468741146 # Number of instructions committed +system.cpu0.committedOps 550955855 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 47157402 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 5078 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93843643871 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.306287 # CPI: cycles per instruction +system.cpu0.ipc 0.433597 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5202 # number of quiesce instructions executed -system.cpu0.tickCycles 710760418 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 297094348 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5529190 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.574807 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 153025870 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5529699 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.673454 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 5324 # number of quiesce instructions executed +system.cpu0.tickCycles 755067683 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 325983879 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 5850262 # number of replacements +system.cpu0.dcache.tags.tagsinuse 501.214442 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 162710873 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5850774 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.810145 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.574807 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938623 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 325514940 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 325514940 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79084139 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79084139 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69445340 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69445340 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 251787 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 251787 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143392 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 143392 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1790882 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1790882 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1762255 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1762255 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148529479 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 148529479 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148781266 # number of overall hits -system.cpu0.dcache.overall_hits::total 148781266 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3438422 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3438422 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2286291 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2286291 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 632969 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 632969 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 749661 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 749661 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167888 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 167888 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194810 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 194810 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5724713 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5724713 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6357682 # number of overall misses -system.cpu0.dcache.overall_misses::total 6357682 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57301041000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 57301041000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 58503452500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 58503452500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 69078584500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 69078584500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2562226000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2562226000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5482087500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5482087500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5099500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5099500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 115804493500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 115804493500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 115804493500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 115804493500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 82522561 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 82522561 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71731631 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 71731631 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 884756 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 884756 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 893053 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 893053 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1958770 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1958770 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1957065 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1957065 # number of StoreCondReq accesses(hits+misses) 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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 16664.923910 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25588.804094 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25588.804094 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 92146.429519 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 92146.429519 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15261.519584 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15261.519584 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28140.688363 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28140.688363 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 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# number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2015754 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014264 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2014264 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 164074862 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164074862 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 165039187 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 165039187 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041105 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.041105 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032126 # miss 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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16248.280858 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27787.387292 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27787.387292 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20228.873220 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20228.873220 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18214.892393 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18214.892393 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20797.963754 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20797.963754 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18666.379301 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18666.379301 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,161 +698,161 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5529208 # number of writebacks -system.cpu0.dcache.writebacks::total 5529208 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 425438 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 425438 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 937459 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 937459 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 53 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 53 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41154 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41154 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 15 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 15 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1362897 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1362897 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1362897 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1362897 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3012984 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3012984 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1348832 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1348832 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631309 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 631309 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 749608 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 749608 # number 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-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16430 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16430 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31915 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 31915 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44936822000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44936822000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34248227000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34248227000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15688131000 # number of SoftPFReq MSHR miss cycles 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StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79185049000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 79185049000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94873180000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 94873180000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2777500000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2777500000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2891122000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2891122000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5668622000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5668622000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018804 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018804 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.713540 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.713540 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.839377 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.839377 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064701 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064701 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099534 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099534 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028277 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028277 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032185 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032185 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14914.391182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14914.391182 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25391.024976 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25391.024976 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24850.162123 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24850.162123 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 91146.509242 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 91146.509242 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13635.531901 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13635.531901 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27137.049206 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27137.049206 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5850286 # number of writebacks +system.cpu0.dcache.writebacks::total 5850286 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444097 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 444097 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1026850 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1026850 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 104 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 104 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44524 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44524 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 32 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 32 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1470947 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1470947 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1470947 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1470947 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125373 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3125373 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1454421 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1454421 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 689314 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 689314 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 805970 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 805970 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129400 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 129400 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 207806 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 207806 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579794 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4579794 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5269108 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5269108 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19530 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19530 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21048 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21048 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40578 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40578 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49230560000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49230560000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36276054500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36276054500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18434925500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18434925500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 70481228500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 70481228500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1893845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1893845500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5565229000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5565229000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4561000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4561000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 85506614500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 85506614500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103941540000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 103941540000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3800939500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3800939500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3971667500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3971667500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7772607000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7772607000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035991 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035991 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018831 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018831 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.714815 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.714815 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.814225 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.814225 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064194 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064194 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103167 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103167 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027913 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027913 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031926 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031926 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15751.899053 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15751.899053 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24941.921562 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24941.921562 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26743.872169 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26743.872169 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87448.947852 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87448.947852 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14635.591190 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14635.591190 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26780.886981 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26780.886981 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18154.147034 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18154.147034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19000.762048 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19000.762048 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179367.129480 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179367.129480 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 175966.037736 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175966.037736 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177616.230613 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177616.230613 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18670.406245 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18670.406245 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19726.591294 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19726.591294 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194620.558116 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194620.558116 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188695.719308 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 188695.719308 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191547.316280 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191547.316280 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 8961850 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.890744 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 229474819 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 8962362 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 25.604279 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 9594128 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.890921 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 242861120 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 9594640 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.312166 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40343615000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890921 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 247 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 485836753 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 485836753 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 229474819 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 229474819 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 229474819 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 229474819 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 229474819 # number of overall hits -system.cpu0.icache.overall_hits::total 229474819 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8962372 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 8962372 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8962372 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 8962372 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8962372 # number of overall misses -system.cpu0.icache.overall_misses::total 8962372 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 94471116000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 94471116000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 94471116000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 94471116000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 94471116000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 94471116000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 238437191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 238437191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 238437191 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 238437191 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 238437191 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 238437191 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037588 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.037588 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037588 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.037588 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037588 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.037588 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10540.860835 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10540.860835 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10540.860835 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10540.860835 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10540.860835 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 514506190 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 514506190 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 242861120 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 242861120 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 242861120 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 242861120 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 242861120 # number of overall hits +system.cpu0.icache.overall_hits::total 242861120 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 9594650 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 9594650 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 9594650 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 9594650 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 9594650 # number of overall misses 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+system.cpu0.icache.demand_accesses::total 252455770 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 252455770 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 252455770 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.038005 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.038005 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.038005 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.038005 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.038005 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.038005 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10694.828264 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10694.828264 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10694.828264 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10694.828264 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10694.828264 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,491 +861,505 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed 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MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 89989930500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 89989930500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 89989930500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 89989930500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 97815809000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 97815809000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 97815809000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 97815809000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 97815809000 # number of overall MSHR miss cycles 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0.038005 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.038005 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.038005 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.038005 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10194.828264 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10194.828264 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10194.828264 # average overall mshr miss latency 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64173364000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64173364000 # number of InvalidateReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 377798500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25527386000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54002983994 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 80388636494 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 480468000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 377798500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25527386000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54002983994 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44849426201 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 125238062695 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2653464500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9649619500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2767850000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2767850000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3644540000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10640695000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3813756000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3813756000 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5421314500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12417469500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028229 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7458296000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14454451000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029661 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998643 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998643 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998145 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998145 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.242429 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.242429 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079332 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260815 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260815 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.775614 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.775614 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.136550 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022178 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047622 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079332 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256661 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.239883 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.239883 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080799 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.270086 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270086 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.755217 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.755217 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139040 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023171 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049164 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080799 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.263055 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.189248 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34093.365180 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46802.000652 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31159.903678 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31159.903678 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19615.493408 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19615.493408 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 510222 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 510222 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55365.484012 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55365.484012 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31576.214868 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32859.363553 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32859.363553 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 107694.400725 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 107694.400725 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 35442.839203 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32339.464586 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36710.874454 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31576.214868 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37662.039004 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46802.000652 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38605.937054 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.191643 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40211.136619 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55167.381577 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29321.577271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29321.577271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19259.373331 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19259.373331 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 460833.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 460833.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 55367.435521 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 55367.435521 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32928.322934 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35777.482886 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35777.482886 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 105717.827108 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 105717.827108 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37410.526173 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 38403.644793 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42771.255519 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32928.322934 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39935.975810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55167.381577 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42284.528463 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171357.087504 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142337.367614 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168463.177115 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 168463.177115 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186612.391193 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148118.640293 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181193.272520 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181193.272520 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 169867.288109 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 147433.860895 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183801.468776 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 155613.282806 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 29837081 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 15255646 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2671 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2145858 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2145409 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 449 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 816702 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13639128 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 16430 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16430 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5128977 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 10898588 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2922524 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 983530 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 456186 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 346923 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 512261 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1174017 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1108975 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 8962372 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4744543 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 755832 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 747915 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 26989618 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17891664 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 337201 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1079102 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 46297585 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1150395968 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 671911459 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1269832 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4069344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1827646603 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7092856 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 22718303 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.108382 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.310926 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 31782914 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16244108 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2495 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2292721 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2292254 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 467 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 871142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 14502039 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 21048 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 21048 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5574338 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 11577498 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 3160606 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1056652 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 471328 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 370548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 537517 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1276044 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1205760 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9594650 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5010763 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 810566 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 803776 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 28888045 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18933308 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 377591 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1141314 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 49340258 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1231429504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 710021103 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1437320 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4319512 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1947207439 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7690219 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 24350841 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.107639 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.309986 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 20256496 89.16% 89.16% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2461358 10.83% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 449 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 21730213 89.24% 89.24% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2620161 10.76% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 467 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22718303 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 29677749987 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 24350841 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 31629791489 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 177431926 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 184209930 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 13525621280 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 14474040275 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7933800899 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8384067550 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 178529385 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 198003844 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 570584194 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 601473802 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 131141392 # Number of BP lookups -system.cpu1.branchPred.condPredicted 92458444 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6313157 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 97645974 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 70218111 # Number of BTB hits +system.cpu1.branchPred.lookups 133924240 # Number of BP lookups +system.cpu1.branchPred.condPredicted 95730476 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5982653 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 100302023 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 73831862 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.910913 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 15567912 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1046402 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.609544 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 15419194 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 1021732 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,63 +1389,63 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 286101 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 286101 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9457 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80855 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 286101 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 286101 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 286101 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 90312 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23344.699486 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21447.607691 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 19228.959334 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 89271 98.85% 98.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 163 0.18% 99.03% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 728 0.81% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 35 0.04% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 43 0.05% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 28 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 30 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 293746 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 293746 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11413 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90757 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 293746 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 293746 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 293746 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 102170 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23413.986493 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21412.179846 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20342.964000 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 100862 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 952 0.93% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 45 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 90312 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 102170 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 527505760 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 527505760 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 527505760 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 80855 89.53% 89.53% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9457 10.47% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 90312 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 286101 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 90757 88.83% 88.83% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11413 11.17% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 102170 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 293746 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 286101 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 293746 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102170 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90312 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 376413 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102170 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 395916 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84597106 # DTB read hits -system.cpu1.dtb.read_misses 236435 # DTB read misses -system.cpu1.dtb.write_hits 75395592 # DTB write hits -system.cpu1.dtb.write_misses 49666 # DTB write misses +system.cpu1.dtb.read_hits 86040245 # DTB read hits +system.cpu1.dtb.read_misses 244355 # DTB read misses +system.cpu1.dtb.write_hits 75067998 # DTB write hits +system.cpu1.dtb.write_misses 49391 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 35920 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1878 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8819 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 37937 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1338 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8312 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11434 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 84833541 # DTB read accesses -system.cpu1.dtb.write_accesses 75445258 # DTB write accesses +system.cpu1.dtb.perms_faults 11189 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 86284600 # DTB read accesses +system.cpu1.dtb.write_accesses 75117389 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159992698 # DTB hits -system.cpu1.dtb.misses 286101 # DTB misses -system.cpu1.dtb.accesses 160278799 # DTB accesses +system.cpu1.dtb.hits 161108243 # DTB hits +system.cpu1.dtb.misses 293746 # DTB misses +system.cpu1.dtb.accesses 161401989 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1461,186 +1475,188 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 70499 # Table walker walks requested -system.cpu1.itb.walker.walksLong 70499 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 664 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63113 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 70499 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 70499 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 70499 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 63777 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26275.796917 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23950.266979 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 21020.894290 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 62694 98.30% 98.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 8 0.01% 98.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 977 1.53% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 42 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 63777 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 65124 # Table walker walks requested +system.cpu1.itb.walker.walksLong 65124 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 508 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 65124 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 65124 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 65124 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 56274 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26926.564666 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23857.779953 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24945.648372 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 54940 97.63% 97.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1199 2.13% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 49 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 56274 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 526611260 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 526611260 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 526611260 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 63113 98.96% 98.96% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 664 1.04% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63777 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 55766 99.10% 99.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 508 0.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56274 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 70499 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 70499 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 65124 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 65124 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63777 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63777 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 134276 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 232338774 # ITB inst hits -system.cpu1.itb.inst_misses 70499 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56274 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56274 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 121398 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 239249458 # ITB inst hits +system.cpu1.itb.inst_misses 65124 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 39659 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25488 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42784 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1060 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 26970 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 208774 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 220780 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 232409273 # ITB inst accesses -system.cpu1.itb.hits 232338774 # DTB hits -system.cpu1.itb.misses 70499 # DTB misses -system.cpu1.itb.accesses 232409273 # DTB accesses -system.cpu1.numCycles 934140798 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 239314582 # ITB inst accesses +system.cpu1.itb.hits 239249458 # DTB hits +system.cpu1.itb.misses 65124 # DTB misses +system.cpu1.itb.accesses 239314582 # DTB accesses +system.cpu1.numCycles 947127317 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 431679438 # Number of instructions committed -system.cpu1.committedOps 508807266 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 44929639 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 4564 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93829974504 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 437680583 # Number of instructions committed +system.cpu1.committedOps 515109454 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 47548266 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 4998 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93977493591 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu1.cpi 2.163969 # CPI: cycles per instruction system.cpu1.ipc 0.462114 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13472 # number of quiesce instructions executed -system.cpu1.tickCycles 702823433 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 231317365 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5070717 # number of replacements -system.cpu1.dcache.tags.tagsinuse 459.449189 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 152180192 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5071229 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.008543 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8388824602000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.449189 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897362 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.897362 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 13761 # number of quiesce instructions executed +system.cpu1.tickCycles 715510770 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 231616547 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 5225400 # number of replacements +system.cpu1.dcache.tags.tagsinuse 442.020428 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 153149767 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5225912 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.305845 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8545383120500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 442.020428 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.863321 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.863321 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 322309894 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 322309894 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 77705355 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 77705355 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70371137 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70371137 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 247594 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 247594 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 180643 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 180643 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624088 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1624088 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1588942 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1588942 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 148076492 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 148076492 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 148324086 # number of overall hits -system.cpu1.dcache.overall_hits::total 148324086 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3222913 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3222913 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2183254 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2183254 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 592382 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 592382 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 513289 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 513289 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 153645 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 153645 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187516 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 187516 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 5406167 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 5406167 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5998549 # number of overall misses -system.cpu1.dcache.overall_misses::total 5998549 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52049628500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 52049628500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 47596189000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 47596189000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20614887000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 20614887000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2521232500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2521232500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5224495500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5224495500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4869500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4869500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 99645817500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 99645817500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 99645817500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 99645817500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 80928268 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 80928268 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72554391 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72554391 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 839976 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 839976 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 693932 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 693932 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1777733 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1777733 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1776458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1776458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 153482659 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 153482659 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 154322635 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 154322635 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039824 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039824 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030091 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030091 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.705237 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.705237 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.739682 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.739682 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086427 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086427 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105556 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105556 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035223 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035223 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.038870 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.038870 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16149.870785 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16149.870785 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21800.573364 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21800.573364 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 40162.339345 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 40162.339345 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16409.466628 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16409.466628 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27861.598477 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27861.598477 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 324837482 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 324837482 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 78835589 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 78835589 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 69932856 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 69932856 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235045 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 235045 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 136840 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 136840 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1777859 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1777859 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734680 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1734680 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 148768445 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 148768445 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 149003490 # number of overall hits +system.cpu1.dcache.overall_hits::total 149003490 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3368921 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3368921 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2278073 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2278073 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 647676 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 647676 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 450910 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 450910 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159516 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 159516 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 201171 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 201171 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5646994 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5646994 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 6294670 # number of overall misses +system.cpu1.dcache.overall_misses::total 6294670 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 55794276000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 55794276000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51841670500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 51841670500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21264976000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 21264976000 # number of WriteLineReq miss cycles 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107635946500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 82204510 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 82204510 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 72210929 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 72210929 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 882721 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 882721 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 587750 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 587750 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1937375 # number of LoadLockedReq accesses(hits+misses) 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average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19060.750994 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17099.537625 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17099.537625 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1649,161 +1665,161 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5070732 # number of writebacks -system.cpu1.dcache.writebacks::total 5070732 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 348629 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 348629 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 899898 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 899898 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 110 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 110 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43396 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43396 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 20 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 20 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1248527 # number of demand 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-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.739523 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062017 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062017 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105545 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105545 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027089 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027089 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030777 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030777 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14484.917635 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14484.917635 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21949.730628 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21949.730628 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24329.804361 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24329.804361 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39147.269276 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 39147.269276 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14461.641375 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14461.641375 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26858.052972 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26858.052972 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 5225429 # number of writebacks +system.cpu1.dcache.writebacks::total 5225429 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 382545 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 382545 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 937825 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 937825 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of 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uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3151598000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2962839500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2962839500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 6114437500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 6114437500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036329 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036329 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018560 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018560 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.733407 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.733407 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.767081 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.767081 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060875 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060875 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103901 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103901 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028019 # mshr miss rate for demand accesses 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184086.971720 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 184086.971720 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17397.480461 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17397.480461 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18295.517929 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18295.517929 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164754.979351 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164754.979351 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169624.978531 # average WriteReq mshr uncacheable latency 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+system.cpu1.icache.demand_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9738.978072 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9738.978072 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 140766.304348 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 140766.304348 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6510084 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6511152 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 939 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 7101301 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7101636 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 296 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 783896 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2135895 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13423.461637 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 24573645 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2151628 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.420954 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9991507442000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12589.805999 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.598025 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.072993 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 692.984620 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.768421 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004460 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.042296 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.819303 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 945 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14692 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 185 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 707 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 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ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 12943476999 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 25012449000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 25012449000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34434512490 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34434512490 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17540729000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 17540729000 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 470190500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 378267000 # number of demand (read+write) miss cycles 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accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 757638 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3212997 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 3212997 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 11821046 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 11821046 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205064 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 205064 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187493 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 187493 # number of SCUpgradeReq accesses(hits+misses) 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accesses -system.cpu1.l2cache.overall_accesses::total 15381077 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.019210 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.041562 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.024962 # miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998191 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998191 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 867300 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2326720 # number of replacements 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blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5193 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7319 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 995 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085144 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per 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-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.024958 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5830277500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5842492000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027270 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.218879 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.218879 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.066850 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245183 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245183 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.512572 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.512572 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.116933 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.019210 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041547 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.066850 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239077 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217571 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217571 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.074364 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.258364 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.258364 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.595469 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.595469 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.129144 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020969 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048259 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.074364 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.248992 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.162850 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38868.158020 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46447.148846 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32424.723840 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32424.723840 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19335.311185 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19335.311185 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1405833 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1405833 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45218.858431 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45218.858431 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31542.063292 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33176.746514 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33176.746514 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60939.383069 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60939.383069 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34215.212681 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37499.907485 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40694.012346 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31542.063292 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35735.769518 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46447.148846 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37664.129796 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.180069 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 44752.586702 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59843.308887 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31713.378069 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31713.378069 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18893.060279 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18893.060279 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 857499.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 857499.800000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 49248.958770 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 49248.958770 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29602.674527 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33120.767364 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33120.767364 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 64362.331558 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 64362.331558 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 34034.379570 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 42550.745181 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 47939.449004 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29602.674527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36358.697069 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59843.308887 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41333.361365 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174673.298083 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174504.103217 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178060.978427 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178060.978427 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156750.379006 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156635.580875 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162122.831625 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162122.831625 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132766.304348 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 176327.105228 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 176236.913175 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 159314.610886 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 159248.037505 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 30858357 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15723821 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2528 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1980391 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1980008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 383 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 850137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14487242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 21647 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 21647 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4268815 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 11821046 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2688015 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 913599 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 423664 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342986 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 458900 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1168045 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1089891 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9966353 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4640105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 517058 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 511224 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 29897221 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16450144 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405579 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179409 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 47932353 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1275569664 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 629289128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1559696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4501408 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1910919896 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6428198 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 22587485 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.100846 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.301181 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 29757775 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15206900 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096240 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095918 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 322 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 863744 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 13939008 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 17467 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 17467 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4436321 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 11191891 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2888082 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 986942 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 436269 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 490098 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1199193 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1126648 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9231824 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4839539 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 455831 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 448771 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27695142 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16951918 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371352 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1238709 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 46257121 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1181646464 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 652642726 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1414024 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4710280 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1840413494 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6842316 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22455736 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.107935 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.310344 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 20310003 89.92% 89.92% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2277099 10.08% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 383 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 20032307 89.21% 89.21% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2423107 10.79% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 322 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 22587485 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 30765191484 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 22455736 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 29622476486 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 188815582 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 182393833 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 14953353610 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 13851399924 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7474900412 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7774596662 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 210684864 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 194664868 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 616864733 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 650073200 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40414 # Transaction distribution -system.iobus.trans_dist::ReadResp 40414 # Transaction distribution -system.iobus.trans_dist::WriteReq 136987 # Transaction distribution -system.iobus.trans_dist::WriteResp 136987 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47846 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40417 # Transaction distribution +system.iobus.trans_dist::ReadResp 40417 # Transaction distribution +system.iobus.trans_dist::WriteReq 136988 # Transaction distribution +system.iobus.trans_dist::WriteResp 136988 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47856 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2313,13 +2334,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122988 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231734 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231734 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122998 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231732 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354802 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47866 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354810 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47876 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2332,792 +2353,791 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156003 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156013 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513377 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47239500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513379 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47192501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 315000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26112500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26190001 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36405000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36429000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566670204 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568769538 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92988000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92997000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148174000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148172000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115848 # number of replacements -system.iocache.tags.tagsinuse 11.264479 # Cycle average of tags in use -system.iocache.tags.total_refs 11 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115864 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000095 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9145999585000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.415083 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.849396 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463443 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.240587 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.704030 # Average percentage of cache occupancy +system.iocache.tags.replacements 115847 # number of replacements +system.iocache.tags.tagsinuse 11.301670 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115863 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9145489939000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.832621 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.469049 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.239539 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.466816 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706354 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043144 # Number of tag accesses -system.iocache.tags.data_accesses 1043144 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 6 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 6 # number of WriteLineReq hits +system.iocache.tags.tag_accesses 1043151 # Number of tag accesses +system.iocache.tags.data_accesses 1043151 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8882 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8919 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106978 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106978 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8883 # number of demand (read+write) misses -system.iocache.demand_misses::total 8923 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8882 # number of demand (read+write) misses +system.iocache.demand_misses::total 8922 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8883 # number of overall misses -system.iocache.overall_misses::total 8923 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5243500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1665415552 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1670659052 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8882 # number of overall misses +system.iocache.overall_misses::total 8922 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1701700997 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1706898997 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 14002624152 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 14002624152 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5612500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1665415552 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1671028052 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5612500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1665415552 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1671028052 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13567134541 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13567134541 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1701700997 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1707267997 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1701700997 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1707267997 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8882 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8919 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8883 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8923 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8882 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8922 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8883 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8923 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8882 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8922 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses -system.iocache.WriteLineReq_miss_rate::realview.ide 0.999944 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 0.999944 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141716.216216 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 187483.457391 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 187293.615695 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 191589.844292 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 191377.844714 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130892.558769 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130892.558769 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 187271.999552 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 140312.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 187483.457391 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 187271.999552 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35141 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126814.612849 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126814.612849 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 191354.852836 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 191589.844292 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 191354.852836 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34809 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3655 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3501 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.614501 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.942588 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106943 # number of writebacks -system.iocache.writebacks::total 106943 # number of writebacks +system.iocache.writebacks::writebacks 106950 # number of writebacks +system.iocache.writebacks::total 106950 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8882 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8919 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 106978 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 106978 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8883 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8923 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8882 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8922 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8883 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8923 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3393500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1221265552 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1224659052 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8882 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8922 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1257600997 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1260948997 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8653724152 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8653724152 # number of WriteLineReq MSHR miss cycles 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+system.iocache.demand_mshr_miss_latency::realview.ide 1257600997 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1261167997 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1257600997 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1261167997 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999944 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.999944 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91716.216216 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137483.457391 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 137293.615695 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141589.844292 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 141377.844714 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80892.558769 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80892.558769 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90312.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 137483.457391 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 137271.999552 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76754.099398 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76754.099398 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141589.844292 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 141354.852836 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1253630 # number of replacements -system.l2c.tags.tagsinuse 63075.564404 # Cycle average of tags in use -system.l2c.tags.total_refs 6221998 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1313632 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.736485 # Average number of references to valid blocks. +system.l2c.tags.replacements 1465460 # number of replacements +system.l2c.tags.tagsinuse 62985.288046 # Cycle average of tags in use +system.l2c.tags.total_refs 6746847 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1525111 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.423840 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 23067.685004 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 146.868876 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 206.473413 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5441.439609 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6307.681817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8428.958067 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 140.047033 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 198.225362 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4720.872050 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6856.377655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 7560.935517 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.351985 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002241 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003151 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.083030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.096248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.128616 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002137 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003025 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.072035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.104620 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.115371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.962457 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9537 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 45 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 233 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2638 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 11674 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 35545 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.145523 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.766373 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 75571866 # Number of tag accesses -system.l2c.tags.data_accesses 75571866 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2585563 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2585563 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 160084 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 122219 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 282303 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 41093 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 37320 # number of SCUpgradeReq hits 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523825 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 313790 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 3038451 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5942 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3808 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 649495 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 760222 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 326607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6405 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 608519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 700016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 313790 # number of demand (read+write) hits -system.l2c.demand_hits::total 3379615 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5942 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3808 # number of overall hits -system.l2c.overall_hits::cpu0.inst 649495 # number of overall hits -system.l2c.overall_hits::cpu0.data 760222 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 326607 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6405 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4811 # number of overall hits -system.l2c.overall_hits::cpu1.inst 608519 # number of overall hits -system.l2c.overall_hits::cpu1.data 700016 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 313790 # number of overall hits -system.l2c.overall_hits::total 3379615 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 64947 # number of UpgradeReq misses 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accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.182795 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164892 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210186 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.295395 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.212217 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.253815 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097663 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.426856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403848 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.280270 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.338250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068377 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.266230 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.445078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.295395 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70665.648541 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70510.844375 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70588.101488 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73697.624453 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73499.423401 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73602.977930 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129628.448141 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 126131.309034 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 128788.187628 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129429.419995 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130411.611492 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144136.486641 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130465.013896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130935.623936 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124440.857896 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129582.587544 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 157062.022343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130793.143035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130652.621124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124595.578948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127943.621161 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157907.439107 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 137541.973961 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153344.559251 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168601.820174 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156682.699511 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130693.494077 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 151451.217285 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161054.718899 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156910.864827 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138760.548387 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 130189.676437 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164179.590555 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145115.792122 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155533.936466 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152369.857434 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166307.988812 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111728.260870 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 158817.140280 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 138452.781060 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 141794.024977 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 137723.145408 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 90579 # Transaction distribution -system.membus.trans_dist::ReadResp 797028 # Transaction distribution -system.membus.trans_dist::WriteReq 38077 # Transaction distribution -system.membus.trans_dist::WriteResp 38077 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1072761 # Transaction distribution -system.membus.trans_dist::CleanEvict 234796 # Transaction distribution -system.membus.trans_dist::UpgradeReq 432847 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 303767 # Transaction distribution -system.membus.trans_dist::UpgradeResp 155875 # Transaction distribution +system.membus.trans_dist::ReadReq 91058 # Transaction distribution +system.membus.trans_dist::ReadResp 962815 # Transaction distribution +system.membus.trans_dist::WriteReq 38515 # Transaction distribution +system.membus.trans_dist::WriteResp 38515 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1239858 # Transaction distribution +system.membus.trans_dist::CleanEvict 269903 # Transaction distribution +system.membus.trans_dist::UpgradeReq 432314 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 322959 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 628014 # Transaction distribution -system.membus.trans_dist::ReadExResp 607752 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 706453 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106976 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106976 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122988 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 660243 # Transaction distribution +system.membus.trans_dist::ReadExResp 640684 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 871757 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122998 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24302 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4826718 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4974060 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5316946 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156003 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5285035 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5434211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5672771 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156013 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 148677184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 148883115 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7268800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 156151915 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 604039 # Total snoops (count) -system.membus.snoop_fanout::samples 3616779 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52252 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172058368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 172267957 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7280448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 179548405 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 621430 # Total snoops (count) +system.membus.snoop_fanout::samples 4033661 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3616779 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4033661 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3616779 # Request fanout histogram -system.membus.reqLayer0.occupancy 110163500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4033661 # Request fanout histogram +system.membus.reqLayer0.occupancy 110232498 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20375999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21930998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7677665405 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8790771874 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7558802547 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8289711005 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 229140974 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45511990 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3171,52 +3191,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11857284 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6410159 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2032721 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 132920 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 118959 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13961 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 90581 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4604579 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38077 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38077 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3658344 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1620073 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 706187 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 382180 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1088365 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1100091 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1100091 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4521240 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106976 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8903542 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7167245 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16070787 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267379155 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202223448 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 469602603 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2985982 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8314965 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.369241 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486066 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 12834320 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6946519 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2149909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 154845 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 139190 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 15655 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 91060 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4987176 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38515 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38515 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4108038 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 3110241 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 736356 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 408827 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1145183 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1157626 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1157626 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4903350 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10442900 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8319786 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 18762686 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 296101599 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 218919254 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 515020853 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3228731 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9024232 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.357725 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482936 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5258700 63.24% 63.24% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3042304 36.59% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13961 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5811691 64.40% 64.40% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3196886 35.43% 99.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 15655 0.17% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8314965 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8970776631 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9024232 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9776043593 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2598924 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2607881 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5002984602 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5412935477 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4113788553 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4393187885 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index 46040b9b9..1a67ea010 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.667482 # Number of seconds simulated -sim_ticks 51667481628000 # Number of ticks simulated -final_tick 51667481628000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.667476 # Number of seconds simulated +sim_ticks 51667476471000 # Number of ticks simulated +final_tick 51667476471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173876 # Simulator instruction rate (inst/s) -host_op_rate 204307 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9745015544 # Simulator tick rate (ticks/s) -host_mem_usage 682548 # Number of bytes of host memory used -host_seconds 5301.94 # Real time elapsed on the host -sim_insts 921877826 # Number of instructions simulated -sim_ops 1083223459 # Number of ops (including micro ops) simulated +host_inst_rate 274767 # Simulator instruction rate (inst/s) +host_op_rate 322852 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15389929524 # Simulator tick rate (ticks/s) +host_mem_usage 683068 # Number of bytes of host memory used +host_seconds 3357.23 # Real time elapsed on the host +sim_insts 922453344 # Number of instructions simulated +sim_ops 1083887959 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 355328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 294720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10221184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 93611976 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 405568 # Number of bytes read from this memory -system.physmem.bytes_read::total 104888776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10221184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10221184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 87378688 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 349632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 295488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10205120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 93689288 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 408000 # Number of bytes read from this memory +system.physmem.bytes_read::total 104947528 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10205120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10205120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 87402048 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 87399268 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 5552 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 159706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1462700 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6337 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1638900 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1365292 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 87422628 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 5463 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4617 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 159455 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1463908 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1639818 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1365657 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1367865 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 6877 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1811816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2030073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1691174 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1368230 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 6767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5719 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 197515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1813313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7897 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2031211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 197515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 197515 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1691626 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1691572 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1691174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 6877 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1812214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3721645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1638900 # Number of read requests accepted -system.physmem.writeReqs 1367865 # Number of write requests accepted -system.physmem.readBursts 1638900 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1367865 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104832704 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 56896 # Total number of bytes read from write queue -system.physmem.bytesWritten 87398080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 104888776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 87399268 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 889 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1692024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1691626 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 6767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5719 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 197515 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1813711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3723235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1639818 # Number of read requests accepted +system.physmem.writeReqs 1368230 # Number of write requests accepted +system.physmem.readBursts 1639818 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1368230 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 104895040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 53312 # Total number of bytes read from write queue +system.physmem.bytesWritten 87421376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 104947528 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 87422628 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 833 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2255 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 381658 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 98450 # Per bank write bursts -system.physmem.perBankRdBursts::1 107251 # Per bank write bursts -system.physmem.perBankRdBursts::2 99188 # Per bank write bursts -system.physmem.perBankRdBursts::3 95203 # Per bank write bursts -system.physmem.perBankRdBursts::4 99955 # Per bank write bursts -system.physmem.perBankRdBursts::5 109194 # Per bank write bursts -system.physmem.perBankRdBursts::6 96838 # Per bank write bursts -system.physmem.perBankRdBursts::7 98371 # Per bank write bursts -system.physmem.perBankRdBursts::8 94736 # Per bank write bursts -system.physmem.perBankRdBursts::9 155242 # Per bank write bursts -system.physmem.perBankRdBursts::10 99865 # Per bank write bursts -system.physmem.perBankRdBursts::11 104170 # Per bank write bursts -system.physmem.perBankRdBursts::12 95009 # Per bank write bursts -system.physmem.perBankRdBursts::13 96057 # Per bank write bursts -system.physmem.perBankRdBursts::14 92133 # Per bank write bursts -system.physmem.perBankRdBursts::15 96349 # Per bank write bursts -system.physmem.perBankWrBursts::0 83734 # Per bank write bursts -system.physmem.perBankWrBursts::1 87693 # Per bank write bursts -system.physmem.perBankWrBursts::2 84639 # Per bank write bursts -system.physmem.perBankWrBursts::3 83186 # Per bank write bursts -system.physmem.perBankWrBursts::4 87134 # Per bank write bursts -system.physmem.perBankWrBursts::5 92701 # Per bank write bursts -system.physmem.perBankWrBursts::6 83787 # Per bank write bursts -system.physmem.perBankWrBursts::7 85921 # Per bank write bursts -system.physmem.perBankWrBursts::8 83051 # Per bank write bursts -system.physmem.perBankWrBursts::9 88932 # Per bank write bursts -system.physmem.perBankWrBursts::10 85543 # Per bank write bursts -system.physmem.perBankWrBursts::11 89009 # Per bank write bursts -system.physmem.perBankWrBursts::12 82580 # Per bank write bursts -system.physmem.perBankWrBursts::13 83353 # Per bank write bursts -system.physmem.perBankWrBursts::14 81127 # Per bank write bursts -system.physmem.perBankWrBursts::15 83205 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 99403 # Per bank write bursts +system.physmem.perBankRdBursts::1 105228 # Per bank write bursts +system.physmem.perBankRdBursts::2 100047 # Per bank write bursts +system.physmem.perBankRdBursts::3 95494 # Per bank write bursts +system.physmem.perBankRdBursts::4 102929 # Per bank write bursts +system.physmem.perBankRdBursts::5 111535 # Per bank write bursts +system.physmem.perBankRdBursts::6 97078 # Per bank write bursts +system.physmem.perBankRdBursts::7 98055 # Per bank write bursts +system.physmem.perBankRdBursts::8 92724 # Per bank write bursts +system.physmem.perBankRdBursts::9 154002 # Per bank write bursts +system.physmem.perBankRdBursts::10 99475 # Per bank write bursts +system.physmem.perBankRdBursts::11 105000 # Per bank write bursts +system.physmem.perBankRdBursts::12 94287 # Per bank write bursts +system.physmem.perBankRdBursts::13 95690 # Per bank write bursts +system.physmem.perBankRdBursts::14 90913 # Per bank write bursts +system.physmem.perBankRdBursts::15 97125 # Per bank write bursts +system.physmem.perBankWrBursts::0 83951 # Per bank write bursts +system.physmem.perBankWrBursts::1 87043 # Per bank write bursts +system.physmem.perBankWrBursts::2 85245 # Per bank write bursts +system.physmem.perBankWrBursts::3 83208 # Per bank write bursts +system.physmem.perBankWrBursts::4 88814 # Per bank write bursts +system.physmem.perBankWrBursts::5 93904 # Per bank write bursts +system.physmem.perBankWrBursts::6 83820 # Per bank write bursts +system.physmem.perBankWrBursts::7 85248 # Per bank write bursts +system.physmem.perBankWrBursts::8 81467 # Per bank write bursts +system.physmem.perBankWrBursts::9 88240 # Per bank write bursts +system.physmem.perBankWrBursts::10 85354 # Per bank write bursts +system.physmem.perBankWrBursts::11 89463 # Per bank write bursts +system.physmem.perBankWrBursts::12 82403 # Per bank write bursts +system.physmem.perBankWrBursts::13 83577 # Per bank write bursts +system.physmem.perBankWrBursts::14 80367 # Per bank write bursts +system.physmem.perBankWrBursts::15 83855 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry -system.physmem.totGap 51667479848500 # Total gap between requests +system.physmem.numWrRetry 37 # Number of times write queue was full causing retry +system.physmem.totGap 51667474307000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1638885 # Read request sizes (log2) +system.physmem.readPktSize::6 1639803 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1365292 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1312759 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 318962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 959 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 673 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1365657 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1314237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 318417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 537 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,117 +159,124 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 65606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 80418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 82482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 82286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 83182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 85216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 84794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 84174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 91789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 82005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 83224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 79922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 647624 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.824083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 173.411154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.640423 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 254912 39.36% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 156143 24.11% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 60053 9.27% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34984 5.40% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25631 3.96% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 18733 2.89% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14068 2.17% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 12825 1.98% 89.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 70275 10.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 647624 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79231 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.673638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 283.409553 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 79228 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 14698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 67736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 80790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 82454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 81257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 81296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 82033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 83039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 83634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 86681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 83880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 94578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 83323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 84131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 81331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 646147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.635603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 173.901229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.036577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 253673 39.26% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 155474 24.06% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 60360 9.34% 72.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 34960 5.41% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25496 3.95% 82.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 18768 2.90% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 14047 2.17% 87.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 13088 2.03% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70281 10.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 646147 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 79019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.741467 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 283.796699 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 79016 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79231 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79231 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.235615 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.796201 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.303380 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 76926 97.09% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 319 0.40% 97.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 70 0.09% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 321 0.41% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 45 0.06% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 342 0.43% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 202 0.25% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 22 0.03% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 52 0.07% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 126 0.16% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 31 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 49 0.06% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 483 0.61% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 14 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 128 0.16% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 11 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79231 # Writes before turning the bus around for reads -system.physmem.totQLat 26417109815 # Total ticks spent queuing -system.physmem.totMemAccLat 57129816065 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8190055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16127.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 79019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 79019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.286463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.794878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.949851 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 76956 97.39% 97.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 330 0.42% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 47 0.06% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 101 0.13% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 35 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 85 0.11% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 245 0.31% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 21 0.03% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 324 0.41% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 69 0.09% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 26 0.03% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 53 0.07% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 312 0.39% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 39 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 28 0.04% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 118 0.15% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.22% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 6 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 79019 # Writes before turning the bus around for reads +system.physmem.totQLat 26490910104 # Total ticks spent queuing +system.physmem.totMemAccLat 57221878854 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8194925000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16163.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34877.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34913.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s @@ -279,40 +286,40 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.24 # Average write queue length when enqueuing -system.physmem.readRowHits 1331553 # Number of row buffer hits during reads -system.physmem.writeRowHits 1024428 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.02 # Row buffer hit rate for writes -system.physmem.avgGap 17183743.94 # Average gap between requests -system.physmem.pageHitRate 78.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2488253040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1357677750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6274663200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4463391600 # Energy for write commands per rank (pJ) +system.physmem.avgWrQLen 25.57 # Average write queue length when enqueuing +system.physmem.readRowHits 1332864 # Number of row buffer hits during reads +system.physmem.writeRowHits 1025932 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.11 # Row buffer hit rate for writes +system.physmem.avgGap 17176412.85 # Average gap between requests +system.physmem.pageHitRate 78.50 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2496243960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1362037875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6316198200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4479189840 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1321909933950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29840915681250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34552077975270 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.739417 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49642099754241 # Time in different power states +system.physmem_0.actBackEnergy 1323055672425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29839910639250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34552288356030 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.743489 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49640417958020 # Time in different power states system.physmem_0.memoryStateTime::REF 1725290580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 300090521259 # Time in different power states +system.physmem_0.memoryStateTime::ACT 301767793230 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2407784400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1313771250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6501775800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4385664000 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 2388627360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1303318500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6467877000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4372224480 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 3374668374480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1318271769585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29844107045250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34551656184765 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.731253 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49647373564820 # Time in different power states +system.physmem_1.actBackEnergy 1316624734350 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29845551821250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34551376977420 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.725849 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49649780004526 # Time in different power states system.physmem_1.memoryStateTime::REF 1725290580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 294812186430 # Time in different power states +system.physmem_1.memoryStateTime::ACT 292405760474 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -336,15 +343,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 252485837 # Number of BP lookups -system.cpu.branchPred.condPredicted 176433570 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11949823 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 185211535 # Number of BTB lookups -system.cpu.branchPred.BTBHits 131480802 # Number of BTB hits +system.cpu.branchPred.lookups 252598760 # Number of BP lookups +system.cpu.branchPred.condPredicted 176508431 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11957032 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 185598793 # Number of BTB lookups +system.cpu.branchPred.BTBHits 131565493 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.989532 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30949299 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2133828 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.887041 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30959293 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2131771 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -375,63 +382,63 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 560555 # Table walker walks requested -system.cpu.dtb.walker.walksLong 560555 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20820 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178520 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 560555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 560555 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 560555 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 199340 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 27109.310725 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 22940.792106 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 20958.396260 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 197062 98.86% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 8 0.00% 98.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1944 0.98% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 53 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 116 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 50 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 75 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 560635 # Table walker walks requested +system.cpu.dtb.walker.walksLong 560635 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20884 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178593 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 560635 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 560635 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 560635 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 199477 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 26985.070961 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 22842.355807 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20873.513445 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 197251 98.88% 98.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 98.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1888 0.95% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 57 0.03% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 46 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 97 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 199340 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 199477 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples -1569959592 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 -1569959592 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total -1569959592 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 178521 89.56% 89.56% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20820 10.44% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 199341 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560555 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 178594 89.53% 89.53% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 20884 10.47% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 199478 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560635 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560555 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199341 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560635 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199478 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199341 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 759896 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199478 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 760113 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 178230117 # DTB read hits -system.cpu.dtb.read_misses 462749 # DTB read misses -system.cpu.dtb.write_hits 157902959 # DTB write hits -system.cpu.dtb.write_misses 97806 # DTB write misses +system.cpu.dtb.read_hits 178339564 # DTB read hits +system.cpu.dtb.read_misses 462901 # DTB read misses +system.cpu.dtb.write_hits 158016400 # DTB write hits +system.cpu.dtb.write_misses 97734 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 78363 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1414 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14783 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 78401 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1394 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14946 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23068 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 178692866 # DTB read accesses -system.cpu.dtb.write_accesses 158000765 # DTB write accesses +system.cpu.dtb.perms_faults 23063 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 178802465 # DTB read accesses +system.cpu.dtb.write_accesses 158114134 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 336133076 # DTB hits -system.cpu.dtb.misses 560555 # DTB misses -system.cpu.dtb.accesses 336693631 # DTB accesses +system.cpu.dtb.hits 336355964 # DTB hits +system.cpu.dtb.misses 560635 # DTB misses +system.cpu.dtb.accesses 336916599 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -461,42 +468,47 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 134868 # Table walker walks requested -system.cpu.itb.walker.walksLong 134868 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1077 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 117569 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 134868 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 134868 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 134868 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 118646 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 30429.546719 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 26050.717125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 23099.528150 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 116148 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.90% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2266 1.91% 99.81% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 70 0.06% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 116 0.10% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 118646 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 134932 # Table walker walks requested +system.cpu.itb.walker.walksLong 134932 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 117658 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 134932 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 134932 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 134932 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 118737 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 30245.892182 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 25862.614601 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 23195.505917 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 58684 49.42% 49.42% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 57510 48.43% 97.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 2 0.00% 97.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 7 0.01% 97.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 1905 1.60% 99.47% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 424 0.36% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 23 0.02% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 17 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 94 0.08% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 21 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 17 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 17 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 118737 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples -1570990092 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 -1570990092 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total -1570990092 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 117569 99.09% 99.09% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1077 0.91% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 118646 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 117658 99.09% 99.09% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1079 0.91% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 118737 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134868 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 134868 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134932 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 134932 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118646 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 118646 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 253514 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 438855637 # ITB inst hits -system.cpu.itb.inst_misses 134868 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118737 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 118737 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 253669 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 439091546 # ITB inst hits +system.cpu.itb.inst_misses 134932 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -505,140 +517,140 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 45299 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56516 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 56478 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 359281 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 354973 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 438990505 # ITB inst accesses -system.cpu.itb.hits 438855637 # DTB hits -system.cpu.itb.misses 134868 # DTB misses -system.cpu.itb.accesses 438990505 # DTB accesses -system.cpu.numCycles 2563496972 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 439226478 # ITB inst accesses +system.cpu.itb.hits 439091546 # DTB hits +system.cpu.itb.misses 134932 # DTB misses +system.cpu.itb.accesses 439226478 # DTB accesses +system.cpu.numCycles 2564620605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 921877826 # Number of instructions committed -system.cpu.committedOps 1083223459 # Number of ops (including micro ops) committed -system.cpu.discardedOps 92885181 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7623 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100772604966 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.780734 # CPI: cycles per instruction -system.cpu.ipc 0.359617 # IPC: instructions per cycle +system.cpu.committedInsts 922453344 # Number of instructions committed +system.cpu.committedOps 1083887959 # Number of ops (including micro ops) committed +system.cpu.discardedOps 92875630 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100771468164 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.780217 # CPI: cycles per instruction +system.cpu.ipc 0.359684 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16483 # number of quiesce instructions executed -system.cpu.tickCycles 1740911334 # Number of cycles that the object actually ticked -system.cpu.idleCycles 822585638 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 10734176 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.930080 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320289523 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10734688 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.836873 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 16482 # number of quiesce instructions executed +system.cpu.tickCycles 1741581813 # Number of cycles that the object actually ticked +system.cpu.idleCycles 823038792 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 10731841 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.930081 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 320513038 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10732353 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.864191 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7087675500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.930080 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.930081 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1345515853 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1345515853 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 163941297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 163941297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 147439641 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 147439641 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 511618 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 511618 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 335027 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 335027 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3852667 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3852667 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4161339 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4161339 # number of StoreCondReq hits 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SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1398816 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1238819 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1238819 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 310200 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 310200 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 10503518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 10503518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 11903656 # number of overall misses -system.cpu.dcache.overall_misses::total 11903656 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 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-system.cpu.dcache.SoftPFReq_accesses::total 1911756 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574681 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1574681 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4163047 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4163047 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4161340 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4161340 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321884456 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321884456 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 323796212 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 323796212 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037398 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027275 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027275 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732383 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.732383 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787241 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.787241 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074556 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074556 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 317353768000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 317353768000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 317353768000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 317353768000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 170415872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 170415872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 151684622 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 151684622 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911159 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1911159 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574679 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1574679 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4164860 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4164860 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4163152 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4163152 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 322100494 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 322100494 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324011653 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324011653 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027232 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027232 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.731920 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.731920 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786712 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786712 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074480 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074480 # miss rate for LoadLockedReq accesses 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# average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68237.711490 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16540.700110 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16540.700110 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032603 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032603 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036728 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036728 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18428.434171 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18428.434171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48406.116003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48406.116003 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68255.980898 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68255.980898 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16569.045777 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16569.045777 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30186.661317 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30186.661317 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26636.030183 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26636.030183 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30220.064208 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30220.064208 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26667.841545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26667.841545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -647,155 +659,155 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8245378 # number of writebacks -system.cpu.dcache.writebacks::total 8245378 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 770684 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 770684 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1822945 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1822945 # number of WriteReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69756 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 69756 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2593629 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2593629 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2593629 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2593629 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5598669 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5598669 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2311220 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2311220 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1392587 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1392587 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1239502 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1239502 # number of WriteLineReq MSHR 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# number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7909146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9300406 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9300406 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96111391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 96111391500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 105871130000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 105871130000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26586103000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26586103000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83345106500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83345106500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3481164500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3481164500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 96067975500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 96067975500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106000226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 106000226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26589323500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26589323500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83310681500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83310681500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3491728500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3491728500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 201982521500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 201982521500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228568624500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 228568624500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197557500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197557500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207394000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207394000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404951500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404951500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032873 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032873 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015248 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015248 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728433 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728433 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787145 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787145 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057800 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057800 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202068202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 202068202000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228657525500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 228657525500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6197287500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6197287500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6207449000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6207449000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12404736500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12404736500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.727967 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.727967 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786615 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786615 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057917 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057917 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024574 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024574 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028729 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028729 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17166.828669 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17166.828669 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45807.465321 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45807.465321 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19091.161270 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19091.161270 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67240.800338 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67240.800338 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14467.237266 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14467.237266 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024555 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024555 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028704 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028704 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17154.701544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17154.701544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45906.423204 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45906.423204 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19111.685451 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19111.685451 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67258.390478 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67258.390478 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14475.406064 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14475.406064 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25535.443228 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25535.443228 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24570.729825 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24570.729825 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183920.156097 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183920.156097 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184162.879013 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184162.879013 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184041.533760 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184041.533760 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25548.675167 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25548.675167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24585.757385 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24585.757385 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183912.143514 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183912.143514 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184164.510770 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184164.510770 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184038.343991 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184038.343991 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24166189 # number of replacements +system.cpu.icache.tags.replacements 24176986 # number of replacements system.cpu.icache.tags.tagsinuse 511.872408 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 414317362 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24166701 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.144142 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 414546703 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24177498 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.145972 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 39504620500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.872408 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 462650783 # Number of tag accesses -system.cpu.icache.tags.data_accesses 462650783 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 414317362 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 414317362 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 414317362 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 414317362 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 414317362 # number of overall hits -system.cpu.icache.overall_hits::total 414317362 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24166711 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24166711 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24166711 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24166711 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24166711 # number of overall misses -system.cpu.icache.overall_misses::total 24166711 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 327482385000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 327482385000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 327482385000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 327482385000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 327482385000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 327482385000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 438484073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 438484073 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 438484073 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 438484073 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 438484073 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 438484073 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055114 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.055114 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.055114 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.055114 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.055114 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.055114 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13550.970382 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13550.970382 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13550.970382 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13550.970382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13550.970382 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13550.970382 # average overall miss latency +system.cpu.icache.tags.tag_accesses 462901718 # Number of tag accesses +system.cpu.icache.tags.data_accesses 462901718 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 414546703 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 414546703 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 414546703 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 414546703 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 414546703 # number of overall hits +system.cpu.icache.overall_hits::total 414546703 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24177508 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24177508 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24177508 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24177508 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24177508 # number of overall misses +system.cpu.icache.overall_misses::total 24177508 # number of overall misses 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-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124754.854431 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124754.854431 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128793.573193 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128793.573193 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 127369.163952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122294.052484 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123354.989764 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123282.400322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126824.117435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127369.163952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122294.052484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123354.989764 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123282.400322 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122649.023309 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122649.023309 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122367.838615 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122367.838615 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124789.860331 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124789.860331 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128850.667834 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128850.667834 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127444.169870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126572.233052 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122367.838615 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123369.027344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123302.213926 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171418.360685 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136180.714136 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172644.974189 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172644.974189 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171410.437131 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 136177.609702 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172646.576277 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172646.576277 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.930624 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172031.749329 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146447.557471 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172028.589232 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 146445.778201 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 70542716 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 35641283 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4403 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2298 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 70561172 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 35651281 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4392 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1728705 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 33127830 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1729330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33139930 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 9610686 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24162502 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2728698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 47872 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 9609467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24176986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2728127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 47900 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 47873 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2263598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2263598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 24166711 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7240510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1346166 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1239502 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72600538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32434260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 690132 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2164681 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 107889611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3096417152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135639442 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2297512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7399400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4241753506 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2152838 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 38433190 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018207 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.133699 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 47901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2261407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2261407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 24177508 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7241194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1345330 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1238666 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72636616 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32428005 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 687897 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2160128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 107912646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3098035136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1135439954 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2278088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7359520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 4243112698 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2160696 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 38442129 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018241 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.133822 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 37733441 98.18% 98.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 699749 1.82% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 37740909 98.18% 98.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 701220 1.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 38433190 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 68234466996 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 38442129 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 68252447493 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1477892 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1464392 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 36335720582 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 36351871671 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14937837927 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14935181922 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 402991902 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 403175920 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1239794423 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1240232910 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40325 # Transaction distribution -system.iobus.trans_dist::ReadResp 40325 # Transaction distribution +system.iobus.trans_dist::ReadReq 40322 # Transaction distribution +system.iobus.trans_dist::ReadResp 40322 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1252,11 +1264,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353786 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1271,12 +1283,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42167500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492360 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42165000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1298,73 +1310,73 @@ system.iobus.reqLayer16.occupancy 16000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25751500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25683500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 34145500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34144500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565709151 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567247076 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147762000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115486 # number of replacements -system.iocache.tags.tagsinuse 10.440009 # Cycle average of tags in use +system.iocache.tags.replacements 115483 # number of replacements +system.iocache.tags.tagsinuse 10.440004 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13160148730000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.520855 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.919154 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13160148727000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.520843 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.919161 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.432447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.432448 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652500 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039893 # Number of tag accesses -system.iocache.tags.data_accesses 1039893 # Number of data accesses +system.iocache.tags.tag_accesses 1039866 # Number of tag accesses +system.iocache.tags.data_accesses 1039866 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses -system.iocache.demand_misses::total 8880 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8840 # number of overall misses -system.iocache.overall_misses::total 8880 # number of overall misses +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1638496114 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1643565614 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1647976559 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1653046059 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13864020537 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13864020537 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13408898017 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13408898017 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1638496114 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1643916614 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1647976559 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1653397059 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1638496114 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1643916614 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1647976559 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1653397059 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1379,54 +1391,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 185350.239140 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 185148.768052 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186485.974765 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186279.700135 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129978.441995 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129978.441995 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125711.561698 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125711.561698 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 185350.239140 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185125.744820 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186256.286921 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 185350.239140 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185125.744820 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33657 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186485.974765 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186256.286921 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33362 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3502 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.610794 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.720862 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1196496114 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1199715614 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206126559 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1209346059 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530820537 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8530820537 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8070540171 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8070540171 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1196496114 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1199916614 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1206126559 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1209547059 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1196496114 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1199916614 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1206126559 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1209547059 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1441,72 +1453,71 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135350.239140 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 135148.768052 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136485.974765 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136279.700135 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79978.441995 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.441995 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75663.205683 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75663.205683 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 135350.239140 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135125.744820 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 135350.239140 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135125.744820 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136485.974765 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136256.286921 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 86006 # Transaction distribution -system.membus.trans_dist::ReadResp 527021 # Transaction distribution +system.membus.trans_dist::ReadResp 526304 # Transaction distribution system.membus.trans_dist::WriteReq 33706 # Transaction distribution system.membus.trans_dist::WriteResp 33706 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1365292 # Transaction distribution -system.membus.trans_dist::CleanEvict 236782 # Transaction distribution -system.membus.trans_dist::UpgradeReq 38218 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1365657 # Transaction distribution +system.membus.trans_dist::CleanEvict 238956 # Transaction distribution +system.membus.trans_dist::UpgradeReq 38308 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 38219 # Transaction distribution -system.membus.trans_dist::ReadExReq 1148769 # Transaction distribution -system.membus.trans_dist::ReadExResp 1148769 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 441015 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 1150364 # Transaction distribution +system.membus.trans_dist::ReadExResp 1150364 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 440298 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4836672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4966324 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5307628 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4800126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4929778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237399 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5167177 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185058092 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185228498 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7229952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7229952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192458450 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3204 # Total snoops (count) -system.membus.snoop_fanout::samples 3459197 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185137772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185308178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7232384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 192540562 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3164 # Total snoops (count) +system.membus.snoop_fanout::samples 3459998 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3459197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3459998 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3459197 # Request fanout histogram -system.membus.reqLayer0.occupancy 102492500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3459998 # Request fanout histogram +system.membus.reqLayer0.occupancy 102421000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5497000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5498500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9250665962 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9252697708 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8763516637 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8691723530 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227782427 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44915426 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index e8c18c866..d62e25962 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.291806 # Number of seconds simulated -sim_ticks 51291805611000 # Number of ticks simulated -final_tick 51291805611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.331525 # Number of seconds simulated +sim_ticks 51331524771000 # Number of ticks simulated +final_tick 51331524771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109804 # Simulator instruction rate (inst/s) -host_op_rate 129027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6627600062 # Simulator tick rate (ticks/s) -host_mem_usage 686384 # Number of bytes of host memory used -host_seconds 7739.12 # Real time elapsed on the host -sim_insts 849784302 # Number of instructions simulated -sim_ops 998554740 # Number of ops (including micro ops) simulated +host_inst_rate 146792 # Simulator instruction rate (inst/s) +host_op_rate 172478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8901142339 # Simulator tick rate (ticks/s) +host_mem_usage 687432 # Number of bytes of host memory used +host_seconds 5766.85 # Real time elapsed on the host +sim_insts 846524467 # Number of instructions simulated +sim_ops 994654061 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 234176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 229184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5702880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74235720 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 438720 # Number of bytes read from this memory -system.physmem.bytes_read::total 80840680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5702880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5702880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69030592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 205568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 197440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5696288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 72187912 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428288 # Number of bytes read from this memory +system.physmem.bytes_read::total 78715496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5696288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5696288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67280640 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69051172 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3659 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3581 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1159946 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6855 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1279101 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1078603 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67301220 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3212 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1127949 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1245895 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1051260 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1081176 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1447321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1576093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1345841 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1053833 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 110971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1406308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1533473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1310708 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1346242 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1345841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1447722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2922335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1279101 # Number of read requests accepted -system.physmem.writeReqs 1081176 # Number of write requests accepted -system.physmem.readBursts 1279101 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1081176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 81811968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50496 # Total number of bytes read from write queue -system.physmem.bytesWritten 69050112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 80840680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69051172 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 789 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 335568 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 76700 # Per bank write bursts -system.physmem.perBankRdBursts::1 81593 # Per bank write bursts -system.physmem.perBankRdBursts::2 83146 # Per bank write bursts -system.physmem.perBankRdBursts::3 75940 # Per bank write bursts -system.physmem.perBankRdBursts::4 76984 # Per bank write bursts -system.physmem.perBankRdBursts::5 83084 # Per bank write bursts -system.physmem.perBankRdBursts::6 76647 # Per bank write bursts -system.physmem.perBankRdBursts::7 76510 # Per bank write bursts -system.physmem.perBankRdBursts::8 74528 # Per bank write bursts -system.physmem.perBankRdBursts::9 104951 # Per bank write bursts -system.physmem.perBankRdBursts::10 78345 # Per bank write bursts -system.physmem.perBankRdBursts::11 82619 # Per bank write bursts -system.physmem.perBankRdBursts::12 77692 # Per bank write bursts -system.physmem.perBankRdBursts::13 79270 # Per bank write bursts -system.physmem.perBankRdBursts::14 75132 # Per bank write bursts -system.physmem.perBankRdBursts::15 75171 # Per bank write bursts -system.physmem.perBankWrBursts::0 64170 # Per bank write bursts -system.physmem.perBankWrBursts::1 68321 # Per bank write bursts -system.physmem.perBankWrBursts::2 70316 # Per bank write bursts -system.physmem.perBankWrBursts::3 66616 # Per bank write bursts -system.physmem.perBankWrBursts::4 66722 # Per bank write bursts -system.physmem.perBankWrBursts::5 70167 # Per bank write bursts -system.physmem.perBankWrBursts::6 65460 # Per bank write bursts -system.physmem.perBankWrBursts::7 67223 # Per bank write bursts -system.physmem.perBankWrBursts::8 64606 # Per bank write bursts -system.physmem.perBankWrBursts::9 72209 # Per bank write bursts -system.physmem.perBankWrBursts::10 66721 # Per bank write bursts -system.physmem.perBankWrBursts::11 70434 # Per bank write bursts -system.physmem.perBankWrBursts::12 67362 # Per bank write bursts -system.physmem.perBankWrBursts::13 68403 # Per bank write bursts -system.physmem.perBankWrBursts::14 65406 # Per bank write bursts -system.physmem.perBankWrBursts::15 64772 # Per bank write bursts +system.physmem.bw_write::total 1311109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1310708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1406708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2844582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1245895 # Number of read requests accepted +system.physmem.writeReqs 1053833 # Number of write requests accepted +system.physmem.readBursts 1245895 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1053833 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79684928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 52352 # Total number of bytes read from write queue +system.physmem.bytesWritten 67299776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78715496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67301220 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 818 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74822 # Per bank write bursts +system.physmem.perBankRdBursts::1 82180 # Per bank write bursts +system.physmem.perBankRdBursts::2 80987 # Per bank write bursts +system.physmem.perBankRdBursts::3 75462 # Per bank write bursts +system.physmem.perBankRdBursts::4 75477 # Per bank write bursts +system.physmem.perBankRdBursts::5 80130 # Per bank write bursts +system.physmem.perBankRdBursts::6 74577 # Per bank write bursts +system.physmem.perBankRdBursts::7 72890 # Per bank write bursts +system.physmem.perBankRdBursts::8 72311 # Per bank write bursts +system.physmem.perBankRdBursts::9 102827 # Per bank write bursts +system.physmem.perBankRdBursts::10 78128 # Per bank write bursts +system.physmem.perBankRdBursts::11 79408 # Per bank write bursts +system.physmem.perBankRdBursts::12 72963 # Per bank write bursts +system.physmem.perBankRdBursts::13 76387 # Per bank write bursts +system.physmem.perBankRdBursts::14 73944 # Per bank write bursts +system.physmem.perBankRdBursts::15 72584 # Per bank write bursts +system.physmem.perBankWrBursts::0 62047 # Per bank write bursts +system.physmem.perBankWrBursts::1 68427 # Per bank write bursts +system.physmem.perBankWrBursts::2 68519 # Per bank write bursts +system.physmem.perBankWrBursts::3 66050 # Per bank write bursts +system.physmem.perBankWrBursts::4 65357 # Per bank write bursts +system.physmem.perBankWrBursts::5 67435 # Per bank write bursts +system.physmem.perBankWrBursts::6 63960 # Per bank write bursts +system.physmem.perBankWrBursts::7 63937 # Per bank write bursts +system.physmem.perBankWrBursts::8 63039 # Per bank write bursts +system.physmem.perBankWrBursts::9 70105 # Per bank write bursts +system.physmem.perBankWrBursts::10 66227 # Per bank write bursts +system.physmem.perBankWrBursts::11 68082 # Per bank write bursts +system.physmem.perBankWrBursts::12 64306 # Per bank write bursts +system.physmem.perBankWrBursts::13 66291 # Per bank write bursts +system.physmem.perBankWrBursts::14 64522 # Per bank write bursts +system.physmem.perBankWrBursts::15 63255 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 27 # Number of times write queue was full causing retry -system.physmem.totGap 51291804197000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 51331523357500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1257816 # Read request sizes (log2) +system.physmem.readPktSize::6 1224610 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1078603 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 653601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 337199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 152943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 128864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1051260 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 635913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 326498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 150136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 126962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,162 +159,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 32136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 66802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 73018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 67891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 85825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 496985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.554208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.944807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.108749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 196641 39.57% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 117090 23.56% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 47261 9.51% 72.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24196 4.87% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18882 3.80% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11863 2.39% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10943 2.20% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8246 1.66% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61863 12.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 496985 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.773365 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 265.981989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 61532 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 11720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 33279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 64510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 65005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 65443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 477001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.142583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.284446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.100691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 186993 39.20% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 111432 23.36% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45372 9.51% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23464 4.92% 76.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18197 3.81% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11652 2.44% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10522 2.21% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8218 1.72% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61151 12.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 477001 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59594 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.891952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 270.280066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 59591 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.533241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.977663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.054277 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58637 95.29% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 877 1.43% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 68 0.11% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 330 0.54% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 47 0.08% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 368 0.60% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 228 0.37% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 20 0.03% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 53 0.09% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 138 0.22% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 26 0.04% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 33 0.05% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 471 0.77% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 129 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61535 # Writes before turning the bus around for reads -system.physmem.totQLat 32791506957 # Total ticks spent queuing -system.physmem.totMemAccLat 56759856957 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6391560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25652.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59594 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59594 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.645384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.994879 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.954134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56960 95.58% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 905 1.52% 97.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 37 0.06% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 115 0.19% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 18 0.03% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 110 0.18% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 195 0.33% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.04% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 355 0.60% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 71 0.12% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.04% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 56 0.09% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 280 0.47% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 26 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 33 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 125 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 203 0.34% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59594 # Writes before turning the bus around for reads +system.physmem.totQLat 31834686171 # Total ticks spent queuing +system.physmem.totMemAccLat 55179879921 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6225385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25568.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44402.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44318.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 1048127 # Number of row buffer hits during reads -system.physmem.writeRowHits 812106 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes -system.physmem.avgGap 21731264.68 # Average gap between requests -system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1887739560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1030016625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4918711200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3492687600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3350131371600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1239587078895 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29687726109750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34288773715230 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.503935 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49388003607661 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712746100000 # Time in different power states +system.physmem.avgWrQLen 26.63 # Average write queue length when enqueuing +system.physmem.readRowHits 1023243 # Number of row buffer hits during reads +system.physmem.writeRowHits 796390 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes +system.physmem.avgGap 22320693.30 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1817907840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 991914000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4808848200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3406743360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1236862065645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29713947077250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34314560092455 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.489031 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49431665045810 # Time in different power states +system.physmem_0.memoryStateTime::REF 1714072360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 191055633589 # Time in different power states +system.physmem_0.memoryStateTime::ACT 185786732190 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1869467040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1020046500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5052099000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3498636240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3350131371600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1240740741510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29686714133250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34289026495140 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.508863 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49386297692325 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712746100000 # Time in different power states +system.physmem_1.actEnergy 1788219720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 975715125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4902705600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3407358960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1238749464465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712291456000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34314840456030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494493 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49428877758086 # Time in different power states +system.physmem_1.memoryStateTime::REF 1714072360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192761562675 # Time in different power states +system.physmem_1.memoryStateTime::ACT 188572884414 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -338,15 +344,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 224688792 # Number of BP lookups -system.cpu.branchPred.condPredicted 150206770 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12191755 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158635537 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103690237 # Number of BTB hits +system.cpu.branchPred.lookups 223870317 # Number of BP lookups +system.cpu.branchPred.condPredicted 149571742 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12183866 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157933845 # Number of BTB lookups +system.cpu.branchPred.BTBHits 103250874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.363814 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30864801 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343432 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.376028 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30780710 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 342883 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,45 +383,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 198718 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 198718 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 198718 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 198718 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 198718 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walks 196101 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 196101 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 196101 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 196101 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 196101 # Table walker wait (enqueue to first request) latency system.cpu.checker.dtb.walker.walksPending::samples -1584953796 # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::0 -1584953796 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.dtb.walker.walksPending::total -1584953796 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 154432 91.32% 91.32% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 14687 8.68% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 169119 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 198718 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkPageSizes::4K 153300 91.91% 91.91% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 13495 8.09% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 166795 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 196101 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 198718 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169119 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 196101 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 166795 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169119 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 367837 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 166795 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 362896 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 159761932 # DTB read hits -system.cpu.checker.dtb.read_misses 147725 # DTB read misses -system.cpu.checker.dtb.write_hits 145062914 # DTB write hits -system.cpu.checker.dtb.write_misses 50993 # DTB write misses +system.cpu.checker.dtb.read_hits 159296881 # DTB read hits +system.cpu.checker.dtb.read_misses 146556 # DTB read misses +system.cpu.checker.dtb.write_hits 144479663 # DTB write hits +system.cpu.checker.dtb.write_misses 49545 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72161 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 71585 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 6829 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7067 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19116 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 159909657 # DTB read accesses -system.cpu.checker.dtb.write_accesses 145113907 # DTB write accesses +system.cpu.checker.dtb.perms_faults 18958 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 159443437 # DTB read accesses +system.cpu.checker.dtb.write_accesses 144529208 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 304824846 # DTB hits -system.cpu.checker.dtb.misses 198718 # DTB misses -system.cpu.checker.dtb.accesses 305023564 # DTB accesses +system.cpu.checker.dtb.hits 303776544 # DTB hits +system.cpu.checker.dtb.misses 196101 # DTB misses +system.cpu.checker.dtb.accesses 303972645 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,46 +451,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 119115 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 119115 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 119115 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 119115 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 119115 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walks 119784 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 119784 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 119784 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 119784 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 119784 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walksPending::samples -1586149296 # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::0 -1586149296 100.00% 100.00% # Table walker pending requests distribution system.cpu.checker.itb.walker.walksPending::total -1586149296 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 107231 98.82% 98.82% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.18% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 108511 # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::4K 107945 98.82% 98.82% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.18% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109231 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119115 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119115 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119784 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119784 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 108511 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 108511 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 227626 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 850192533 # ITB inst hits -system.cpu.checker.itb.inst_misses 119115 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109231 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109231 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 229015 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 846929544 # ITB inst hits +system.cpu.checker.itb.inst_misses 119784 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 51914 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 51594 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 850311648 # ITB inst accesses -system.cpu.checker.itb.hits 850192533 # DTB hits -system.cpu.checker.itb.misses 119115 # DTB misses -system.cpu.checker.itb.accesses 850311648 # DTB accesses -system.cpu.checker.numCycles 999125211 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 847049328 # ITB inst accesses +system.cpu.checker.itb.hits 846929544 # DTB hits +system.cpu.checker.itb.misses 119784 # DTB misses +system.cpu.checker.itb.accesses 847049328 # DTB accesses +system.cpu.checker.numCycles 995222047 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -516,85 +522,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 949667 # Table walker walks requested -system.cpu.dtb.walker.walksLong 949667 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16250 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155668 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435817 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 513850 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2276.559307 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14912.808509 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 510335 99.32% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1958 0.38% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1047 0.20% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 218 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 154 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 54 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 937088 # Table walker walks requested +system.cpu.dtb.walker.walksLong 937088 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15029 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154587 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 427394 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 509694 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2223.932399 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14616.246492 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 506310 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1920 0.38% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 988 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 199 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 148 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 46 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 513850 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 485169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23149.084134 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18057.598080 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21275.722761 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 473369 97.57% 97.57% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7953 1.64% 99.21% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2827 0.58% 99.79% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 192 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 567 0.12% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 106 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 98 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 485169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 791579212632 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.715441 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.525649 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 789339278132 99.72% 99.72% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1195712000 0.15% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 474046500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 207567500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 154449500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121794500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 29070000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 54831500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2463000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 791579212632 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155669 90.55% 90.55% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16250 9.45% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171919 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949667 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 509694 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 474748 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23018.407660 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18045.301329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20477.097679 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 463839 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7714 1.62% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2286 0.48% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 175 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 504 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 86 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 94 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 30 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 474748 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 784053971876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.725342 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.519550 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 781854829876 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1175747000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 476309500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 200437500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 146602500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 120332500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 25999000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 51086000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2628000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 784053971876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 154588 91.14% 91.14% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15029 8.86% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 169617 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 937088 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949667 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171919 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 937088 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169617 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171919 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1121586 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169617 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1106705 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169633674 # DTB read hits -system.cpu.dtb.read_misses 671728 # DTB read misses -system.cpu.dtb.write_hits 147819857 # DTB write hits -system.cpu.dtb.write_misses 277939 # DTB write misses +system.cpu.dtb.read_hits 169133397 # DTB read hits +system.cpu.dtb.read_misses 670096 # DTB read misses +system.cpu.dtb.write_hits 147221017 # DTB write hits +system.cpu.dtb.write_misses 266992 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72392 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 97 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9958 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 71818 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 99 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 9972 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 70151 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170305402 # DTB read accesses -system.cpu.dtb.write_accesses 148097796 # DTB write accesses +system.cpu.dtb.perms_faults 69741 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 169803493 # DTB read accesses +system.cpu.dtb.write_accesses 147488009 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 317453531 # DTB hits -system.cpu.dtb.misses 949667 # DTB misses -system.cpu.dtb.accesses 318403198 # DTB accesses +system.cpu.dtb.hits 316354414 # DTB hits +system.cpu.dtb.misses 937088 # DTB misses +system.cpu.dtb.accesses 317291502 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -624,885 +630,884 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 160444 # Table walker walks requested -system.cpu.itb.walker.walksLong 160444 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1424 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120836 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17536 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 142908 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1360.753072 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 10149.850878 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 141808 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 585 0.41% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 64 0.04% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 103 0.07% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 274 0.19% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 31 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 17 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 160983 # Table walker walks requested +system.cpu.itb.walker.walksLong 160983 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1438 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121478 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17520 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 143463 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1273.722144 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9463.659088 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142472 99.31% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 574 0.40% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 44 0.03% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 82 0.06% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 231 0.16% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 142908 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139796 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29385.243498 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24234.240486 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24521.703817 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136348 97.53% 97.53% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 877 0.63% 98.16% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2201 1.57% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 135 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 29 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 40 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139796 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 671317017344 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.945059 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.228245 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 36939918060 5.50% 5.50% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 634320646784 94.49% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 55500500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 942000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 671317017344 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120836 98.84% 98.84% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1424 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 122260 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 143463 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140436 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29061.341109 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24320.215707 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22395.663440 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137485 97.90% 97.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 845 0.60% 98.50% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1830 1.30% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 92 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 113 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140436 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 672381692680 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944059 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.230149 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37665306856 5.60% 5.60% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634665708824 94.39% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 49644500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 1013500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 19000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 672381692680 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121478 98.83% 98.83% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1438 1.17% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 122916 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160444 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 160444 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160983 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 160983 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122260 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 122260 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 282704 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357283873 # ITB inst hits -system.cpu.itb.inst_misses 160444 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 283899 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 355891670 # ITB inst hits +system.cpu.itb.inst_misses 160983 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 79146 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2042 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53225 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 78302 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 52900 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 370647 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 368990 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357444317 # ITB inst accesses -system.cpu.itb.hits 357283873 # DTB hits -system.cpu.itb.misses 160444 # DTB misses -system.cpu.itb.accesses 357444317 # DTB accesses -system.cpu.numCycles 1651928956 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 356052653 # ITB inst accesses +system.cpu.itb.hits 355891670 # DTB hits +system.cpu.itb.misses 160983 # DTB misses +system.cpu.itb.accesses 356052653 # DTB accesses +system.cpu.numCycles 1641618102 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 644904840 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002675339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 224688792 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 134555038 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 920067624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26040080 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3808104 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9331769 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1037128 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356896495 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6093203 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48590 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1592200226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.737909 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.145097 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 643295277 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 998912988 # Number of instructions fetch has processed +system.cpu.fetch.Branches 223870317 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 134031584 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 911548920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26021190 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3814569 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28072 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9294541 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1045994 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 928 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 355505947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6091455 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48555 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1582038896 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.739816 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1034156168 64.95% 64.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214254104 13.46% 78.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70725246 4.44% 82.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273064708 17.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1026150412 64.86% 64.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213368743 13.49% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70509493 4.46% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 272010248 17.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1592200226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136016 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606972 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 524217376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 575207225 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 433339906 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50215792 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9219927 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33654884 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3860028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1086626232 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28988785 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9219927 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 568973528 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70181306 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 374019312 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438766207 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 131039946 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1066849636 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6780403 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5130065 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 345924 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 553258 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 79683463 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20375 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1014727198 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1644037540 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1261867774 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1469696 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 949117253 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65609942 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27037743 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23369810 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103057716 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173655780 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 151390357 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9897841 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9017927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1031708315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27333559 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1047312719 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3286243 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60487130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33695071 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1592200226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.657777 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.917314 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1582038896 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.608493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 523526038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 567332242 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 432225078 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49743606 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9211932 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33585206 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3858658 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1082487330 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28953315 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9211932 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 568013928 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68659821 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 370106883 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 437449183 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 128597149 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1062778939 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6765759 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5100330 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 330196 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 669001 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 77613497 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20248 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1010589647 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1636490834 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1256895335 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1474103 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 945145868 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65443776 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26770566 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23114475 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 102068123 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173157157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150776419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9868164 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9014634 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1027918827 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27065451 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1043272281 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3272960 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60330213 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33600804 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 313388 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1582038896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.659448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917899 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 943790813 59.28% 59.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334741898 21.02% 80.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234957148 14.76% 95.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72204170 4.53% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6486970 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19227 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 936232713 59.18% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 333194737 21.06% 80.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234236353 14.81% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 71914703 4.55% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6441221 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1592200226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1582038896 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57844214 35.03% 35.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99575 0.06% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26721 0.02% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 685 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44353632 26.86% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62797684 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57633129 35.05% 35.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100179 0.06% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26746 0.02% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 783 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44218992 26.89% 62.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62461837 37.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 721297441 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2539668 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122649 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121234 0.01% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173513888 16.57% 85.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149717789 14.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 718385578 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2533352 0.24% 69.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122770 0.01% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 382 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121248 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173007895 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149100989 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1047312719 # Type of FU issued -system.cpu.iq.rate 0.633994 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165122511 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157663 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3852756863 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118723028 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1029355100 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2477554 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 946947 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909717 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1210878214 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1557015 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4319350 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1043272281 # Type of FU issued +system.cpu.iq.rate 0.635515 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164441666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157621 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3833820592 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1114508942 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1025374913 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2477491 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 947894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909947 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1206157308 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1556618 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4301219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13798077 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14626 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142237 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6323389 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13765356 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14482 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6293913 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2533948 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1563961 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2526650 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1543650 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9219927 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7084785 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9314562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1059264038 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9211932 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6884950 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9078435 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1055205514 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173655780 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 151390357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22943670 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 58438 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9182367 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142237 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3657929 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5098518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8756447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1036137894 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169621625 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10236296 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173157157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150776419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22691259 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 56491 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8949926 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3653003 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5096400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8749403 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1032130630 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169121119 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10215406 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222164 # number of nop insts executed -system.cpu.iew.exec_refs 317437095 # number of memory reference insts executed -system.cpu.iew.exec_branches 196547238 # Number of branches executed -system.cpu.iew.exec_stores 147815470 # Number of stores executed -system.cpu.iew.exec_rate 0.627229 # Inst execution rate -system.cpu.iew.wb_sent 1031075002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1030264817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 438532269 # num instructions producing a value -system.cpu.iew.wb_consumers 709380763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.623674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618190 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51390718 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27018492 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8391642 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1580228062 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.631905 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.268654 # Number of insts commited each cycle +system.cpu.iew.exec_nop 221236 # number of nop insts executed +system.cpu.iew.exec_refs 316337352 # number of memory reference insts executed +system.cpu.iew.exec_branches 195829859 # Number of branches executed +system.cpu.iew.exec_stores 147216233 # Number of stores executed +system.cpu.iew.exec_rate 0.628728 # Inst execution rate +system.cpu.iew.wb_sent 1027090277 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1026284860 # cumulative count of insts written-back +system.cpu.iew.wb_producers 436833707 # num instructions producing a value +system.cpu.iew.wb_consumers 706462159 # num instructions consuming a value +system.cpu.iew.wb_rate 0.625167 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618340 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51246502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26752063 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8385203 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1570087734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.633502 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1067496193 67.55% 67.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288499411 18.26% 85.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120593665 7.63% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36542296 2.31% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28489830 1.80% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14035785 0.89% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8641720 0.55% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4180750 0.26% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11748412 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1059518127 67.48% 67.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 287046411 18.28% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120236472 7.66% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36451838 2.32% 95.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28385212 1.81% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13987217 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8615612 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4166173 0.27% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11680672 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1580228062 # Number of insts commited each cycle -system.cpu.commit.committedInsts 849784302 # Number of instructions committed -system.cpu.commit.committedOps 998554740 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1570087734 # Number of insts commited each cycle +system.cpu.commit.committedInsts 846524467 # Number of instructions committed +system.cpu.commit.committedOps 994654061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304924670 # Number of memory references committed -system.cpu.commit.loads 159857702 # Number of loads committed -system.cpu.commit.membars 6942890 # Number of memory barriers committed -system.cpu.commit.branches 189641559 # Number of branches committed -system.cpu.commit.fp_insts 896155 # Number of committed floating point instructions. -system.cpu.commit.int_insts 917432780 # Number of committed integer instructions. -system.cpu.commit.function_calls 25317062 # Number of function calls committed. +system.cpu.commit.refs 303874306 # Number of memory references committed +system.cpu.commit.loads 159391800 # Number of loads committed +system.cpu.commit.membars 6909679 # Number of memory barriers committed +system.cpu.commit.branches 188935778 # Number of branches committed +system.cpu.commit.fp_insts 896706 # Number of committed floating point instructions. +system.cpu.commit.int_insts 913907111 # Number of committed integer instructions. +system.cpu.commit.function_calls 25250179 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 691266097 69.23% 69.23% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2154064 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98002 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111865 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159857702 16.01% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145066968 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 688421836 69.21% 69.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2147861 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98019 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159391800 16.02% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144482506 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 998554740 # Class of committed instruction -system.cpu.commit.bw_lim_events 11748412 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2610868733 # The number of ROB reads -system.cpu.rob.rob_writes 2111769063 # The number of ROB writes -system.cpu.timesIdled 8146861 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59728730 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100931682357 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 849784302 # Number of Instructions Simulated -system.cpu.committedOps 998554740 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.943939 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.943939 # CPI: Total CPI of All Threads -system.cpu.ipc 0.514419 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.514419 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1226658290 # number of integer regfile reads -system.cpu.int_regfile_writes 732482520 # number of integer regfile writes -system.cpu.fp_regfile_reads 1461367 # number of floating regfile reads -system.cpu.fp_regfile_writes 784012 # number of floating regfile writes -system.cpu.cc_regfile_reads 225710355 # number of cc regfile reads -system.cpu.cc_regfile_writes 226370154 # number of cc regfile writes -system.cpu.misc_regfile_reads 2581410543 # number of misc regfile reads -system.cpu.misc_regfile_writes 27063260 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9708370 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972782 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283529628 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9708882 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.203118 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 994654061 # Class of committed instruction +system.cpu.commit.bw_lim_events 11680672 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2596784081 # The number of ROB reads +system.cpu.rob.rob_writes 2103659595 # The number of ROB writes +system.cpu.timesIdled 8144337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59579206 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101021431570 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 846524467 # Number of Instructions Simulated +system.cpu.committedOps 994654061 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.939245 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.939245 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515665 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515665 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1221742987 # number of integer regfile reads +system.cpu.int_regfile_writes 729786547 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462559 # number of floating regfile reads +system.cpu.fp_regfile_writes 782552 # number of floating regfile writes +system.cpu.cc_regfile_reads 224594796 # number of cc regfile reads +system.cpu.cc_regfile_writes 225242859 # number of cc regfile writes +system.cpu.misc_regfile_reads 2567204891 # number of misc regfile reads +system.cpu.misc_regfile_writes 26785378 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9653571 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972798 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 282643774 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9654083 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.277123 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972782 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972798 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1238524544 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1238524544 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 147275132 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147275132 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128498890 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128498890 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 378449 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 378449 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323156 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323156 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3306743 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3306743 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3702780 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 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ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78478155174 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 78478155174 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 23792891000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 23792891000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 88415534042 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 88415534042 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3234901000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3234901000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163635250674 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163635250674 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187428141674 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187428141674 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191802000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191802000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228377464 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228377464 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84024978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84024978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76144562086 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76144562086 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22952152500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22952152500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 87564866876 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87564866876 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3184481000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3184481000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 267500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 267500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160169540086 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160169540086 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183121692586 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 183121692586 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191871000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191871000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228308464 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228308464 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420179464 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420179464 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014379 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014379 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752369 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752369 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787912 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787912 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061032 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.750363 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.750363 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787071 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787071 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060925 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024022 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024022 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027822 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027822 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16646.358856 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16646.358856 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39040.769996 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39040.769996 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20326.874348 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20326.874348 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72046.497715 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72046.497715 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14114.186610 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14114.186610 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54100 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54100 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22963.714576 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22963.714576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22591.687709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22591.687709 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183853.019776 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183853.019776 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184840.261871 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184840.261871 # average WriteReq mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023982 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023982 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027745 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027745 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16496.552951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16496.552951 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38132.587730 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38132.587730 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19868.054299 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19868.054299 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71514.975475 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71514.975475 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14011.822890 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14011.822890 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 53500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 53500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22589.876018 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22589.876018 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22208.539874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22208.539874 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183855.068591 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183855.068591 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184838.214150 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184838.214150 # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15025014 # number of replacements -system.cpu.icache.tags.tagsinuse 511.916800 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 341084146 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15025526 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.700313 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15015869 # number of replacements +system.cpu.icache.tags.tagsinuse 511.916858 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 339700335 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15016381 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.621984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 24730722500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.916800 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 511.916858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999838 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371900940 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371900940 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 341084146 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 341084146 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 341084146 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 341084146 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 341084146 # number of overall hits -system.cpu.icache.overall_hits::total 341084146 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15791051 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15791051 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15791051 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15791051 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15791051 # number of overall misses -system.cpu.icache.overall_misses::total 15791051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 213656099879 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 213656099879 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 213656099879 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 213656099879 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 213656099879 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 213656099879 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356875197 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356875197 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356875197 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356875197 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356875197 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356875197 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044248 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044248 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044248 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044248 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044248 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044248 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13530.201370 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13530.201370 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13530.201370 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13530.201370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13530.201370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13530.201370 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 23378 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 370501257 # Number of tag accesses +system.cpu.icache.tags.data_accesses 370501257 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 339700335 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 339700335 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 339700335 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 339700335 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 339700335 # number of overall hits +system.cpu.icache.overall_hits::total 339700335 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15784316 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15784316 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15784316 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15784316 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15784316 # number of overall misses +system.cpu.icache.overall_misses::total 15784316 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 213513378383 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 213513378383 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 213513378383 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 213513378383 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 213513378383 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 213513378383 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 355484651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 355484651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 355484651 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 355484651 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 355484651 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 355484651 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044402 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044402 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044402 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044402 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044402 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044402 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13526.932582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13526.932582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13526.932582 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13526.932582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13526.932582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13526.932582 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 23493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1447 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1429 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was 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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126977.999453 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 127566.322256 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124754.623884 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129077.692998 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128578.841860 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.197685 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.197685 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005574 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038376 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038376 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.403563 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.403563 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029564 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029564 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127863.347785 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.600757 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.600757 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128655.026050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128655.026050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124605.160034 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124605.160034 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128886.233897 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128886.233897 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145023.125375 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145023.125375 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171347.229645 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148973.932184 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.033357 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.033357 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171350.302868 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148975.814960 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173203.881766 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173203.881766 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172276.879805 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158182.720937 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.339923 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.070555 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50209605 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25474994 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2120 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2120 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 50072876 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25402191 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3486 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2165 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2165 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1623677 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23162262 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1616472 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23106705 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8599615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15022476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2383518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8523542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15015869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2370764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43153 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1969613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1969613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15025743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1227201 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45116347 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29348618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 723959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1930896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77119820 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923413728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1024410462 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2386824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6302376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2956513390 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1874549 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27826881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025283 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156985 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1956829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1956829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15016606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6481683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1331091 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1224427 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45091458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29183621 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917139 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 76921811 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922405600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017963166 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2418728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6263128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2949050622 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1833494 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27720270 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27123321 97.47% 97.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 703560 2.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27024822 97.49% 97.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 695448 2.51% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27826881 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48147469995 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27720270 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48021701496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1446401 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1471889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22568730706 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22555136481 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13411529968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13331758520 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 425937320 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 427610263 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1143472216 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1134604242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution +system.iobus.trans_dist::ReadReq 40281 # Transaction distribution +system.iobus.trans_dist::ReadResp 40281 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1722,11 +1727,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230920 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230920 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353704 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1741,12 +1746,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334112 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41872500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41869500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1768,73 +1773,73 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25139500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25153000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36496500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565848565 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567170357 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147680000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.417914 # Cycle average of tags in use +system.iocache.tags.replacements 115446 # number of replacements +system.iocache.tags.tagsinuse 10.422236 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13103145499000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.546638 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.871276 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103145496000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.903254 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.518982 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.368953 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.282436 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039605 # Number of tag accesses -system.iocache.tags.data_accesses 1039605 # Number of data accesses +system.iocache.tags.tag_accesses 1039497 # Number of tag accesses +system.iocache.tags.data_accesses 1039497 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8796 # number of 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8833 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8808 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8796 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8836 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8808 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8796 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8836 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1848,55 +1853,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191963.951067 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191734.197965 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 190819.355048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190593.971131 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129996.977274 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129996.977274 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191963.951067 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191708.858612 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191963.951067 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191708.858612 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36185 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125723.888191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125723.888191 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190568.984495 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190568.984495 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34452 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3641 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.938204 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.991879 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8796 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8833 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8808 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8848 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8796 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8836 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8808 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8848 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1250418481 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1253638981 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8796 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8836 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1238647047 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1241866547 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8532797584 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8532797584 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1250418481 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1253839981 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1250418481 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1253839981 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071956842 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8071956842 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1238647047 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1242067547 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1238647047 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1242067547 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1910,73 +1915,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141963.951067 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141734.197965 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140819.355048 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140593.971131 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79996.977274 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79996.977274 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141963.951067 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141708.858612 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141963.951067 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141708.858612 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75676.487306 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75676.487306 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 414632 # Transaction distribution +system.membus.trans_dist::ReadResp 402203 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1078603 # Transaction distribution -system.membus.trans_dist::CleanEvict 193680 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35229 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1051260 # Transaction distribution +system.membus.trans_dist::CleanEvict 188377 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34626 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35232 # Transaction distribution -system.membus.trans_dist::ReadExReq 900805 # Transaction distribution -system.membus.trans_dist::ReadExResp 900805 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 359660 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 880179 # Transaction distribution +system.membus.trans_dist::ReadExResp 880179 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 347231 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3779727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3909347 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342337 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342337 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4251684 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3643028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3772648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4010286 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 142628812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 142798782 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7263040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 150061822 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2657 # Total snoops (count) -system.membus.snoop_fanout::samples 2765486 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138764108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138934078 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7252608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 146186686 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2808 # Total snoops (count) +system.membus.snoop_fanout::samples 2697046 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2765486 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2697046 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2765486 # Request fanout histogram -system.membus.reqLayer0.occupancy 103948000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2697046 # Request fanout histogram +system.membus.reqLayer0.occupancy 103954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5458000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5466500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7323908114 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7139670905 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6816104590 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6571001988 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227615986 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44720417 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2031,6 +2035,6 @@ system.realview.mcc.osc_mcc.clock 20000 # Cl system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16126 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16102 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 5e9f9ee14..6b53e6579 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,172 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.393981 # Number of seconds simulated -sim_ticks 47393980707000 # Number of ticks simulated -final_tick 47393980707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.354243 # Number of seconds simulated +sim_ticks 47354242877000 # Number of ticks simulated +final_tick 47354242877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 118826 # Simulator instruction rate (inst/s) -host_op_rate 139727 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6107626980 # Simulator tick rate (ticks/s) -host_mem_usage 769604 # Number of bytes of host memory used -host_seconds 7759.80 # Real time elapsed on the host -sim_insts 922064003 # Number of instructions simulated -sim_ops 1084251192 # Number of ops (including micro ops) simulated +host_inst_rate 195342 # Simulator instruction rate (inst/s) +host_op_rate 229691 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10034841905 # Simulator tick rate (ticks/s) +host_mem_usage 778832 # Number of bytes of host memory used +host_seconds 4718.98 # Real time elapsed on the host +sim_insts 921815819 # Number of instructions simulated +sim_ops 1083910027 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 150400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 142336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4326432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 44486728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 20365824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 171008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 152256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3129632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 15575440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14887232 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428800 # Number of bytes read from this memory -system.physmem.bytes_read::total 103816088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4326432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3129632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7456064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86117376 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 202368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 196224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4450144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 45350984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 22283904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 113792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 85504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2862048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13865872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 12452160 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439808 # Number of bytes read from this memory +system.physmem.bytes_read::total 102302808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4450144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2862048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7312192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 85371072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86137960 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 83553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 695118 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 318216 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 48944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 243379 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 232613 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6700 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1638148 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1345584 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 85391656 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 85486 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 708622 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 348186 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1778 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1336 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44763 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 216667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 194565 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6872 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1614503 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1333923 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1348158 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 91287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 938658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 429713 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3608 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 66034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 328638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 314117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2190491 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 91287 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 66034 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 157321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1817053 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1336497 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 4144 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 93976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 957696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 470579 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 292812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 262958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2160373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 93976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60439 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 154415 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1802818 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1817487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1817053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 91287 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 939092 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 429713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 66034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 328638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 314117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4007978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1638148 # Number of read requests accepted -system.physmem.writeReqs 1348158 # Number of write requests accepted -system.physmem.readBursts 1638148 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1348158 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 104808896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 32576 # Total number of bytes read from write queue -system.physmem.bytesWritten 86137280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 103816088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 86137960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 509 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1803252 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1802818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 4144 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 93976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 958131 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 470579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 292812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 262958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3963625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1614503 # Number of read requests accepted +system.physmem.writeReqs 1336497 # Number of write requests accepted +system.physmem.readBursts 1614503 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1336497 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 103293760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 34432 # Total number of bytes read from write queue +system.physmem.bytesWritten 85390720 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 102302808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 85391656 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 538 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 529318 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 98506 # Per bank write bursts -system.physmem.perBankRdBursts::1 102125 # Per bank write bursts -system.physmem.perBankRdBursts::2 96514 # Per bank write bursts -system.physmem.perBankRdBursts::3 101212 # Per bank write bursts -system.physmem.perBankRdBursts::4 98283 # Per bank write bursts -system.physmem.perBankRdBursts::5 109978 # Per bank write bursts -system.physmem.perBankRdBursts::6 106703 # Per bank write bursts -system.physmem.perBankRdBursts::7 105175 # Per bank write bursts -system.physmem.perBankRdBursts::8 93813 # Per bank write bursts -system.physmem.perBankRdBursts::9 120186 # Per bank write bursts -system.physmem.perBankRdBursts::10 99379 # Per bank write bursts -system.physmem.perBankRdBursts::11 109206 # Per bank write bursts -system.physmem.perBankRdBursts::12 97639 # Per bank write bursts -system.physmem.perBankRdBursts::13 103304 # Per bank write bursts -system.physmem.perBankRdBursts::14 94884 # Per bank write bursts -system.physmem.perBankRdBursts::15 100732 # Per bank write bursts -system.physmem.perBankWrBursts::0 82092 # Per bank write bursts -system.physmem.perBankWrBursts::1 86582 # Per bank write bursts -system.physmem.perBankWrBursts::2 80748 # Per bank write bursts -system.physmem.perBankWrBursts::3 83407 # Per bank write bursts -system.physmem.perBankWrBursts::4 81928 # Per bank write bursts -system.physmem.perBankWrBursts::5 88947 # Per bank write bursts -system.physmem.perBankWrBursts::6 86848 # Per bank write bursts -system.physmem.perBankWrBursts::7 87370 # Per bank write bursts -system.physmem.perBankWrBursts::8 79257 # Per bank write bursts -system.physmem.perBankWrBursts::9 83439 # Per bank write bursts -system.physmem.perBankWrBursts::10 82066 # Per bank write bursts -system.physmem.perBankWrBursts::11 89206 # Per bank write bursts -system.physmem.perBankWrBursts::12 82040 # Per bank write bursts -system.physmem.perBankWrBursts::13 87648 # Per bank write bursts -system.physmem.perBankWrBursts::14 80198 # Per bank write bursts -system.physmem.perBankWrBursts::15 84119 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 97103 # Per bank write bursts +system.physmem.perBankRdBursts::1 99552 # Per bank write bursts +system.physmem.perBankRdBursts::2 98906 # Per bank write bursts +system.physmem.perBankRdBursts::3 103577 # Per bank write bursts +system.physmem.perBankRdBursts::4 99773 # Per bank write bursts +system.physmem.perBankRdBursts::5 105983 # Per bank write bursts +system.physmem.perBankRdBursts::6 104785 # Per bank write bursts +system.physmem.perBankRdBursts::7 101396 # Per bank write bursts +system.physmem.perBankRdBursts::8 95400 # Per bank write bursts +system.physmem.perBankRdBursts::9 122614 # Per bank write bursts +system.physmem.perBankRdBursts::10 95999 # Per bank write bursts +system.physmem.perBankRdBursts::11 101585 # Per bank write bursts +system.physmem.perBankRdBursts::12 99838 # Per bank write bursts +system.physmem.perBankRdBursts::13 98462 # Per bank write bursts +system.physmem.perBankRdBursts::14 93633 # Per bank write bursts +system.physmem.perBankRdBursts::15 95359 # Per bank write bursts +system.physmem.perBankWrBursts::0 80772 # Per bank write bursts +system.physmem.perBankWrBursts::1 85062 # Per bank write bursts +system.physmem.perBankWrBursts::2 82679 # Per bank write bursts +system.physmem.perBankWrBursts::3 85393 # Per bank write bursts +system.physmem.perBankWrBursts::4 84018 # Per bank write bursts +system.physmem.perBankWrBursts::5 87943 # Per bank write bursts +system.physmem.perBankWrBursts::6 87092 # Per bank write bursts +system.physmem.perBankWrBursts::7 86427 # Per bank write bursts +system.physmem.perBankWrBursts::8 80096 # Per bank write bursts +system.physmem.perBankWrBursts::9 84617 # Per bank write bursts +system.physmem.perBankWrBursts::10 79653 # Per bank write bursts +system.physmem.perBankWrBursts::11 85236 # Per bank write bursts +system.physmem.perBankWrBursts::12 82895 # Per bank write bursts +system.physmem.perBankWrBursts::13 82853 # Per bank write bursts +system.physmem.perBankWrBursts::14 78695 # Per bank write bursts +system.physmem.perBankWrBursts::15 80799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 13 # Number of times write queue was full causing retry -system.physmem.totGap 47393979099500 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 47354241269500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1616790 # Read request sizes (log2) +system.physmem.readPktSize::6 1593145 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1345584 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 619728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 417888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 167778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 159876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 99605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 61553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 27167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7798 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1279 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1333923 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 609512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 408742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 165543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 158385 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 99064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 61330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30716 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 4295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see @@ -188,163 +188,166 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 36742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 44665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 54132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 78252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 84742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 88110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 91290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 97437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 95426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 99220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 98211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 87853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 81636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1054994 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 180.992301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.466356 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 240.522304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 655278 62.11% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 195680 18.55% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 62552 5.93% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34743 3.29% 89.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24726 2.34% 92.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13789 1.31% 93.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13873 1.31% 94.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7523 0.71% 95.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 46830 4.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1054994 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 76193 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.493169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249.861284 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 76190 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 21385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 25204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 37704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 53566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 76299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 82207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 85573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 89148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 94653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 94373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 98828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 112387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 98640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 87955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 82141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1039142 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 181.576816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.689088 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.244363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 644376 62.01% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 193180 18.59% 80.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 61698 5.94% 86.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 33929 3.27% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24382 2.35% 92.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13748 1.32% 93.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13846 1.33% 94.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7628 0.73% 95.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46355 4.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1039142 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 75311 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.430349 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 250.668355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 75308 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 76193 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 76193 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.664287 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.191501 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.434084 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 70631 92.70% 92.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 3142 4.12% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 485 0.64% 97.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 323 0.42% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 79 0.10% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 306 0.40% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 178 0.23% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 116 0.15% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 95 0.12% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 99 0.13% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 41 0.05% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.07% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 407 0.53% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 35 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 33 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 86 0.11% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 20 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 76193 # Writes before turning the bus around for reads -system.physmem.totQLat 70239099561 # Total ticks spent queuing -system.physmem.totMemAccLat 100944830811 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 8188195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 42890.47 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 75311 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 75311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.716270 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.189166 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.091364 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 70052 93.02% 93.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 3029 4.02% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 423 0.56% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 178 0.24% 97.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 138 0.18% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 118 0.16% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 205 0.27% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 81 0.11% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 292 0.39% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 59 0.08% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 23 0.03% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 57 0.08% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 240 0.32% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 44 0.06% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 108 0.14% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 169 0.22% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 75311 # Writes before turning the bus around for reads +system.physmem.totQLat 70116127057 # Total ticks spent queuing +system.physmem.totMemAccLat 100377970807 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8069825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43443.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 61640.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62193.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing -system.physmem.readRowHits 1316973 # Number of row buffer hits during reads -system.physmem.writeRowHits 611565 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.42 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 45.44 # Row buffer hit rate for writes -system.physmem.avgGap 15870436.28 # Average gap between requests -system.physmem.pageHitRate 64.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4035157560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2201722875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6384222000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4392934560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1182732038730 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27398902223250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31694192500335 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.738819 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45580299815708 # Time in different power states -system.physmem_0.memoryStateTime::REF 1582589060000 # Time in different power states +system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.55 # Average write queue length when enqueuing +system.physmem.readRowHits 1298803 # Number of row buffer hits during reads +system.physmem.writeRowHits 610248 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.74 # Row buffer hit rate for writes +system.physmem.avgGap 16046845.57 # Average gap between requests +system.physmem.pageHitRate 64.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4027930200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2197779375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6326346000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4402421280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1180978829595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27376595514000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31667477331570 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.735888 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45543196260914 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581262020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 231091139792 # Time in different power states +system.physmem_0.memoryStateTime::ACT 229783905086 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3940597080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2150127375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 6389315400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4328465040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1183329754695 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27398377902750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31694060363700 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.736031 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45579400276584 # Time in different power states -system.physmem_1.memoryStateTime::REF 1582589060000 # Time in different power states +system.physmem_1.actEnergy 3827983320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2088681375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 6262534200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4243389120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177720349355 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27379453830000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31666545278490 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.716205 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45547950580913 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581262020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 231988109666 # Time in different power states +system.physmem_1.memoryStateTime::ACT 225030017087 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -378,15 +381,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 135522453 # Number of BP lookups -system.cpu0.branchPred.condPredicted 89756354 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6696164 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 95487916 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 63232655 # Number of BTB hits +system.cpu0.branchPred.lookups 149665852 # Number of BP lookups +system.cpu0.branchPred.condPredicted 99294558 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 7394871 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 104737280 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 69525721 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.220583 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 18624977 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 201233 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 66.381064 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 20507496 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 218312 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -417,85 +420,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 590400 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 590400 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12973 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94460 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 278631 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 311769 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2427.181663 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14785.327659 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 309280 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1331 0.43% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 885 0.28% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 311769 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 310891 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 20766.069137 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 17798.694444 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 20375.668326 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 307651 98.96% 98.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 747 0.24% 99.20% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1834 0.59% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 107 0.03% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 307 0.10% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 102 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 75 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 634428 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 634428 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14162 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 100318 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 297022 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 337406 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2383.727616 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14932.270093 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 334700 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1380 0.41% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 1061 0.31% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 46 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 68 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 337406 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 331422 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21257.229454 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17843.462773 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 23121.353715 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 326855 98.62% 98.62% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1016 0.31% 98.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2453 0.74% 99.67% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 165 0.05% 99.72% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.19% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 136 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 310891 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 523001837252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.567345 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.551290 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 521647732752 99.74% 99.74% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 761373500 0.15% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 275460500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 125915000 0.02% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 99351000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 52861000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 16652500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 21714500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 741500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 523001837252 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94460 87.92% 87.92% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 12973 12.08% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107433 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 590400 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 24 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 331422 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 582048251060 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.606269 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.543146 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 580572178560 99.75% 99.75% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 833055500 0.14% 99.89% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 305294500 0.05% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 135391000 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 101845000 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 57765000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 18306500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 23753000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 653000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 582048251060 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 100318 87.63% 87.63% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 14162 12.37% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 114480 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 634428 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 590400 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107433 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 634428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114480 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107433 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 697833 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114480 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 748908 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 98363253 # DTB read hits -system.cpu0.dtb.read_misses 426453 # DTB read misses -system.cpu0.dtb.write_hits 80524387 # DTB write hits -system.cpu0.dtb.write_misses 163947 # DTB write misses +system.cpu0.dtb.read_hits 109416332 # DTB read hits +system.cpu0.dtb.read_misses 460008 # DTB read misses +system.cpu0.dtb.write_hits 89314742 # DTB write hits +system.cpu0.dtb.write_misses 174420 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40807 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 204 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 7493 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 43796 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 708 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 7923 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 42725 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 98789706 # DTB read accesses -system.cpu0.dtb.write_accesses 80688334 # DTB write accesses +system.cpu0.dtb.perms_faults 42753 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 109876340 # DTB read accesses +system.cpu0.dtb.write_accesses 89489162 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178887640 # DTB hits -system.cpu0.dtb.misses 590400 # DTB misses -system.cpu0.dtb.accesses 179478040 # DTB accesses +system.cpu0.dtb.hits 198731074 # DTB hits +system.cpu0.dtb.misses 634428 # DTB misses +system.cpu0.dtb.accesses 199365502 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -525,1170 +529,1175 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 85262 # Table walker walks requested -system.cpu0.itb.walker.walksLong 85262 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1098 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61891 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9791 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75471 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1466.000186 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11351.229924 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 75137 99.56% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 79 0.10% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 235 0.31% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 91298 # Table walker walks requested +system.cpu0.itb.walker.walksLong 91298 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1125 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 66671 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 10542 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 80756 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1599.144336 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 12482.430449 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-65535 80336 99.48% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-131071 92 0.11% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-196607 294 0.36% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75471 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72780 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26660.353119 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 23025.074927 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 26139.582838 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71045 97.62% 97.62% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 123 0.17% 97.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1365 1.88% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.13% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 88 0.12% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 30 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 80756 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 78338 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27568.581021 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23319.178868 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 29698.501423 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 76052 97.08% 97.08% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 130 0.17% 97.25% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1833 2.34% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 110 0.14% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 41 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 39 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72780 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 389854695076 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.839132 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.367626 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 62743884640 16.09% 16.09% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 327084697936 83.90% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 23698000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 2390500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 389854695076 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61891 98.26% 98.26% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 1098 1.74% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 62989 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::917504-983039 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 78338 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 423131286608 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.845297 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.361834 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 65489609660 15.48% 15.48% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 357613926448 84.52% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 25558000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 2033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 159500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 423131286608 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 66671 98.34% 98.34% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 1125 1.66% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 67796 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85262 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85262 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 91298 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 91298 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62989 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62989 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 148251 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 213975614 # ITB inst hits -system.cpu0.itb.inst_misses 85262 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 67796 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 67796 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 159094 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 236080263 # ITB inst hits +system.cpu0.itb.inst_misses 91298 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29309 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 31862 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 214464 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 229508 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 214060876 # ITB inst accesses -system.cpu0.itb.hits 213975614 # DTB hits -system.cpu0.itb.misses 85262 # DTB misses -system.cpu0.itb.accesses 214060876 # DTB accesses -system.cpu0.numCycles 807659312 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 236171561 # ITB inst accesses +system.cpu0.itb.hits 236080263 # DTB hits +system.cpu0.itb.misses 91298 # DTB misses +system.cpu0.itb.accesses 236171561 # DTB accesses +system.cpu0.numCycles 875332831 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 88233839 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 599476727 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 135522453 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81857632 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 670713114 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 14447630 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2036483 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 334818 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6261942 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 813783 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 863786 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 213760838 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1698349 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 28412 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 776481580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.903685 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.199979 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 98502478 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 662547160 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 149665852 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 90033217 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 725278481 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 15926346 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2210942 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 343253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 6644206 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 843353 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 921483 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 235849038 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1874950 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 30072 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 842707369 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.920891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.205357 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 440207018 56.69% 56.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 130689201 16.83% 73.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 45750499 5.89% 79.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 159834862 20.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 471086256 55.90% 55.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 144263495 17.12% 73.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 50294842 5.97% 78.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 177062776 21.01% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 776481580 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.167797 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.742240 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 105533428 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 405339788 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 223093644 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 37388098 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5126622 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19615970 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2136984 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 619581339 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 23102207 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5126622 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 140592491 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 65041706 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 253704898 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 224831888 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 87183975 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 602582059 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 5894427 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 10859505 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 384608 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 879717 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 52095352 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 10977 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 576174683 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 933371731 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 711261087 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 684793 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 519247735 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 56926942 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15518812 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13493208 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 75428854 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 98376014 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83834868 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 8883598 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 7640207 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 580665271 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15522553 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 585221400 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2674583 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 53398017 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 34936380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 261009 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 776481580 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.753684 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.045500 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 842707369 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.170982 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.756909 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 117017992 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 431286061 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 248304840 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 40439583 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5658893 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 21552813 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2348874 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 685973615 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 25548756 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5658893 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 155339909 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 68898576 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 270709645 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 249775497 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 92324849 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 667175567 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6553348 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 11928405 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 414386 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 932685 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 54388046 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11955 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 637281036 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1029527825 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 787757309 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 900744 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 574091859 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 63189171 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 16646916 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 14438257 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 81666616 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 109512073 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 93001551 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 9792967 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 8489048 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 643441375 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 16650008 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 647817648 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2959555 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 59258512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 38730764 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 299230 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 842707369 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.768734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.052616 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 456332573 58.77% 58.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 134692381 17.35% 76.12% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 113447710 14.61% 90.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 64406978 8.29% 99.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7597025 0.98% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 4913 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 489695832 58.11% 58.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 146908165 17.43% 75.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 125837037 14.93% 90.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 71836004 8.52% 99.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 8424258 1.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 6073 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 776481580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 842707369 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 60244006 45.44% 45.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 62130 0.05% 45.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 15273 0.01% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 15 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 34917494 26.34% 71.84% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 37330795 28.16% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 67261039 45.56% 45.56% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 66196 0.04% 45.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 15732 0.01% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 38768633 26.26% 71.88% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 41521295 28.12% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 400469737 68.43% 68.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1445270 0.25% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 74848 0.01% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 41036 0.01% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.70% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 101401840 17.33% 86.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 81788668 13.98% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 442579425 68.32% 68.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1577066 0.24% 68.56% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 84316 0.01% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 83107 0.01% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 112773884 17.41% 86.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 90719836 14.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 585221400 # Type of FU issued -system.cpu0.iq.rate 0.724589 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 132569713 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.226529 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2081071755 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 649281804 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 568296572 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1096919 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 437057 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 404655 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 717109128 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 681984 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2687978 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 647817648 # Type of FU issued +system.cpu0.iq.rate 0.740082 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 147632924 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.227893 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2287461115 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 718905040 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 629078745 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1474027 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 598009 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 548346 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 794539840 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 910718 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2963176 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 12198109 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 15815 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 133954 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 5685458 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 13511879 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 17808 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 154801 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 6318307 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2533664 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4860713 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2892844 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5122180 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5126622 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 8215667 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 7173428 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 596307716 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5658893 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 8725604 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7188731 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 660220960 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 98376014 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83834868 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13216543 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 57072 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 7044703 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 133954 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2031236 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2866413 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4897649 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 577519741 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 98358575 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7118543 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 109512073 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 93001551 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 14147683 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 61387 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 7052032 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 154801 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2237378 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 3184169 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5421547 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 639276531 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 109409199 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7914356 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119892 # number of nop insts executed -system.cpu0.iew.exec_refs 178881734 # number of memory reference insts executed -system.cpu0.iew.exec_branches 109041178 # Number of branches executed -system.cpu0.iew.exec_stores 80523159 # Number of stores executed -system.cpu0.iew.exec_rate 0.715054 # Inst execution rate -system.cpu0.iew.wb_sent 569480217 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 568701227 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 276442254 # num instructions producing a value -system.cpu0.iew.wb_consumers 453748356 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.704135 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609241 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 46598328 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15261544 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4598971 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 767596191 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.707129 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.516118 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 129577 # number of nop insts executed +system.cpu0.iew.exec_refs 198721456 # number of memory reference insts executed +system.cpu0.iew.exec_branches 120519027 # Number of branches executed +system.cpu0.iew.exec_stores 89312257 # Number of stores executed +system.cpu0.iew.exec_rate 0.730324 # Inst execution rate +system.cpu0.iew.wb_sent 630467148 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 629627091 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 306648182 # num instructions producing a value +system.cpu0.iew.wb_consumers 503078288 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.719300 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609544 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 51710398 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 16350778 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 5090591 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 832883786 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.721389 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.530255 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 529386438 68.97% 68.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 123369518 16.07% 85.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 53181556 6.93% 91.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 17664925 2.30% 94.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 12675398 1.65% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 8710511 1.13% 97.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5748655 0.75% 97.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3557202 0.46% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 13301988 1.73% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 570514920 68.50% 68.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 134700149 16.17% 84.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 59058098 7.09% 91.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 19776256 2.37% 94.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 14036208 1.69% 95.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 9662272 1.16% 96.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6431324 0.77% 97.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3992857 0.48% 98.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 14711702 1.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 767596191 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 462839739 # Number of instructions committed -system.cpu0.commit.committedOps 542789800 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 832883786 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 511876907 # Number of instructions committed +system.cpu0.commit.committedOps 600832864 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 164327314 # Number of memory references committed -system.cpu0.commit.loads 86177904 # Number of loads committed -system.cpu0.commit.membars 3634236 # Number of memory barriers committed -system.cpu0.commit.branches 103555612 # Number of branches committed -system.cpu0.commit.fp_insts 396011 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 497579695 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13818381 # Number of function calls committed. +system.cpu0.commit.refs 182683437 # Number of memory references committed +system.cpu0.commit.loads 96000193 # Number of loads committed +system.cpu0.commit.membars 3986424 # Number of memory barriers committed +system.cpu0.commit.branches 114418082 # Number of branches committed +system.cpu0.commit.fp_insts 535391 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 551244640 # Number of committed integer instructions. +system.cpu0.commit.function_calls 15252520 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 377157891 69.49% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1210852 0.22% 69.71% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 58620 0.01% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.72% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 35123 0.01% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.73% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 86177904 15.88% 85.60% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 78149410 14.40% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 416691372 69.35% 69.35% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1318004 0.22% 69.57% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 66523 0.01% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 73528 0.01% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 96000193 15.98% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 86683244 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 542789800 # Class of committed instruction -system.cpu0.commit.bw_lim_events 13301988 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1339296609 # The number of ROB reads -system.cpu0.rob.rob_writes 1187626415 # The number of ROB writes -system.cpu0.timesIdled 1008617 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 31177732 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93980302134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 462839739 # Number of Instructions Simulated -system.cpu0.committedOps 542789800 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.745009 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.745009 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.573063 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.573063 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 681400785 # number of integer regfile reads -system.cpu0.int_regfile_writes 404691660 # number of integer regfile writes -system.cpu0.fp_regfile_reads 669454 # number of floating regfile reads -system.cpu0.fp_regfile_writes 305508 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127155216 # number of cc regfile reads -system.cpu0.cc_regfile_writes 127713312 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1347757085 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15341922 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6037671 # number of replacements -system.cpu0.dcache.tags.tagsinuse 477.387062 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 152039806 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6038183 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 25.179728 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 600832864 # Class of committed instruction +system.cpu0.commit.bw_lim_events 14711702 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1466105636 # The number of ROB reads +system.cpu0.rob.rob_writes 1314872451 # The number of ROB writes +system.cpu0.timesIdled 1097159 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 32625462 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93833152963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 511876907 # Number of Instructions Simulated +system.cpu0.committedOps 600832864 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.710046 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.710046 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.584780 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.584780 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 754446272 # number of integer regfile reads +system.cpu0.int_regfile_writes 448604038 # number of integer regfile writes +system.cpu0.fp_regfile_reads 881646 # number of floating regfile reads +system.cpu0.fp_regfile_writes 476304 # number of floating regfile writes +system.cpu0.cc_regfile_reads 139793568 # number of cc regfile reads +system.cpu0.cc_regfile_writes 140496633 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1470350924 # number of misc regfile reads +system.cpu0.misc_regfile_writes 16456285 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 6559473 # number of replacements +system.cpu0.dcache.tags.tagsinuse 490.326221 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 169584910 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6559985 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 25.851417 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 477.387062 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.932397 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.932397 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.326221 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957668 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.957668 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 341097294 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 341097294 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 79771007 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 79771007 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67422867 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 67422867 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213459 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 213459 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258123 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 258123 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1760749 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1760749 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1785447 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1785447 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147193874 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147193874 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147407333 # number of overall hits -system.cpu0.dcache.overall_hits::total 147407333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6628879 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6628879 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7648651 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7648651 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 727328 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 727328 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823977 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 823977 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 249122 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 249122 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189214 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 189214 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14277530 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14277530 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15004858 # number of overall misses -system.cpu0.dcache.overall_misses::total 15004858 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 114348877500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 114348877500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 176760598457 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 176760598457 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91829921579 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 91829921579 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3934102000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3934102000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5393439500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5393439500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4601000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4601000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 291109475957 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 291109475957 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 291109475957 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 291109475957 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86399886 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 86399886 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75071518 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 75071518 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 940787 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 940787 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082100 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1082100 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009871 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2009871 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1974661 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1974661 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 161471404 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 161471404 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 162412191 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 162412191 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076723 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.076723 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101885 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.101885 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.773106 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.773106 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.761461 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.761461 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123949 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123949 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095821 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095821 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.088421 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.088421 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092388 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.092388 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17250.107824 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17250.107824 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23110.035803 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23110.035803 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111447.190369 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111447.190369 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15791.869044 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15791.869044 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28504.442060 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28504.442060 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 379087602 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 379087602 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 89088742 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 89088742 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75269986 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75269986 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228422 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 228422 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263534 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 263534 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1920078 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1920078 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1972778 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1972778 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 164358728 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 164358728 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 164587150 # number of overall hits +system.cpu0.dcache.overall_hits::total 164587150 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 7258058 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7258058 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 8107301 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 8107301 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768102 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 768102 # number of SoftPFReq misses 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StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7820000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 310197257322 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 310197257322 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 310197257322 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 310197257322 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 96346800 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 96346800 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 83377287 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 83377287 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 996524 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 996524 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1118959 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1118959 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207375 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2207375 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2166297 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2166297 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 179724087 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 179724087 # number of demand (read+write) accesses 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0.130153 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130153 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089332 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089332 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085494 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.085494 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089273 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.089273 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16952.624449 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16952.624449 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23084.640107 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23084.640107 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 108456.188601 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 108456.188601 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15820.215665 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15820.215665 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28632.111059 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28632.111059 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20389.344372 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20389.344372 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19401.015055 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19401.015055 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 28956080 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 26869955 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 763930 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 756063 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.904101 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 35.539307 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20188.090452 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20188.090452 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19226.950579 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 19226.950579 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 29213495 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 28830141 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 790800 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 799061 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.941698 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 36.080025 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6037757 # number of writebacks -system.cpu0.dcache.writebacks::total 6037757 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3397304 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3397304 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6149640 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6149640 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4348 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 4348 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 126499 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 126499 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9546944 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9546944 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9546944 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9546944 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3231575 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3231575 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1499011 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1499011 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 720499 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 720499 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 819629 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 819629 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122623 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122623 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189214 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 189214 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4730586 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4730586 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5451085 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5451085 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32157 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64121 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51760022500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51760022500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40775562681 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 40775562681 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18675421500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18675421500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90765682079 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90765682079 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1771728000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1771728000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5204285500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5204285500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4541000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4541000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92535585181 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 92535585181 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111211006681 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 111211006681 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6175664000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6175664000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6047364000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6047364000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12223028000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12223028000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037403 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037403 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019968 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019968 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765847 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765847 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.757443 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.757443 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061010 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095821 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095821 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029297 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029297 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033563 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033563 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16016.964638 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16016.964638 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27201.643404 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27201.643404 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25920.121333 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25920.121333 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 110739.959273 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 110739.959273 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14448.578162 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14448.578162 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27504.759162 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27504.759162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 6559531 # number of writebacks +system.cpu0.dcache.writebacks::total 6559531 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3685333 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3685333 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6510101 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 6510101 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4620 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 4620 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 146516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 10195434 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 10195434 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 10195434 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 10195434 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3572725 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3572725 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1597200 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1597200 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 761247 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 761247 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 850805 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 850805 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140781 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140781 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193511 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 193511 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5169925 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5169925 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5931172 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5931172 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32878 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65819 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56556979500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56556979500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 42701336905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42701336905 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18998780500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18998780500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 91672230134 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 91672230134 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2014552000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2014552000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5347454500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5347454500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7712000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7712000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99258316405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 99258316405 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 118257096905 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 118257096905 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6293183000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6293183000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6230446500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6230446500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12523629500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12523629500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019156 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763902 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763902 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760354 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760354 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063778 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063778 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089328 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089328 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028766 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028766 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032820 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032820 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15830.207895 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15830.207895 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26735.122029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26735.122029 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24957.445481 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24957.445481 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 107747.639158 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 107747.639158 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14309.828741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14309.828741 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27633.852856 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27633.852856 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19561.125235 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19561.125235 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20401.627691 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20401.627691 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192047.268091 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192047.268091 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189192.967088 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189192.967088 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190624.413219 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190624.413219 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19199.179177 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19199.179177 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19938.234282 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19938.234282 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191410.152686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191410.152686 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189139.567712 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189139.567712 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190273.773530 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190273.773530 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5991449 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.937020 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 207384617 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5991961 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.610475 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 21603135000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937020 # Average occupied blocks per requestor +system.cpu0.icache.tags.replacements 6707377 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.936942 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 228724396 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6707889 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.097821 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 21622819000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936942 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 433456796 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 433456796 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 207384617 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 207384617 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 207384617 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 207384617 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 207384617 # number of overall hits -system.cpu0.icache.overall_hits::total 207384617 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6347783 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6347783 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6347783 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6347783 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6347783 # number of overall misses -system.cpu0.icache.overall_misses::total 6347783 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72771579605 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 72771579605 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 72771579605 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 72771579605 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 72771579605 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 72771579605 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 213732400 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 213732400 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 213732400 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 213732400 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 213732400 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 213732400 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029700 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029700 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029700 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029700 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029700 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029700 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11464.093780 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11464.093780 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11464.093780 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11464.093780 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 11432767 # number of cycles access was blocked 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of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 1787 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 839174 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.611407 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 127.642857 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 5991449 # number of writebacks -system.cpu0.icache.writebacks::total 5991449 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355787 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 355787 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 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65359568752 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 65359568752 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 71756007072 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 71756007072 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 71756007072 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 71756007072 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 71756007072 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 71756007072 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028035 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028035 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10907.812481 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028445 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028445 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028445 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10697.205151 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8312308 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8321741 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 8453 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 8921966 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 8932201 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 9178 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1049931 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2736768 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15876.012159 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 17362528 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2752871 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.307062 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1125087 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2909208 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16158.656650 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 19404404 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2925253 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.633411 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14917.842100 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.317341 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.112590 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 828.740128 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.910513 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004292 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003608 # Average 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per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15221.688116 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.041534 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.344722 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000040 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 812.582238 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.929058 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003726 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003866 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049596 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986246 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1170 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14800 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 338 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1270 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5895 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4592 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2939 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074036 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903992 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 412851946 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 412851946 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 601484 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 195644 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 797128 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3986432 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3986432 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 8040621 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 8040621 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 576 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 576 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of 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-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34459.268133 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38492.382138 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38492.382138 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 134486.414137 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 134486.414137 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40764.387598 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50652.711230 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.218494 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51181.463946 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 73680.499500 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29805.846010 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29805.846010 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20120.704683 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20120.704683 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 530768.923077 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 530768.923077 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 61287.090469 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 61287.090469 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33985.476098 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38663.373624 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38663.373624 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 131960.143226 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 131960.143226 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40638.435405 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 51102.429562 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184042.650123 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162737.923293 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181511.261638 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181511.261638 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183403.887098 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162633.798527 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181462.644334 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181462.644334 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182780.765537 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169763.363933 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182432.336666 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169753.839505 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 24968942 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12837433 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2144 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 2067889 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2067431 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 458 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 957998 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11124580 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31965 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5704814 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 8040643 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2700571 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1106688 # Transaction distribution +system.cpu0.toL2Bus.snoop_filter.tot_requests 27467007 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14098216 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2397 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 2174971 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2174417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 554 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 1027741 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 12311555 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 6114023 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 8970970 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2853143 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1178619 # Transaction distribution system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 482477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344108 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 518232 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1334424 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1260303 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5991996 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5072927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 824948 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 817802 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18016682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19524167 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428300 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294882 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 39264031 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 767195088 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 734396467 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4909864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1508140643 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 7265658 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20566582 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.118168 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.322876 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::UpgradeReq 489036 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343853 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 531725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 106 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1422561 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1350501 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6707921 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5424362 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 856015 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 848782 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20165788 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21120167 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 459340 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1399304 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 43144599 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 858918672 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 799305801 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1762224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5318384 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1665305081 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 7537626 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 22154436 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.115021 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.319126 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 18136730 88.19% 88.19% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2429394 11.81% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 458 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 19606761 88.50% 88.50% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2547121 11.50% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 554 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20566582 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 24844807916 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 22154436 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 27362140922 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 204855996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 207113536 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9015512485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 10089828109 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8672428624 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9431575123 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 223891503 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 239573965 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 681731807 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 735155181 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 134041815 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89707660 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6609017 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 94187638 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 61197396 # Number of BTB hits +system.cpu1.branchPred.lookups 119891525 # Number of BP lookups +system.cpu1.branchPred.condPredicted 80198528 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5904198 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 84182887 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 54925615 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.973915 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17950728 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 175820 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.245583 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16054982 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 157154 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,90 +1727,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 567287 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 567287 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11327 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89325 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 259417 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 307870 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2446.318251 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 14947.483095 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 305492 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1236 0.40% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 840 0.27% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 307870 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 284687 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20644.869629 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17424.592515 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 21452.651975 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 281397 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 951 0.33% 99.18% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1579 0.55% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 108 0.04% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 394 0.14% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 106 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 102 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 31 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 523591 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 523591 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9887 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82113 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 242894 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 280697 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2503.193835 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 14937.525211 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 278494 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1255 0.45% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 659 0.23% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 166 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 38 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 280697 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 263545 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19785.484452 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17259.480271 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16001.974136 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 261738 99.31% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 658 0.25% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 820 0.31% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 79 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 151 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 47 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 31 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 284687 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 488633591384 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.617867 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.545160 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 487382306384 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 662548500 0.14% 99.88% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 271218500 0.06% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 131442000 0.03% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 92501000 0.02% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 52739500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 15718500 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 24644000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 457500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 488633591384 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 89326 88.75% 88.75% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11327 11.25% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 100653 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 567287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 263545 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 427419381904 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.550644 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.560610 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 426298998404 99.74% 99.74% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 579725500 0.14% 99.87% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 235009500 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 123480000 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 88192000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 51481500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 16753000 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 25205500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 518000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 18500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 427419381904 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 82114 89.25% 89.25% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 9887 10.75% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 92001 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 523591 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 567287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100653 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 523591 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92001 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100653 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 667940 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92001 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 615592 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 99577859 # DTB read hits -system.cpu1.dtb.read_misses 392921 # DTB read misses -system.cpu1.dtb.write_hits 81911984 # DTB write hits -system.cpu1.dtb.write_misses 174366 # DTB write misses +system.cpu1.dtb.read_hits 88459625 # DTB read hits +system.cpu1.dtb.read_misses 355289 # DTB read misses +system.cpu1.dtb.write_hits 73058314 # DTB write hits +system.cpu1.dtb.write_misses 168302 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37295 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 442 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 6095 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 34429 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 243 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5558 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 38665 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 99970780 # DTB read accesses -system.cpu1.dtb.write_accesses 82086350 # DTB write accesses +system.cpu1.dtb.perms_faults 38457 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 88814914 # DTB read accesses +system.cpu1.dtb.write_accesses 73226616 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 181489843 # DTB hits -system.cpu1.dtb.misses 567287 # DTB misses -system.cpu1.dtb.accesses 182057130 # DTB accesses +system.cpu1.dtb.hits 161517939 # DTB hits +system.cpu1.dtb.misses 523591 # DTB misses +system.cpu1.dtb.accesses 162041530 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1831,1165 +1837,1156 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 85422 # Table walker walks requested -system.cpu1.itb.walker.walksLong 85422 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 706 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60440 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 10533 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 74889 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1637.737184 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12543.180008 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 74488 99.46% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 92 0.12% 99.59% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 279 0.37% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 13 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74889 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26447.767128 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 22834.132885 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 26054.956905 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70042 97.72% 97.72% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 124 0.17% 97.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1290 1.80% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 62 0.09% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 94 0.13% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 27 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71679 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 419883309648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.857166 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.350104 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 59999474576 14.29% 14.29% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 359861735072 85.71% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 18604000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 3422000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 61500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 419883309648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 60440 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 706 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61146 # Table walker page sizes translated +system.cpu1.itb.walker.walks 79238 # Table walker walks requested +system.cpu1.itb.walker.walksLong 79238 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 670 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55768 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9704 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 69534 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1362.196911 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 10189.827482 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 68875 99.05% 99.05% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 429 0.62% 99.67% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 22 0.03% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 45 0.06% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 97 0.14% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 46 0.07% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69534 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 66142 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 24972.294457 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22450.763423 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 20128.243900 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 65282 98.70% 98.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 106 0.16% 98.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 635 0.96% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 41 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 66142 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 405913969924 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.852777 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.354498 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 59781305300 14.73% 14.73% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 346114009624 85.27% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 16127000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 2369500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 82500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 76000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 405913969924 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 55768 98.81% 98.81% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 670 1.19% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 56438 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85422 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85422 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79238 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79238 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61146 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61146 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 146568 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 210903230 # ITB inst hits -system.cpu1.itb.inst_misses 85422 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56438 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56438 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 135676 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 188743149 # ITB inst hits +system.cpu1.itb.inst_misses 79238 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26936 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 24595 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 219212 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 203696 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 210988652 # ITB inst accesses -system.cpu1.itb.hits 210903230 # DTB hits -system.cpu1.itb.misses 85422 # DTB misses -system.cpu1.itb.accesses 210988652 # DTB accesses -system.cpu1.numCycles 739589068 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 188822387 # ITB inst accesses +system.cpu1.itb.hits 188743149 # DTB hits +system.cpu1.itb.misses 79238 # DTB misses +system.cpu1.itb.accesses 188822387 # DTB accesses +system.cpu1.numCycles 668763369 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 87179307 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 594353675 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 134041815 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 79148124 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 611930141 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 14224484 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1980961 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 327085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6413771 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 794469 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 836341 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 210662459 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1674863 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 29397 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 716574317 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.975535 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.220237 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 76762482 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 531105996 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 119891525 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 70980597 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 555217707 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12731518 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1797928 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 295013 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 5987179 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 752221 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 763722 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 188519405 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1489379 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 27517 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 647942011 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.963740 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.217002 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 382171132 53.33% 53.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 130053591 18.15% 71.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 44058900 6.15% 77.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 160290694 22.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 349005233 53.86% 53.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 116425876 17.97% 71.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 39511198 6.10% 77.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 142999704 22.07% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 716574317 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.181238 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.803627 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 104297157 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 348522347 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 221906314 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 36809016 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5039483 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 18926425 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 2113724 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 618028101 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 22771231 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5039483 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 138949493 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 52143991 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 230343934 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 223632177 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 66465239 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 601445820 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5788119 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 10817316 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 260401 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 332552 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 31997393 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 11898 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 571172784 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 925552885 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 711516112 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 817303 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 514566329 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 56606455 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15686724 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13790746 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 74346046 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 99668213 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85253354 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 9496006 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 8106709 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 579162522 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15985308 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 584188542 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2667167 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 53686437 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 34500302 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 290258 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 716574317 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.815252 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.066417 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 647942011 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.179273 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.794161 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 92682171 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 320350015 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 196661442 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 33741382 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4507001 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 16971690 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1895430 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 551371568 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 20348682 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4507001 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 124070698 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 47114866 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 212074227 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 198637530 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 61537689 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 536563152 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5145214 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 9840770 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 223861 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 282097 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 29934469 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 10810 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 509803663 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 829081125 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 634679636 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 600803 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 459431302 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 50372361 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14562905 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12854163 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 68041373 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 88476596 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 76035338 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8565835 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7285035 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 516079501 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14870100 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 521291240 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2377203 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 47872437 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 30743352 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 257935 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 647942011 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.804534 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.061029 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 397414827 55.46% 55.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 134713914 18.80% 74.26% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 111740906 15.59% 89.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 64830862 9.05% 98.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7868810 1.10% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 4998 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 361872507 55.85% 55.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 122353667 18.88% 74.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 99252241 15.32% 90.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 57424869 8.86% 98.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7035151 1.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 3576 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 716574317 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 647942011 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 59065524 44.03% 44.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 54166 0.04% 44.07% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 19277 0.01% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.09% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36039894 26.87% 70.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 38965641 29.05% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 52040674 43.67% 43.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 50092 0.04% 43.71% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 18388 0.02% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 16 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 32200400 27.02% 70.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 34865580 29.26% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 396970173 67.95% 67.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1317793 0.23% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 74565 0.01% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 1 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 84907 0.01% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 102569706 17.56% 85.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 83171310 14.24% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 354670500 68.04% 68.04% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1183955 0.23% 68.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 65513 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 42657 0.01% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 91135432 17.48% 85.77% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 74193108 14.23% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 584188542 # Type of FU issued -system.cpu1.iq.rate 0.789883 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 134144524 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.229625 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 2020390722 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 648436438 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 567390385 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1372370 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 557189 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 510457 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 717484509 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 848517 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2681981 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 521291240 # Type of FU issued +system.cpu1.iq.rate 0.779485 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 119175150 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.228615 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1811086365 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 578565811 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 506287229 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 990479 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 395514 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 364516 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 639849832 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 616531 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2398408 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 12380566 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16529 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 160745 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5876169 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11063470 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 14436 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 140383 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5257500 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2772484 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 4108210 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2402216 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3864822 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5039483 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6511130 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2319208 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 595271017 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4507001 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 5849706 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2188326 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 531063111 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 99668213 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85253354 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13572161 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64444 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2193101 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 160745 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2023154 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2795718 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4818872 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 576621181 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 99570735 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 7012433 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 88476596 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 76035338 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12650539 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 60907 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2070757 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 140383 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1813068 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2483133 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4296201 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 514538937 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 88454625 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6240485 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 123187 # number of nop insts executed -system.cpu1.iew.exec_refs 181482515 # number of memory reference insts executed -system.cpu1.iew.exec_branches 107903719 # Number of branches executed -system.cpu1.iew.exec_stores 81911780 # Number of stores executed -system.cpu1.iew.exec_rate 0.779651 # Inst execution rate -system.cpu1.iew.wb_sent 568628901 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 567900842 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 274880956 # num instructions producing a value -system.cpu1.iew.wb_consumers 450165977 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.767860 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610621 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 47031076 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15695050 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4536258 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 707685383 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.765116 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.566861 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 113510 # number of nop insts executed +system.cpu1.iew.exec_refs 161513914 # number of memory reference insts executed +system.cpu1.iew.exec_branches 96416033 # Number of branches executed +system.cpu1.iew.exec_stores 73059289 # Number of stores executed +system.cpu1.iew.exec_rate 0.769389 # Inst execution rate +system.cpu1.iew.wb_sent 507314383 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 506651745 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 244576343 # num instructions producing a value +system.cpu1.iew.wb_consumers 400655745 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.757595 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.610440 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 41944033 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14612165 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4045440 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 639995571 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.754813 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.555930 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 470367960 66.47% 66.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 123401303 17.44% 83.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 52359305 7.40% 91.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 17652538 2.49% 93.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 12497517 1.77% 95.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 8502383 1.20% 96.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5935480 0.84% 97.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3482174 0.49% 98.09% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 13486723 1.91% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 426913272 66.71% 66.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 112061055 17.51% 84.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 46474767 7.26% 91.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15512784 2.42% 93.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11149430 1.74% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7505688 1.17% 96.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5285555 0.83% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3055428 0.48% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12037592 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 707685383 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 459224264 # Number of instructions committed -system.cpu1.commit.committedOps 541461392 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 639995571 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 409938912 # Number of instructions committed +system.cpu1.commit.committedOps 483077163 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 166664832 # Number of memory references committed -system.cpu1.commit.loads 87287647 # Number of loads committed -system.cpu1.commit.membars 3905531 # Number of memory barriers committed -system.cpu1.commit.branches 102374979 # Number of branches committed -system.cpu1.commit.fp_insts 497703 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 497469676 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13371734 # Number of function calls committed. +system.cpu1.commit.refs 148190964 # Number of memory references committed +system.cpu1.commit.loads 77413126 # Number of loads committed +system.cpu1.commit.membars 3553266 # Number of memory barriers committed +system.cpu1.commit.branches 91478423 # Number of branches committed +system.cpu1.commit.fp_insts 356192 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 443462583 # Number of committed integer instructions. +system.cpu1.commit.function_calls 11919697 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 373594883 69.00% 69.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1066183 0.20% 69.19% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 59540 0.01% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 75912 0.01% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 87287647 16.12% 85.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 79377185 14.66% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 333838399 69.11% 69.11% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 958189 0.20% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 52064 0.01% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 37505 0.01% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 77413126 16.03% 85.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 70777838 14.65% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 541461392 # Class of committed instruction -system.cpu1.commit.bw_lim_events 13486723 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1278856692 # The number of ROB reads -system.cpu1.rob.rob_writes 1185834230 # The number of ROB writes -system.cpu1.timesIdled 958439 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 23014751 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94048355585 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 459224264 # Number of Instructions Simulated -system.cpu1.committedOps 541461392 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.610518 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.610518 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.620918 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.620918 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 681935687 # number of integer regfile reads -system.cpu1.int_regfile_writes 403917801 # number of integer regfile writes -system.cpu1.fp_regfile_reads 803668 # number of floating regfile reads -system.cpu1.fp_regfile_writes 473340 # number of floating regfile writes -system.cpu1.cc_regfile_reads 122826591 # number of cc regfile reads -system.cpu1.cc_regfile_writes 123738784 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1267794356 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15807378 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5498905 # number of replacements -system.cpu1.dcache.tags.tagsinuse 458.394450 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 155608106 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5499414 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.295398 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.394450 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895302 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.895302 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 416 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 345701865 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 345701865 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 81166944 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 81166944 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 69652711 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 69652711 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 179570 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 179570 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55554 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 55554 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1867218 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1867218 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1906025 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1906025 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150819655 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150819655 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150999225 # number of overall hits -system.cpu1.dcache.overall_hits::total 150999225 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6513815 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6513815 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 7138740 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 7138740 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 666746 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 666746 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433208 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 433208 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 280157 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 280157 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195063 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 195063 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13652555 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13652555 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 14319301 # number of overall misses -system.cpu1.dcache.overall_misses::total 14319301 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 107790302500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 107790302500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 154935306923 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 154935306923 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17952138757 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 17952138757 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4403404000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 4403404000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5419622500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5419622500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3200000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3200000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 262725609423 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 262725609423 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 262725609423 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 262725609423 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87680759 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87680759 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 76791451 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 76791451 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 846316 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 846316 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 488762 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 488762 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2147375 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2147375 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2101088 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2101088 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 164472210 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 164472210 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 165318526 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 165318526 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074290 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.074290 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092963 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.092963 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787822 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787822 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.886337 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.886337 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130465 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130465 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092839 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092839 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083008 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.083008 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086616 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.086616 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16547.952697 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16547.952697 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21703.452839 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21703.452839 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41439.998239 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41439.998239 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15717.629758 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15717.629758 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27783.959541 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27783.959541 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 483077163 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12037592 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1149378464 # The number of ROB reads +system.cpu1.rob.rob_writes 1057951201 # The number of ROB writes +system.cpu1.timesIdled 862725 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 20821358 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 94039702456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 409938912 # Number of Instructions Simulated +system.cpu1.committedOps 483077163 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.631373 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.631373 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.612981 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.612981 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 608507800 # number of integer regfile reads +system.cpu1.int_regfile_writes 359700181 # number of integer regfile writes +system.cpu1.fp_regfile_reads 588843 # number of floating regfile reads +system.cpu1.fp_regfile_writes 298828 # number of floating regfile writes +system.cpu1.cc_regfile_reads 110183943 # number of cc regfile reads +system.cpu1.cc_regfile_writes 110950246 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1143200959 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14699928 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 4943818 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.490717 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 138046990 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4944322 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.920307 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8486298300000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.490717 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889630 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.889630 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 307427480 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 307427480 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 71852716 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 71852716 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 61790747 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 61790747 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 162379 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 162379 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50057 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 50057 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1706960 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1706960 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1722622 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1722622 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 133643463 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 133643463 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 133805842 # number of overall hits +system.cpu1.dcache.overall_hits::total 133805842 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 5820950 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 5820950 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6630483 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6630483 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 628859 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 628859 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 401328 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 401328 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243245 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 243245 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186259 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 186259 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 12451433 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 12451433 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13080292 # number of overall misses +system.cpu1.dcache.overall_misses::total 13080292 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96708932500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 96708932500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 144491403356 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 144491403356 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16631824083 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 16631824083 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3760760000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3760760000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5141971500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5141971500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6754500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6754500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 241200335856 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 241200335856 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 241200335856 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 241200335856 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 77673666 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 77673666 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 68421230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 68421230 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 791238 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 791238 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 451385 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 451385 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1950205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1950205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1908881 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1908881 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146094896 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146094896 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146886134 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146886134 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074941 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074941 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.096907 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.096907 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794779 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794779 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889104 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889104 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124728 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124728 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097575 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097575 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085228 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.085228 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089051 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.089051 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16613.943171 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16613.943171 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21791.987606 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21791.987606 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41441.972858 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41441.972858 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15460.790561 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15460.790561 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27606.566663 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27606.566663 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19243.695369 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19243.695369 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18347.656036 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18347.656036 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4719493 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 24576154 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 351674 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 713575 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.420079 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34.440884 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19371.291309 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19371.291309 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18439.980992 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18439.980992 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4381553 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 22968096 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 326353 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 670571 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.425809 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 34.251550 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5498938 # number of writebacks -system.cpu1.dcache.writebacks::total 5498938 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3304670 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3304670 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5753104 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5753104 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3561 # number of WriteLineReq MSHR hits -system.cpu1.dcache.WriteLineReq_mshr_hits::total 3561 # number of WriteLineReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 144550 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 144550 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 9057774 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 9057774 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 9057774 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 9057774 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3209145 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3209145 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1385636 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1385636 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 666638 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 666638 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 429647 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 429647 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135607 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135607 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195058 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4594781 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4594781 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5261419 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5261419 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6299 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12727 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 49159510500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49159510500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 33253300624 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 33253300624 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15899737000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15899737000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17350623757 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17350623757 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1958308000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1958308000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5224605500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5224605500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3159000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3159000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82412811124 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 82412811124 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 98312548124 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 98312548124 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 727883500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 727883500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859834500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859834500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1587718000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1587718000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018044 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018044 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787694 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787694 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879052 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879052 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063150 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063150 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092837 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092837 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027937 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027937 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031826 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031826 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15318.569432 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15318.569432 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23998.583051 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23998.583051 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23850.631077 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23850.631077 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40383.439794 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40383.439794 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14441.053928 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14441.053928 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26784.881933 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26784.881933 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4943833 # number of writebacks +system.cpu1.dcache.writebacks::total 4943833 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2977175 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 2977175 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5355618 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5355618 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3078 # number of WriteLineReq MSHR hits +system.cpu1.dcache.WriteLineReq_mshr_hits::total 3078 # number of WriteLineReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125917 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125917 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8332793 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8332793 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8332793 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8332793 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2843775 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2843775 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1274865 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1274865 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628773 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 628773 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 398250 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 398250 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117328 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117328 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186249 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 186249 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4118640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4118640 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4747413 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4747413 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5429 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10713 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43326231000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43326231000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30961849442 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30961849442 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15267610500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15267610500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16078596583 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16078596583 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1709363500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1709363500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4955815500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4955815500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6661500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6661500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74288080442 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 74288080442 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89555690942 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 89555690942 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604887500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 604887500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 670175500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 670175500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1275063000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1275063000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036612 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036612 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018633 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018633 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794670 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794670 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.882285 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.882285 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060162 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060162 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097570 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097570 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028192 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032320 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032320 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15235.463776 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15235.463776 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24286.374982 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24286.374982 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24281.593675 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24281.593675 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40373.123874 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40373.123874 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14569.101152 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14569.101152 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26608.548234 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26608.548234 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17936.178269 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17936.178269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18685.557665 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18685.557665 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 115555.405620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 115555.405620 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133763.923460 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 133763.923460 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124751.944685 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124751.944685 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.041461 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18037.041461 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18864.103659 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18864.103659 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111417.848591 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 111417.848591 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126831.093868 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 126831.093868 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119020.162419 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119020.162419 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5972259 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.613786 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 204337040 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5972771 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.211431 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.613786 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979714 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.979714 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5253385 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.776230 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 182951519 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5253897 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 34.822060 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8525973531000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.776230 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980032 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980032 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 427283163 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 427283163 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 204337040 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 204337040 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 204337040 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 204337040 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 204337040 # number of overall hits -system.cpu1.icache.overall_hits::total 204337040 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 6318152 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 6318152 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 6318152 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 6318152 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 6318152 # number of overall misses -system.cpu1.icache.overall_misses::total 6318152 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 69955140831 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 69955140831 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 69955140831 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 69955140831 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 69955140831 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 69955140831 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 210655192 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 210655192 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 210655192 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 210655192 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 210655192 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 210655192 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029993 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029993 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029993 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029993 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029993 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029993 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11072.088932 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 11072.088932 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 11072.088932 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 11072.088932 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 10670268 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 1157 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 748022 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.264645 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 144.625000 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 382279380 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 382279380 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 182951519 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 182951519 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 182951519 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 182951519 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 182951519 # number of overall hits +system.cpu1.icache.overall_hits::total 182951519 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5561220 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5561220 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5561220 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5561220 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5561220 # number of overall misses +system.cpu1.icache.overall_misses::total 5561220 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62243274721 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 62243274721 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 62243274721 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 62243274721 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 62243274721 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 62243274721 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 188512739 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 188512739 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 188512739 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 188512739 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 188512739 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 188512739 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029500 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029500 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029500 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029500 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029500 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029500 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11192.377701 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 11192.377701 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 11192.377701 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 11192.377701 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 9679381 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 762 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 668024 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.489571 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 5972259 # number of writebacks -system.cpu1.icache.writebacks::total 5972259 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 345373 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 345373 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 345373 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 345373 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 345373 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 345373 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5972779 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5972779 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5972779 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5972779 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5972779 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5972779 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 5253385 # number of writebacks +system.cpu1.icache.writebacks::total 5253385 # number of writebacks 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number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 63045966777 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028353 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028353 # mshr miss rate for demand accesses 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-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56076616223 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 56076616223 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56076616223 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 56076616223 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56076616223 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 56076616223 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9266998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9266998 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9266998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9266998 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027870 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.027870 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for overall accesses 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68.405438 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000005 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 667.153246 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.766763 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004095 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004175 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040720 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.815752 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1289 # Occupied blocks per task id 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0.003248 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003388 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044426 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.815418 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1266 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 101 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14252 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 87 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 167 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id 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192926 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 5413940 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3859216 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 10053216 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 587134 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 192926 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 5413940 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3859216 # number of overall hits -system.cpu1.l2cache.overall_hits::total 10053216 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12541 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9429 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 21970 # number of ReadReq misses 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-system.cpu1.l2cache.ReadSharedReq_miss_latency::total 40947637491 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14994721499 # number of InvalidateReq miss cycles -system.cpu1.l2cache.InvalidateReq_miss_latency::total 14994721499 # number of InvalidateReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 648758500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 531765000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21287303500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 57037204991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 79505031991 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 648758500 # number of overall miss cycles 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miss rate for WritebackDirty accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses -system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10780 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 314747000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 750932000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40592481689 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7117149993 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7117149993 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3556198494 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3556198494 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5961498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5961498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11593238999 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11593238999 # number of ReadExReq MSHR miss cycles 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16408482000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 42945541485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 60104955485 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 314747000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16408482000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 42945541485 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 100697437174 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8763500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 561342500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 570106000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 630451500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 630451500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8763500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1191794000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1200557500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026804 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses +system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996614 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996614 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999990 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997593 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997593 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222329 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222329 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093564 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.249012 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249012 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.552554 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.552554 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153745 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.235701 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.235701 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097211 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261133 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261133 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562593 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562593 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161372 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218798 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 47696.316200 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60275.447456 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31180.899835 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31180.899835 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19270.223778 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19270.223778 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2850999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2850999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48033.169385 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48033.169385 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32092.287527 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34717.232569 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34717.232569 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 57409.047655 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 57409.047655 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35935.044345 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43171.931250 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107536.434355 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 107713.556393 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126250.544493 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 126250.544493 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116988.331893 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 117026.965765 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228955 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38153.236460 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56526.199996 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30720.803520 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30720.803520 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19094.913466 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19094.913466 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 541954.363636 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 541954.363636 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46776.544018 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46776.544018 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32126.941549 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33480.096542 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33480.096542 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 56378.079768 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 56378.079768 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35052.548527 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41391.104169 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 103397.034445 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 103731.077147 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119313.304315 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119313.304315 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 111247.456361 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 111368.970315 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 23835470 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12272459 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1390 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 2000895 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2000561 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 900425 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10970003 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6428 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4651207 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 8011843 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2673516 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 976496 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 21246355 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10958434 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1131 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1866438 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1866138 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 300 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 825754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9752282 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4201386 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 7090370 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2466487 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 905169 # Transaction distribution system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 442024 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347278 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 498740 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1227372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1161574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5972779 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4961310 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 435892 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 427958 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17917345 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17734263 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 424426 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1271663 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 37347697 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 764444720 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 688461274 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1618840 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4797400 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1459322234 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 6483444 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19136823 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.123774 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.329377 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeReq 447608 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337242 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 479463 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1130462 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1058321 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5253902 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4579290 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 402900 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 396573 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15761317 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16025111 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 394044 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1160504 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 33340976 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 672467056 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 619232766 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1502776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4371544 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1297574142 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 6151657 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 17448758 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.126682 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.332668 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 16768514 87.62% 87.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2367975 12.37% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 15238612 87.33% 87.33% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2209846 12.66% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 300 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19136823 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 23662576976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 17448758 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 21067285470 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 176028266 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 170823638 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8965097194 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7886135987 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8193842587 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7380840948 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 222514103 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 206620146 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 672743976 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 614769571 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40336 # Transaction distribution -system.iobus.trans_dist::ReadResp 40336 # Transaction distribution -system.iobus.trans_dist::WriteReq 136625 # Transaction distribution -system.iobus.trans_dist::WriteResp 136625 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40283 # Transaction distribution +system.iobus.trans_dist::ReadResp 40283 # Transaction distribution +system.iobus.trans_dist::WriteReq 136631 # Transaction distribution +system.iobus.trans_dist::WriteResp 136631 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -3002,13 +2999,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122562 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231280 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231280 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353922 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -3021,101 +3018,101 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155669 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339136 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339136 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338672 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338672 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496891 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36916001 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36944000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 24643501 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 24787502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36442501 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36442000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565518728 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567400129 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92668000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147976000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147860000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115636 # number of replacements -system.iocache.tags.tagsinuse 11.302848 # Cycle average of tags in use +system.iocache.tags.replacements 115578 # number of replacements +system.iocache.tags.tagsinuse 11.298905 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115652 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115594 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9125688591000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.411882 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.890966 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463243 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.243185 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706428 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9125697698000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.418105 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.880800 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463632 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242550 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706182 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041117 # Number of tag accesses -system.iocache.tags.data_accesses 1041117 # Number of data accesses +system.iocache.tags.tag_accesses 1040595 # Number of tag accesses +system.iocache.tags.data_accesses 1040595 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses -system.iocache.demand_misses::total 8952 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses +system.iocache.demand_misses::total 8894 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8912 # number of overall misses -system.iocache.overall_misses::total 8952 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1705648493 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1710848493 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8854 # number of overall misses +system.iocache.overall_misses::total 8894 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5230500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1713293012 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1718523512 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13974401235 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13974401235 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1705648493 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1711217493 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1705648493 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1711217493 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13529785617 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13529785617 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5599500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1713293012 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1718892512 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5599500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1713293012 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1718892512 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3129,55 +3126,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191387.847060 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191177.616829 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141364.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 193504.970861 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 193287.989203 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130934.724112 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130934.724112 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191154.769102 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191154.769102 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35975 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.848072 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126768.848072 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 193264.280639 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 193264.280639 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34686 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3674 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.791780 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.944381 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1260048493 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1263398493 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3380500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1270593012 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1273973512 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638001235 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8638001235 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1260048493 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1263617493 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1260048493 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1263617493 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8187257903 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8187257903 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3599500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1270593012 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1274192512 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3599500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1270593012 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1274192512 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3191,620 +3188,624 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141387.847060 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141177.616829 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91364.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143504.970861 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 143287.989203 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80934.724112 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80934.724112 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76711.433766 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76711.433766 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1576044 # number of replacements -system.l2c.tags.tagsinuse 63242.380291 # Cycle average of tags in use -system.l2c.tags.total_refs 6232719 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1635533 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.810818 # Average number of references to valid blocks. +system.l2c.tags.replacements 1550465 # number of replacements +system.l2c.tags.tagsinuse 63029.233494 # Cycle average of tags in use +system.l2c.tags.total_refs 6222316 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1609843 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.865169 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 20333.059620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.017365 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 59.342117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3579.623644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5086.228075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3815.151087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 296.252046 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 450.100507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3644.907232 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8614.023056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17319.675542 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.310258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000672 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.054621 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.077610 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.058215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004520 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006868 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055617 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.131440 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.264277 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.965002 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9601 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49687 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1158 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 504 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 7939 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40824 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.146500 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.758163 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 79314813 # Number of tag accesses -system.l2c.tags.data_accesses 79314813 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2898844 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2898844 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 4 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 4 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 171467 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 140817 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 312284 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 39034 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 42272 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 81306 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 165571 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 166162 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 331733 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6582 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4549 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 520761 # number of ReadSharedReq hits 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9854.606144 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15763.557433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 96.147248 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 123.490081 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3067.505167 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4557.367994 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3831.673436 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.321652 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003761 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005490 # Average percentage of cache occupancy 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-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.266313 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.316112 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.288249 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.231240 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.224483 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228174 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755522 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.413096 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.662470 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200921 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.165412 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246768 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.333289 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.333289 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70731.256683 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70524.458464 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70631.360557 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73709.083278 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73545.587960 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73636.111663 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155183.159891 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137005.808089 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 152103.004073 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134274.620202 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134773.122390 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 154259.180639 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166037.674534 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89546.847705 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138881.908918 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164494.713834 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109206.207218 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155237.719655 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165399.143105 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 85408.885941 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139208.448018 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164446.132935 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102249.341030 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155848.412897 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165268.516290 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99477.721022 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145275.940706 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164922.181923 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 93716.697040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145706.176668 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 59814 # Transaction distribution -system.membus.trans_dist::ReadResp 1023090 # Transaction distribution -system.membus.trans_dist::WriteReq 38392 # Transaction distribution -system.membus.trans_dist::WriteResp 38392 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1345584 # Transaction distribution -system.membus.trans_dist::CleanEvict 266165 # Transaction distribution -system.membus.trans_dist::UpgradeReq 443726 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 302861 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156448 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 676664 # Transaction distribution -system.membus.trans_dist::ReadExResp 656494 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 963276 # Transaction distribution +system.membus.trans_dist::ReadReq 59665 # Transaction distribution +system.membus.trans_dist::ReadResp 1004280 # Transaction distribution +system.membus.trans_dist::WriteReq 38225 # Transaction distribution +system.membus.trans_dist::WriteResp 38225 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1333923 # Transaction distribution +system.membus.trans_dist::CleanEvict 260984 # Transaction distribution +system.membus.trans_dist::UpgradeReq 453995 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 297100 # Transaction distribution +system.membus.trans_dist::UpgradeResp 23 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 671706 # Transaction distribution +system.membus.trans_dist::ReadExResp 651282 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 944615 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122562 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5690514 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5839062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342298 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342298 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6181360 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155669 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5471994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5619910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5857982 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51820 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182696832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 182904877 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190162093 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 613313 # Total snoops (count) -system.membus.snoop_fanout::samples 4205672 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180426240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 180632999 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7268224 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 187901223 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 614880 # Total snoops (count) +system.membus.snoop_fanout::samples 4166995 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4205672 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4166995 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4205672 # Request fanout histogram -system.membus.reqLayer0.occupancy 98421997 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4166995 # Request fanout histogram +system.membus.reqLayer0.occupancy 98592998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21914471 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21315973 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 9436458556 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9342770498 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8880795227 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 8446463151 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228859415 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45344986 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3858,57 +3859,57 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 12199905 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 6623903 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1949036 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 168152 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 152817 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 15335 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 59816 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4662380 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38392 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38392 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 4244441 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1619343 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 747362 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 384167 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1131529 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1137603 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1137603 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4609811 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 12162467 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 6606326 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1941011 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 162574 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 148386 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14188 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 59667 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4643440 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38225 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38225 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 4233094 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2736996 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 756317 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 379558 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1135875 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 201 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1140134 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1140134 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 4591007 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9241165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7356268 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16597433 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283441843 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 210970938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 494412781 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 3322045 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8775737 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.344900 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.478998 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10341744 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7350795 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17692539 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 299067465 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 193620382 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 492687847 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 3308925 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8737988 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.345814 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.479035 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5764320 65.68% 65.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2996082 34.14% 99.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 15335 0.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5730454 65.58% 65.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2993346 34.26% 99.84% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14188 0.16% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8775737 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 9513972562 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8737988 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 9497901955 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2693663 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2589298 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 5075177047 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5324917465 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4195991011 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3923923162 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12889 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 12950 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5680 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5465 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 25838a319..5a29e8890 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.291806 # Number of seconds simulated -sim_ticks 51291805611000 # Number of ticks simulated -final_tick 51291805611000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.331525 # Number of seconds simulated +sim_ticks 51331524771000 # Number of ticks simulated +final_tick 51331524771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117828 # Simulator instruction rate (inst/s) -host_op_rate 138456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7111926295 # Simulator tick rate (ticks/s) -host_mem_usage 686644 # Number of bytes of host memory used -host_seconds 7212.08 # Real time elapsed on the host -sim_insts 849784302 # Number of instructions simulated -sim_ops 998554740 # Number of ops (including micro ops) simulated +host_inst_rate 185259 # Simulator instruction rate (inst/s) +host_op_rate 217677 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11233724737 # Simulator tick rate (ticks/s) +host_mem_usage 689476 # Number of bytes of host memory used +host_seconds 4569.41 # Real time elapsed on the host +sim_insts 846524467 # Number of instructions simulated +sim_ops 994654061 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 234176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 229184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5702880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 74235720 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 438720 # Number of bytes read from this memory -system.physmem.bytes_read::total 80840680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5702880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5702880 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69030592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 205568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 197440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5696288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 72187912 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 428288 # Number of bytes read from this memory +system.physmem.bytes_read::total 78715496 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5696288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5696288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67280640 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69051172 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3659 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3581 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105060 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1159946 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6855 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1279101 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1078603 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67301220 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3212 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 104957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1127949 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1245895 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1051260 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1081176 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111185 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1447321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1576093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111185 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1345841 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1053833 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 4005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3846 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 110971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1406308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1533473 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1310708 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1346242 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1345841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1447722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2922335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1279101 # Number of read requests accepted -system.physmem.writeReqs 1081176 # Number of write requests accepted -system.physmem.readBursts 1279101 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1081176 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 81811968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50496 # Total number of bytes read from write queue -system.physmem.bytesWritten 69050112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 80840680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 69051172 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 789 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 335568 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 76700 # Per bank write bursts -system.physmem.perBankRdBursts::1 81593 # Per bank write bursts -system.physmem.perBankRdBursts::2 83146 # Per bank write bursts -system.physmem.perBankRdBursts::3 75940 # Per bank write bursts -system.physmem.perBankRdBursts::4 76984 # Per bank write bursts -system.physmem.perBankRdBursts::5 83084 # Per bank write bursts -system.physmem.perBankRdBursts::6 76647 # Per bank write bursts -system.physmem.perBankRdBursts::7 76510 # Per bank write bursts -system.physmem.perBankRdBursts::8 74528 # Per bank write bursts -system.physmem.perBankRdBursts::9 104951 # Per bank write bursts -system.physmem.perBankRdBursts::10 78345 # Per bank write bursts -system.physmem.perBankRdBursts::11 82619 # Per bank write bursts -system.physmem.perBankRdBursts::12 77692 # Per bank write bursts -system.physmem.perBankRdBursts::13 79270 # Per bank write bursts -system.physmem.perBankRdBursts::14 75132 # Per bank write bursts -system.physmem.perBankRdBursts::15 75171 # Per bank write bursts -system.physmem.perBankWrBursts::0 64170 # Per bank write bursts -system.physmem.perBankWrBursts::1 68321 # Per bank write bursts -system.physmem.perBankWrBursts::2 70316 # Per bank write bursts -system.physmem.perBankWrBursts::3 66616 # Per bank write bursts -system.physmem.perBankWrBursts::4 66722 # Per bank write bursts -system.physmem.perBankWrBursts::5 70167 # Per bank write bursts -system.physmem.perBankWrBursts::6 65460 # Per bank write bursts -system.physmem.perBankWrBursts::7 67223 # Per bank write bursts -system.physmem.perBankWrBursts::8 64606 # Per bank write bursts -system.physmem.perBankWrBursts::9 72209 # Per bank write bursts -system.physmem.perBankWrBursts::10 66721 # Per bank write bursts -system.physmem.perBankWrBursts::11 70434 # Per bank write bursts -system.physmem.perBankWrBursts::12 67362 # Per bank write bursts -system.physmem.perBankWrBursts::13 68403 # Per bank write bursts -system.physmem.perBankWrBursts::14 65406 # Per bank write bursts -system.physmem.perBankWrBursts::15 64772 # Per bank write bursts +system.physmem.bw_write::total 1311109 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1310708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3846 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1406708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2844582 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1245895 # Number of read requests accepted +system.physmem.writeReqs 1053833 # Number of write requests accepted +system.physmem.readBursts 1245895 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1053833 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 79684928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 52352 # Total number of bytes read from write queue +system.physmem.bytesWritten 67299776 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 78715496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67301220 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 818 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74822 # Per bank write bursts +system.physmem.perBankRdBursts::1 82180 # Per bank write bursts +system.physmem.perBankRdBursts::2 80987 # Per bank write bursts +system.physmem.perBankRdBursts::3 75462 # Per bank write bursts +system.physmem.perBankRdBursts::4 75477 # Per bank write bursts +system.physmem.perBankRdBursts::5 80130 # Per bank write bursts +system.physmem.perBankRdBursts::6 74577 # Per bank write bursts +system.physmem.perBankRdBursts::7 72890 # Per bank write bursts +system.physmem.perBankRdBursts::8 72311 # Per bank write bursts +system.physmem.perBankRdBursts::9 102827 # Per bank write bursts +system.physmem.perBankRdBursts::10 78128 # Per bank write bursts +system.physmem.perBankRdBursts::11 79408 # Per bank write bursts +system.physmem.perBankRdBursts::12 72963 # Per bank write bursts +system.physmem.perBankRdBursts::13 76387 # Per bank write bursts +system.physmem.perBankRdBursts::14 73944 # Per bank write bursts +system.physmem.perBankRdBursts::15 72584 # Per bank write bursts +system.physmem.perBankWrBursts::0 62047 # Per bank write bursts +system.physmem.perBankWrBursts::1 68427 # Per bank write bursts +system.physmem.perBankWrBursts::2 68519 # Per bank write bursts +system.physmem.perBankWrBursts::3 66050 # Per bank write bursts +system.physmem.perBankWrBursts::4 65357 # Per bank write bursts +system.physmem.perBankWrBursts::5 67435 # Per bank write bursts +system.physmem.perBankWrBursts::6 63960 # Per bank write bursts +system.physmem.perBankWrBursts::7 63937 # Per bank write bursts +system.physmem.perBankWrBursts::8 63039 # Per bank write bursts +system.physmem.perBankWrBursts::9 70105 # Per bank write bursts +system.physmem.perBankWrBursts::10 66227 # Per bank write bursts +system.physmem.perBankWrBursts::11 68082 # Per bank write bursts +system.physmem.perBankWrBursts::12 64306 # Per bank write bursts +system.physmem.perBankWrBursts::13 66291 # Per bank write bursts +system.physmem.perBankWrBursts::14 64522 # Per bank write bursts +system.physmem.perBankWrBursts::15 63255 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 27 # Number of times write queue was full causing retry -system.physmem.totGap 51291804197000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 51331523357500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1257816 # Read request sizes (log2) +system.physmem.readPktSize::6 1224610 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1078603 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 653601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 337199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 152943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 128864 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 728 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1051260 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 635913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 326498 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 150136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 126962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 762 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 332 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 367 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 170 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 71 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,162 +159,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 32136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 45674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 66802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 68184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 67712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 73018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 67891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 82006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 85825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 63013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 496985 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.554208 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.944807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.108749 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 196641 39.57% 39.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 117090 23.56% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 47261 9.51% 72.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24196 4.87% 77.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18882 3.80% 81.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11863 2.39% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10943 2.20% 85.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8246 1.66% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61863 12.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 496985 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.773365 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 265.981989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 61532 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 11720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 15352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 33279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 44422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 54389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 63406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 64510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 63581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 65005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 68339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 65443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 86913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 69586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 477001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.142583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 177.284446 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.100691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 186993 39.20% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 111432 23.36% 62.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45372 9.51% 72.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23464 4.92% 76.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18197 3.81% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11652 2.44% 83.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10522 2.21% 85.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8218 1.72% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 61151 12.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 477001 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59594 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.891952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 270.280066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 59591 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.533241 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.977663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.054277 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 58637 95.29% 95.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 877 1.43% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 68 0.11% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 330 0.54% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 47 0.08% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 368 0.60% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 228 0.37% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 20 0.03% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 53 0.09% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 138 0.22% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 26 0.04% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 33 0.05% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 471 0.77% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 36 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 24 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 129 0.21% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61535 # Writes before turning the bus around for reads -system.physmem.totQLat 32791506957 # Total ticks spent queuing -system.physmem.totMemAccLat 56759856957 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6391560000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25652.19 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59594 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59594 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.645384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.994879 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.954134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56960 95.58% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 905 1.52% 97.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 37 0.06% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 115 0.19% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 18 0.03% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 110 0.18% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 195 0.33% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.04% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 355 0.60% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 71 0.12% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.04% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 56 0.09% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 280 0.47% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 26 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 33 0.06% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 125 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 203 0.34% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 8 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59594 # Writes before turning the bus around for reads +system.physmem.totQLat 31834686171 # Total ticks spent queuing +system.physmem.totMemAccLat 55179879921 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6225385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25568.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44402.19 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44318.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing -system.physmem.readRowHits 1048127 # Number of row buffer hits during reads -system.physmem.writeRowHits 812106 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.27 # Row buffer hit rate for writes -system.physmem.avgGap 21731264.68 # Average gap between requests -system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1887739560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1030016625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4918711200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3492687600 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3350131371600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1239587078895 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29687726109750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34288773715230 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.503935 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49388003607661 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712746100000 # Time in different power states +system.physmem.avgWrQLen 26.63 # Average write queue length when enqueuing +system.physmem.readRowHits 1023243 # Number of row buffer hits during reads +system.physmem.writeRowHits 796390 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes +system.physmem.avgGap 22320693.30 # Average gap between requests +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1817907840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 991914000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4808848200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3406743360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1236862065645 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29713947077250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34314560092455 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.489031 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49431665045810 # Time in different power states +system.physmem_0.memoryStateTime::REF 1714072360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 191055633589 # Time in different power states +system.physmem_0.memoryStateTime::ACT 185786732190 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1869467040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1020046500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5052099000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3498636240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3350131371600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1240740741510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29686714133250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34289026495140 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.508863 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49386297692325 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712746100000 # Time in different power states +system.physmem_1.actEnergy 1788219720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 975715125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4902705600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3407358960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1238749464465 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29712291456000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34314840456030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.494493 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49428877758086 # Time in different power states +system.physmem_1.memoryStateTime::REF 1714072360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192761562675 # Time in different power states +system.physmem_1.memoryStateTime::ACT 188572884414 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -338,15 +344,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 224688792 # Number of BP lookups -system.cpu.branchPred.condPredicted 150206770 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12191755 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158635537 # Number of BTB lookups -system.cpu.branchPred.BTBHits 103690237 # Number of BTB hits +system.cpu.branchPred.lookups 223870317 # Number of BP lookups +system.cpu.branchPred.condPredicted 149571742 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12183866 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157933845 # Number of BTB lookups +system.cpu.branchPred.BTBHits 103250874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.363814 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 30864801 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 343432 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.376028 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 30780710 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 342883 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,85 +383,85 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 949667 # Table walker walks requested -system.cpu.dtb.walker.walksLong 949667 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16250 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155668 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 435817 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 513850 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 2276.559307 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 14912.808509 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-65535 510335 99.32% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-131071 1958 0.38% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-196607 1047 0.20% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-262143 218 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-327679 154 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-458751 51 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::458752-524287 54 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 937088 # Table walker walks requested +system.cpu.dtb.walker.walksLong 937088 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15029 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154587 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 427394 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 509694 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 2223.932399 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 14616.246492 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-65535 506310 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-131071 1920 0.38% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-196607 988 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-262143 199 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-327679 148 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-458751 46 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 513850 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 485169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23149.084134 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18057.598080 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 21275.722761 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 473369 97.57% 97.57% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 7953 1.64% 99.21% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 2827 0.58% 99.79% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 192 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 567 0.12% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 106 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 98 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 485169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 791579212632 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.715441 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.525649 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 789339278132 99.72% 99.72% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 1195712000 0.15% 99.87% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 474046500 0.06% 99.93% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 207567500 0.03% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 154449500 0.02% 99.97% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 121794500 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 29070000 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 54831500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2463000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 791579212632 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 155669 90.55% 90.55% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16250 9.45% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 171919 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 949667 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 509694 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 474748 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23018.407660 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 18045.301329 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 20477.097679 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 463839 97.70% 97.70% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 7714 1.62% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 2286 0.48% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 175 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 504 0.11% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 86 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 94 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 30 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 474748 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 784053971876 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.725342 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.519550 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 781854829876 99.72% 99.72% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1175747000 0.15% 99.87% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 476309500 0.06% 99.93% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 200437500 0.03% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 146602500 0.02% 99.97% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 120332500 0.02% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 25999000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 51086000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2628000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 784053971876 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 154588 91.14% 91.14% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15029 8.86% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 169617 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 937088 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 949667 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 171919 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 937088 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169617 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 171919 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1121586 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169617 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1106705 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 169633674 # DTB read hits -system.cpu.dtb.read_misses 671728 # DTB read misses -system.cpu.dtb.write_hits 147819857 # DTB write hits -system.cpu.dtb.write_misses 277939 # DTB write misses +system.cpu.dtb.read_hits 169133397 # DTB read hits +system.cpu.dtb.read_misses 670096 # DTB read misses +system.cpu.dtb.write_hits 147221017 # DTB write hits +system.cpu.dtb.write_misses 266992 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 39573 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1021 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 72392 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 97 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9958 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39151 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 71818 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 99 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 9972 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 70151 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 170305402 # DTB read accesses -system.cpu.dtb.write_accesses 148097796 # DTB write accesses +system.cpu.dtb.perms_faults 69741 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 169803493 # DTB read accesses +system.cpu.dtb.write_accesses 147488009 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 317453531 # DTB hits -system.cpu.dtb.misses 949667 # DTB misses -system.cpu.dtb.accesses 318403198 # DTB accesses +system.cpu.dtb.hits 316354414 # DTB hits +system.cpu.dtb.misses 937088 # DTB misses +system.cpu.dtb.accesses 317291502 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -485,885 +491,884 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 160444 # Table walker walks requested -system.cpu.itb.walker.walksLong 160444 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1424 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 120836 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17536 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 142908 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 1360.753072 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 10149.850878 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 141808 99.23% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 585 0.41% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 64 0.04% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 103 0.07% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 274 0.19% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::163840-196607 31 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 17 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 160983 # Table walker walks requested +system.cpu.itb.walker.walksLong 160983 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1438 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 121478 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17520 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 143463 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1273.722144 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 9463.659088 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 142472 99.31% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 574 0.40% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 44 0.03% 99.74% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 82 0.06% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 231 0.16% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 142908 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 139796 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 29385.243498 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24234.240486 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 24521.703817 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 136348 97.53% 97.53% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 877 0.63% 98.16% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 2201 1.57% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 135 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 151 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 29 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 40 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 139796 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 671317017344 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.945059 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.228245 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 36939918060 5.50% 5.50% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 634320646784 94.49% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 55500500 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 942000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 671317017344 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 120836 98.84% 98.84% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1424 1.16% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 122260 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 143463 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 140436 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 29061.341109 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24320.215707 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 22395.663440 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 137485 97.90% 97.90% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 845 0.60% 98.50% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1830 1.30% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 92 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 113 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 140436 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 672381692680 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.944059 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.230149 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 37665306856 5.60% 5.60% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 634665708824 94.39% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 49644500 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 1013500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 19000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 672381692680 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 121478 98.83% 98.83% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1438 1.17% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 122916 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160444 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 160444 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160983 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 160983 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122260 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 122260 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 282704 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 357283873 # ITB inst hits -system.cpu.itb.inst_misses 160444 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 283899 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 355891670 # ITB inst hits +system.cpu.itb.inst_misses 160983 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 39573 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1021 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53225 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39151 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 52900 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 370647 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 368990 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 357444317 # ITB inst accesses -system.cpu.itb.hits 357283873 # DTB hits -system.cpu.itb.misses 160444 # DTB misses -system.cpu.itb.accesses 357444317 # DTB accesses -system.cpu.numCycles 1651928956 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 356052653 # ITB inst accesses +system.cpu.itb.hits 355891670 # DTB hits +system.cpu.itb.misses 160983 # DTB misses +system.cpu.itb.accesses 356052653 # DTB accesses +system.cpu.numCycles 1641618102 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 644904840 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1002675339 # Number of instructions fetch has processed -system.cpu.fetch.Branches 224688792 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 134555038 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 920067624 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26040080 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3808104 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29772 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9331769 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1037128 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 356896495 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6093203 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 48590 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1592200226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.737909 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.145097 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 643295277 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 998912988 # Number of instructions fetch has processed +system.cpu.fetch.Branches 223870317 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 134031584 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 911548920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26021190 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3814569 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 28072 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9294541 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1045994 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 928 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 355505947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6091455 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48555 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1582038896 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.739816 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.145969 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 1034156168 64.95% 64.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 214254104 13.46% 78.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70725246 4.44% 82.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 273064708 17.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 1026150412 64.86% 64.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 213368743 13.49% 78.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 70509493 4.46% 82.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 272010248 17.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1592200226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.136016 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606972 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 524217376 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 575207225 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 433339906 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 50215792 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9219927 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33654884 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3860028 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1086626232 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 28988785 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9219927 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 568973528 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 70181306 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 374019312 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 438766207 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 131039946 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1066849636 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6780403 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 5130065 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 345924 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 553258 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 79683463 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 20375 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1014727198 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1644037540 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1261867774 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1469696 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 949117253 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65609942 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27037743 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23369810 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 103057716 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 173655780 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 151390357 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9897841 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9017927 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1031708315 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27333559 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1047312719 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3286243 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 60487130 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33695071 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315067 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1592200226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.657777 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.917314 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1582038896 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.136372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.608493 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 523526038 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 567332242 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 432225078 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 49743606 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9211932 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33585206 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3858658 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1082487330 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28953315 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9211932 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 568013928 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 68659821 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 370106883 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 437449183 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 128597149 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1062778939 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6765759 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5100330 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 330196 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 669001 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 77613497 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20248 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1010589647 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1636490834 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1256895335 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1474103 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 945145868 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65443776 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26770566 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23114475 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 102068123 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173157157 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 150776419 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9868164 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9014634 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1027918827 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27065451 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1043272281 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3272960 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 60330213 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33600804 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 313388 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1582038896 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.659448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.917899 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 943790813 59.28% 59.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 334741898 21.02% 80.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 234957148 14.76% 95.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72204170 4.53% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6486970 0.41% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19227 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 936232713 59.18% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 333194737 21.06% 80.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 234236353 14.81% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 71914703 4.55% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6441221 0.41% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1592200226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1582038896 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 57844214 35.03% 35.03% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 99575 0.06% 35.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26721 0.02% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 685 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44353632 26.86% 61.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62797684 38.03% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 57633129 35.05% 35.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 100179 0.06% 35.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26746 0.02% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 783 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44218992 26.89% 62.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62461837 37.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 721297441 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2539668 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 122649 0.01% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 121234 0.01% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 173513888 16.57% 85.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 149717789 14.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 718385578 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2533352 0.24% 69.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 122770 0.01% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 382 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 121248 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 173007895 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 149100989 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1047312719 # Type of FU issued -system.cpu.iq.rate 0.633994 # Inst issue rate -system.cpu.iq.fu_busy_cnt 165122511 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157663 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3852756863 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1118723028 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1029355100 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2477554 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 946947 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 909717 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1210878214 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1557015 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4319350 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1043272281 # Type of FU issued +system.cpu.iq.rate 0.635515 # Inst issue rate +system.cpu.iq.fu_busy_cnt 164441666 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157621 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3833820592 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1114508942 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1025374913 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2477491 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 947894 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909947 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1206157308 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1556618 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4301219 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13798077 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14626 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 142237 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6323389 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13765356 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14482 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6293913 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2533948 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1563961 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2526650 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1543650 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9219927 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 7084785 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9314562 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1059264038 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9211932 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6884950 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9078435 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1055205514 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 173655780 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 151390357 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22943670 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 58438 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 9182367 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 142237 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3657929 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5098518 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8756447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1036137894 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 169621625 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10236296 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 173157157 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 150776419 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 22691259 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 56491 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8949926 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3653003 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5096400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8749403 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1032130630 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 169121119 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10215406 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 222164 # number of nop insts executed -system.cpu.iew.exec_refs 317437095 # number of memory reference insts executed -system.cpu.iew.exec_branches 196547238 # Number of branches executed -system.cpu.iew.exec_stores 147815470 # Number of stores executed -system.cpu.iew.exec_rate 0.627229 # Inst execution rate -system.cpu.iew.wb_sent 1031075002 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1030264817 # cumulative count of insts written-back -system.cpu.iew.wb_producers 438532269 # num instructions producing a value -system.cpu.iew.wb_consumers 709380763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.623674 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618190 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 51390718 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27018492 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8391642 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1580228062 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.631905 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.268654 # Number of insts commited each cycle +system.cpu.iew.exec_nop 221236 # number of nop insts executed +system.cpu.iew.exec_refs 316337352 # number of memory reference insts executed +system.cpu.iew.exec_branches 195829859 # Number of branches executed +system.cpu.iew.exec_stores 147216233 # Number of stores executed +system.cpu.iew.exec_rate 0.628728 # Inst execution rate +system.cpu.iew.wb_sent 1027090277 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1026284860 # cumulative count of insts written-back +system.cpu.iew.wb_producers 436833707 # num instructions producing a value +system.cpu.iew.wb_consumers 706462159 # num instructions consuming a value +system.cpu.iew.wb_rate 0.625167 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618340 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 51246502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 26752063 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8385203 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1570087734 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.633502 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.269814 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 1067496193 67.55% 67.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 288499411 18.26% 85.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 120593665 7.63% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36542296 2.31% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28489830 1.80% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14035785 0.89% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8641720 0.55% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4180750 0.26% 99.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11748412 0.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1059518127 67.48% 67.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 287046411 18.28% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 120236472 7.66% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36451838 2.32% 95.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28385212 1.81% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 13987217 0.89% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8615612 0.55% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4166173 0.27% 99.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11680672 0.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1580228062 # Number of insts commited each cycle -system.cpu.commit.committedInsts 849784302 # Number of instructions committed -system.cpu.commit.committedOps 998554740 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1570087734 # Number of insts commited each cycle +system.cpu.commit.committedInsts 846524467 # Number of instructions committed +system.cpu.commit.committedOps 994654061 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 304924670 # Number of memory references committed -system.cpu.commit.loads 159857702 # Number of loads committed -system.cpu.commit.membars 6942890 # Number of memory barriers committed -system.cpu.commit.branches 189641559 # Number of branches committed -system.cpu.commit.fp_insts 896155 # Number of committed floating point instructions. -system.cpu.commit.int_insts 917432780 # Number of committed integer instructions. -system.cpu.commit.function_calls 25317062 # Number of function calls committed. +system.cpu.commit.refs 303874306 # Number of memory references committed +system.cpu.commit.loads 159391800 # Number of loads committed +system.cpu.commit.membars 6909679 # Number of memory barriers committed +system.cpu.commit.branches 188935778 # Number of branches committed +system.cpu.commit.fp_insts 896706 # Number of committed floating point instructions. +system.cpu.commit.int_insts 913907111 # Number of committed integer instructions. +system.cpu.commit.function_calls 25250179 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 691266097 69.23% 69.23% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2154064 0.22% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98002 0.01% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111865 0.01% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 159857702 16.01% 85.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 145066968 14.53% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 688421836 69.21% 69.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2147861 0.22% 69.43% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98019 0.01% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 159391800 16.02% 85.47% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 144482506 14.53% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 998554740 # Class of committed instruction -system.cpu.commit.bw_lim_events 11748412 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2610868733 # The number of ROB reads -system.cpu.rob.rob_writes 2111769063 # The number of ROB writes -system.cpu.timesIdled 8146861 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 59728730 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 100931682357 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 849784302 # Number of Instructions Simulated -system.cpu.committedOps 998554740 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.943939 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.943939 # CPI: Total CPI of All Threads -system.cpu.ipc 0.514419 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.514419 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1226658290 # number of integer regfile reads -system.cpu.int_regfile_writes 732482403 # number of integer regfile writes -system.cpu.fp_regfile_reads 1461367 # number of floating regfile reads -system.cpu.fp_regfile_writes 784012 # number of floating regfile writes -system.cpu.cc_regfile_reads 225710355 # number of cc regfile reads -system.cpu.cc_regfile_writes 226370154 # number of cc regfile writes -system.cpu.misc_regfile_reads 2581410543 # number of misc regfile reads -system.cpu.misc_regfile_writes 27063260 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9708370 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.972782 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 283529628 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9708882 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.203118 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 994654061 # Class of committed instruction +system.cpu.commit.bw_lim_events 11680672 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2596784081 # The number of ROB reads +system.cpu.rob.rob_writes 2103659595 # The number of ROB writes +system.cpu.timesIdled 8144337 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 59579206 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101021431570 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 846524467 # Number of Instructions Simulated +system.cpu.committedOps 994654061 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.939245 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.939245 # CPI: Total CPI of All Threads +system.cpu.ipc 0.515665 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.515665 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1221742987 # number of integer regfile reads +system.cpu.int_regfile_writes 729786392 # number of integer regfile writes +system.cpu.fp_regfile_reads 1462559 # number of floating regfile reads +system.cpu.fp_regfile_writes 782552 # number of floating regfile writes +system.cpu.cc_regfile_reads 224594796 # number of cc regfile reads +system.cpu.cc_regfile_writes 225242859 # number of cc regfile writes +system.cpu.misc_regfile_reads 2567204891 # number of misc regfile reads +system.cpu.misc_regfile_writes 26785378 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9653571 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.972798 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 282643774 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9654083 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.277123 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.972782 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.972798 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1238524544 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1238524544 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 147275132 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147275132 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128498890 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128498890 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 378449 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 378449 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 323156 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 323156 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3306743 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3306743 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3702780 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3702780 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 275774022 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 275774022 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 276152471 # number of overall hits -system.cpu.dcache.overall_hits::total 276152471 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9562571 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9562571 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11295910 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11295910 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1177323 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1177323 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1234379 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1234379 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 448575 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 448575 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1234280358 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1234280358 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146896386 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146896386 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128038519 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128038519 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 377527 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 377527 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 324244 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 324244 # number of WriteLineReq hits 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(read+write) accesses +system.cpu.dcache.demand_accesses::total 295651892 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 297191453 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 297191453 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060861 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060861 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080420 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080420 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754783 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.754783 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791573 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.791573 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119568 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119568 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070318 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070318 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073899 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17676.442089 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17676.442089 # average ReadReq miss latency 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cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163635250674 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 163635250674 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187428141674 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 187428141674 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191802000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191802000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228377464 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228377464 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84024978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 84024978000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76144562086 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 76144562086 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22952152500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22952152500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 87564866876 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87564866876 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3184481000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3184481000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 267500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 267500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160169540086 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160169540086 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183121692586 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 183121692586 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191871000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191871000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228308464 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228308464 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420179464 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420179464 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032618 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014379 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014379 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.752369 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.752369 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787912 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787912 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.061032 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.061032 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032564 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014341 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.750363 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.750363 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787071 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787071 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060925 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024022 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024022 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027822 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027822 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16646.358856 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16646.358856 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39040.769996 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39040.769996 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 20326.874348 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 20326.874348 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 72046.497715 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 72046.497715 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14114.186610 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14114.186610 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54100 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54100 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22963.714576 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22963.714576 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22591.687709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22591.687709 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183853.019776 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183853.019776 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184840.261871 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184840.261871 # average WriteReq mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023982 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023982 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027745 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027745 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16496.552951 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16496.552951 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38132.587730 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38132.587730 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19868.054299 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19868.054299 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71514.975475 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71514.975475 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14011.822890 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14011.822890 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 53500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 53500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22589.876018 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22589.876018 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22208.539874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22208.539874 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183855.068591 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183855.068591 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184838.214150 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184838.214150 # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702 # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15025014 # number of replacements -system.cpu.icache.tags.tagsinuse 511.916800 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 341084146 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15025526 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.700313 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 15015869 # number of replacements +system.cpu.icache.tags.tagsinuse 511.916858 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 339700335 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15016381 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.621984 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 24730722500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.916800 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999837 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999837 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 511.916858 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999838 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999838 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 371900940 # Number of tag accesses -system.cpu.icache.tags.data_accesses 371900940 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 341084146 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 341084146 # number of ReadReq hits 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cycles -system.cpu.icache.demand_miss_latency::cpu.inst 213656099879 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 213656099879 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 213656099879 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 213656099879 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 356875197 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 356875197 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 356875197 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 356875197 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 356875197 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 356875197 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044248 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.044248 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.044248 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.044248 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.044248 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.044248 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13530.201370 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13530.201370 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13530.201370 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13530.201370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13530.201370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13530.201370 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 23378 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 370501257 # Number of tag accesses +system.cpu.icache.tags.data_accesses 370501257 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 339700335 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 339700335 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 339700335 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 339700335 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 339700335 # number of overall hits +system.cpu.icache.overall_hits::total 339700335 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15784316 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15784316 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15784316 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15784316 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15784316 # number of overall misses +system.cpu.icache.overall_misses::total 15784316 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 213513378383 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 213513378383 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 213513378383 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 213513378383 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 213513378383 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 213513378383 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 355484651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 355484651 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 355484651 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 355484651 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 355484651 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 355484651 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044402 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044402 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044402 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044402 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044402 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044402 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13526.932582 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13526.932582 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13526.932582 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13526.932582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13526.932582 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13526.932582 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 23493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1447 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1429 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.156185 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 16.440168 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 15025014 # number of writebacks -system.cpu.icache.writebacks::total 15025014 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 765308 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 765308 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 765308 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 765308 # number of demand (read+write) MSHR hits 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+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038376 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038376 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.403563 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.403563 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029564 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029564 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127863.347785 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.600757 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.600757 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128655.026050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128655.026050 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124605.160034 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124605.160034 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128886.233897 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128886.233897 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145023.125375 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145023.125375 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171347.229645 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148973.932184 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173206.033357 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173206.033357 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171350.302868 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148975.814960 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173203.881766 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173203.881766 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172276.879805 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158182.720937 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.339923 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.070555 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 50209605 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 25474994 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2120 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2120 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 50072876 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 25402191 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3486 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2165 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2165 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1623677 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23162262 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1616472 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23106705 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8599615 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15022476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2383518 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8523542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 15015869 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2370764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43153 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1969613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1969613 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15025743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6520923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1333865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1227201 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45116347 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29348618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 723959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1930896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 77119820 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1923413728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1024410462 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2386824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6302376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2956513390 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1874549 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 27826881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.025283 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.156985 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 43158 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1956829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1956829 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 15016606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6481683 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1331091 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1224427 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45091458 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29183621 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917139 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 76921811 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922405600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017963166 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2418728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6263128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2949050622 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1833494 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 27720270 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.025088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.156393 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 27123321 97.47% 97.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 703560 2.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 27024822 97.49% 97.49% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 695448 2.51% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 27826881 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 48147469995 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 27720270 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 48021701496 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1446401 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1471889 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22568730706 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22555136481 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13411529968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13331758520 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 425937320 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 427610263 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1143472216 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1134604242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40293 # Transaction distribution -system.iobus.trans_dist::ReadResp 40293 # Transaction distribution +system.iobus.trans_dist::ReadReq 40281 # Transaction distribution +system.iobus.trans_dist::ReadResp 40281 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1583,11 +1588,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230920 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230920 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353704 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1602,12 +1607,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334112 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492128 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 41872500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 41869500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1629,73 +1634,73 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25139500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25153000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 36500500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36496500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565848565 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567170357 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147704000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147680000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115453 # number of replacements -system.iocache.tags.tagsinuse 10.417914 # Cycle average of tags in use +system.iocache.tags.replacements 115446 # number of replacements +system.iocache.tags.tagsinuse 10.422236 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115469 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13103145499000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.546638 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.871276 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221665 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429455 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651120 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13103145496000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.903254 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.518982 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.368953 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.282436 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039605 # Number of tag accesses -system.iocache.tags.data_accesses 1039605 # Number of data accesses +system.iocache.tags.tag_accesses 1039497 # Number of tag accesses +system.iocache.tags.data_accesses 1039497 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8808 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8845 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8796 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8833 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8808 # number of demand (read+write) misses -system.iocache.demand_misses::total 8848 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8796 # number of demand (read+write) misses +system.iocache.demand_misses::total 8836 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8808 # number of overall misses -system.iocache.overall_misses::total 8848 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1690818481 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1695888981 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8796 # number of overall misses +system.iocache.overall_misses::total 8836 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1678447047 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1683516547 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13865997584 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13865997584 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1690818481 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1696239981 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1690818481 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1696239981 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13410212810 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13410212810 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1678447047 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1683867547 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1678447047 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1683867547 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8808 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8845 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8796 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8833 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8808 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8796 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8836 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8808 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8796 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8836 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1709,55 +1714,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191963.951067 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 191734.197965 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 190819.355048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 190593.971131 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129996.977274 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129996.977274 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191963.951067 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 191708.858612 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191963.951067 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 191708.858612 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36185 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125723.888191 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125723.888191 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 190568.984495 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 190568.984495 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34452 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3641 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.938204 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.991879 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8808 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8845 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8796 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8833 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8808 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8848 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8796 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8836 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8808 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8848 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1250418481 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1253638981 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8796 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8836 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1238647047 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1241866547 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8532797584 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8532797584 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1250418481 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1253839981 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1250418481 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1253839981 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071956842 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8071956842 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1238647047 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1242067547 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1238647047 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1242067547 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1771,73 +1776,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141963.951067 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 141734.197965 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140819.355048 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 140593.971131 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79996.977274 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79996.977274 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141963.951067 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 141708.858612 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141963.951067 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 141708.858612 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75676.487306 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75676.487306 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 54972 # Transaction distribution -system.membus.trans_dist::ReadResp 414632 # Transaction distribution +system.membus.trans_dist::ReadResp 402203 # Transaction distribution system.membus.trans_dist::WriteReq 33696 # Transaction distribution system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1078603 # Transaction distribution -system.membus.trans_dist::CleanEvict 193680 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35229 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1051260 # Transaction distribution +system.membus.trans_dist::CleanEvict 188377 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34626 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35232 # Transaction distribution -system.membus.trans_dist::ReadExReq 900805 # Transaction distribution -system.membus.trans_dist::ReadExResp 900805 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 359660 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 880179 # Transaction distribution +system.membus.trans_dist::ReadExResp 880179 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 347231 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3779727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3909347 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342337 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342337 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4251684 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3643028 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3772648 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237638 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4010286 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 142628812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 142798782 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7263040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 150061822 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2657 # Total snoops (count) -system.membus.snoop_fanout::samples 2765486 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138764108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138934078 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7252608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 146186686 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2808 # Total snoops (count) +system.membus.snoop_fanout::samples 2697046 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2765486 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2697046 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2765486 # Request fanout histogram -system.membus.reqLayer0.occupancy 103948000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2697046 # Request fanout histogram +system.membus.reqLayer0.occupancy 103954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5458000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5466500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7323908114 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7139670905 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6816104590 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6571001988 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227615986 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44720417 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1892,6 +1896,6 @@ system.realview.mcc.osc_mcc.clock 20000 # Cl system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16126 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16102 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt index df4777d2f..ea1074d2e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-checkpoint/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111153 # Number of seconds simulated -sim_ticks 51111152682000 # Number of ticks simulated -final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111167 # Number of seconds simulated +sim_ticks 51111167216500 # Number of ticks simulated +final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 966487 # Simulator instruction rate (inst/s) -host_op_rate 1135781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50172400532 # Simulator tick rate (ticks/s) -host_mem_usage 679768 # Number of bytes of host memory used -host_seconds 1018.71 # Real time elapsed on the host -sim_insts 984570519 # Number of instructions simulated -sim_ops 1157031967 # Number of ops (including micro ops) simulated +host_inst_rate 1100410 # Simulator instruction rate (inst/s) +host_op_rate 1293220 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57262321562 # Simulator tick rate (ticks/s) +host_mem_usage 678496 # Number of bytes of host memory used +host_seconds 892.58 # Real time elapsed on the host +sim_insts 982203438 # Number of instructions simulated +sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110253960 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 116962748 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1722731 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1867963 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2157140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2288399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2157543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4309446 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -103,45 +103,45 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 265715 # Table walker walks requested -system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 266586 # Table walker walks requested +system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184014035 # DTB read hits -system.cpu.dtb.read_misses 194198 # DTB read misses -system.cpu.dtb.write_hits 168232768 # DTB write hits -system.cpu.dtb.write_misses 71517 # DTB write misses +system.cpu.dtb.read_hits 183545125 # DTB read hits +system.cpu.dtb.read_misses 195347 # DTB read misses +system.cpu.dtb.write_hits 167774776 # DTB write hits +system.cpu.dtb.write_misses 71239 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184208233 # DTB read accesses -system.cpu.dtb.write_accesses 168304285 # DTB write accesses +system.cpu.dtb.read_accesses 183740472 # DTB read accesses +system.cpu.dtb.write_accesses 167846015 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 352246803 # DTB hits -system.cpu.dtb.misses 265715 # DTB misses -system.cpu.dtb.accesses 352512518 # DTB accesses +system.cpu.dtb.hits 351319901 # DTB hits +system.cpu.dtb.misses 266586 # DTB misses +system.cpu.dtb.accesses 351586487 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,26 +171,26 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 126837 # Table walker walks requested -system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 126834 # Table walker walks requested +system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 985047321 # ITB inst hits -system.cpu.itb.inst_misses 126837 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 982680284 # ITB inst hits +system.cpu.itb.inst_misses 126834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -199,159 +199,159 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 985174158 # ITB inst accesses -system.cpu.itb.hits 985047321 # DTB hits -system.cpu.itb.misses 126837 # DTB misses -system.cpu.itb.accesses 985174158 # DTB accesses -system.cpu.numCycles 102222322140 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 982807118 # ITB inst accesses +system.cpu.itb.hits 982680284 # DTB hits +system.cpu.itb.misses 126834 # DTB misses +system.cpu.itb.accesses 982807118 # DTB accesses +system.cpu.numCycles 102222351209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 984570519 # Number of instructions committed -system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses -system.cpu.num_func_calls 57056367 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls -system.cpu.num_int_insts 1060455466 # number of integer instructions -system.cpu.num_fp_insts 880805 # number of float instructions -system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read -system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read -system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written -system.cpu.num_mem_refs 352465606 # number of memory refs -system.cpu.num_load_insts 184180431 # Number of load instructions -system.cpu.num_store_insts 168285175 # Number of store instructions -system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles -system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles -system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988675 # Percentage of idle cycles -system.cpu.Branches 220088562 # Number of branches fetched +system.cpu.committedInsts 982203438 # Number of instructions committed +system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses +system.cpu.num_func_calls 56834581 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls +system.cpu.num_int_insts 1057882257 # number of integer instructions +system.cpu.num_fp_insts 881349 # number of float instructions +system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read +system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read +system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written +system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written +system.cpu.num_mem_refs 351539335 # number of memory refs +system.cpu.num_load_insts 183712430 # Number of load instructions +system.cpu.num_store_insts 167826905 # Number of store instructions +system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles +system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles +system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.988702 # Percentage of idle cycles +system.cpu.Branches 219534054 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction -system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction -system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction +system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1157666593 # Class of executed instruction -system.cpu.dcache.tags.replacements 11612141 # number of replacements +system.cpu.op_class::total 1154935820 # Class of executed instruction +system.cpu.dcache.tags.replacements 11606642 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 337709 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits -system.cpu.dcache.overall_hits::total 331514149 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1245349 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits +system.cpu.dcache.overall_hits::total 330608768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses -system.cpu.dcache.overall_misses::total 10164734 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583058 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786673 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses +system.cpu.dcache.overall_misses::total 10157717 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,49 +360,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks -system.cpu.dcache.writebacks::total 8921277 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks +system.cpu.dcache.writebacks::total 8917390 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 14295641 # number of replacements +system.cpu.icache.tags.replacements 14265253 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses -system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits -system.cpu.icache.overall_hits::total 970865862 # number of overall hits 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-system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses +system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits 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-system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022508 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015917 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,55 +557,55 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks -system.cpu.l2cache.writebacks::total 1503967 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks +system.cpu.l2cache.writebacks::total 1507080 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1954989 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1957577 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40246 # Transaction distribution -system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40242 # Transaction distribution +system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -622,11 +622,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -641,53 +641,53 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115463 # number of replacements -system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use +system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039686 # Number of tag accesses -system.iocache.tags.data_accesses 1039686 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses -system.iocache.demand_misses::total 8857 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8817 # number of overall misses -system.iocache.overall_misses::total 8857 # number of overall misses +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -713,47 +713,47 @@ system.iocache.writebacks::writebacks 106631 # nu system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 525254 # Transaction distribution +system.membus.trans_dist::ReadResp 524946 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution -system.membus.trans_dist::CleanEvict 224691 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution +system.membus.trans_dist::CleanEvict 226320 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution +system.membus.trans_dist::ReadExReq 1379258 # Transaction distribution +system.membus.trans_dist::ReadExResp 1379258 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213041440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213210490 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220601274 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3920464 # Request fanout histogram +system.membus.snoop_fanout::samples 3924997 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3920464 # Request fanout histogram +system.membus.snoop_fanout::total 3924997 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 1a0f4314f..54c2c1887 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.216814 # Number of seconds simulated -sim_ticks 47216814145000 # Number of ticks simulated -final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.256536 # Number of seconds simulated +sim_ticks 47256535705500 # Number of ticks simulated +final_tick 47256535705500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 919960 # Simulator instruction rate (inst/s) -host_op_rate 1082251 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44530469299 # Simulator tick rate (ticks/s) -host_mem_usage 691012 # Number of bytes of host memory used -host_seconds 1060.33 # Real time elapsed on the host -sim_insts 975457230 # Number of instructions simulated -sim_ops 1147538415 # Number of ops (including micro ops) simulated +host_inst_rate 1053178 # Simulator instruction rate (inst/s) +host_op_rate 1239009 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51012949173 # Simulator tick rate (ticks/s) +host_mem_usage 689744 # Number of bytes of host memory used +host_seconds 926.36 # Real time elapsed on the host +sim_insts 975625723 # Number of instructions simulated +sim_ops 1147772483 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 152064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3862964 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 62933832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 221952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 220096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2661000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 46409840 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 419200 # Number of bytes read from this memory -system.physmem.bytes_read::total 117007860 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3862964 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2661000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6523964 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100926976 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 155968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 131392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3922036 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 63542792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 217344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 214144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2638472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 46092656 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 429440 # Number of bytes read from this memory +system.physmem.bytes_read::total 117344244 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3922036 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2638472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 101301760 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 100947560 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 100766 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 983354 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3468 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3439 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 41685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 725170 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6550 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1868791 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1576984 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 101322344 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2437 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2053 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101689 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 992869 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3346 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 720214 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6710 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1874047 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1582840 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1579558 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1332869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 982909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8878 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2478097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 138170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2137522 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1585414 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1344635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4532 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55833 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 975371 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9087 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2483133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82995 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55833 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138828 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2143656 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2137958 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2137522 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1333305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4701 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 982909 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8878 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4616055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2144092 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2143656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1345070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55833 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 975371 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4627224 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -134,45 +134,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 125229 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 124170 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 124170 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 124170 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 124170 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 124170 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 95903 89.91% 89.91% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10758 10.09% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 106661 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 124170 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 124170 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106661 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 230831 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 92662773 # DTB read hits -system.cpu0.dtb.read_misses 88786 # DTB read misses -system.cpu0.dtb.write_hits 85694958 # DTB write hits -system.cpu0.dtb.write_misses 36443 # DTB write misses +system.cpu0.dtb.read_hits 91996645 # DTB read hits +system.cpu0.dtb.read_misses 87944 # DTB read misses +system.cpu0.dtb.write_hits 85085804 # DTB write hits +system.cpu0.dtb.write_misses 36226 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36305 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5760 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92751559 # DTB read accesses -system.cpu0.dtb.write_accesses 85731401 # DTB write accesses +system.cpu0.dtb.perms_faults 10368 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92084589 # DTB read accesses +system.cpu0.dtb.write_accesses 85122030 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 178357731 # DTB hits -system.cpu0.dtb.misses 125229 # DTB misses -system.cpu0.dtb.accesses 178482960 # DTB accesses +system.cpu0.dtb.hits 177082449 # DTB hits +system.cpu0.dtb.misses 124170 # DTB misses +system.cpu0.dtb.accesses 177206619 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,187 +202,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 61377 # Table walker walks requested -system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 60706 # Table walker walks requested +system.cpu0.itb.walker.walksLong 60706 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 60706 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 60706 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 60706 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 54677 98.81% 98.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 656 1.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 55333 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60706 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60706 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 497696393 # ITB inst hits -system.cpu0.itb.inst_misses 61377 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55333 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 116039 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 494456191 # ITB inst hits +system.cpu0.itb.inst_misses 60706 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25125 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses -system.cpu0.itb.hits 497696393 # DTB hits -system.cpu0.itb.misses 61377 # DTB misses -system.cpu0.itb.accesses 497757770 # DTB accesses -system.cpu0.numCycles 94433641544 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 494516897 # ITB inst accesses +system.cpu0.itb.hits 494456191 # DTB hits +system.cpu0.itb.misses 60706 # DTB misses +system.cpu0.itb.accesses 494516897 # DTB accesses +system.cpu0.numCycles 94513084765 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed -system.cpu0.committedInsts 497466384 # Number of instructions committed -system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses -system.cpu0.num_func_calls 28869117 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls -system.cpu0.num_int_insts 536103359 # number of integer instructions -system.cpu0.num_fp_insts 526132 # number of float instructions -system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read -system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written -system.cpu0.num_mem_refs 178459396 # number of memory refs -system.cpu0.num_load_insts 92737001 # Number of load instructions -system.cpu0.num_store_insts 85722395 # Number of store instructions -system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles -system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles -system.cpu0.Branches 111287587 # Number of branches fetched +system.cpu0.kern.inst.quiesce 13353 # number of quiesce instructions executed +system.cpu0.committedInsts 494222683 # Number of instructions committed +system.cpu0.committedOps 581244792 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 532690974 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 523276 # Number of float alu accesses +system.cpu0.num_func_calls 28754621 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 75975087 # number of instructions that are conditional controls +system.cpu0.num_int_insts 532690974 # number of integer instructions +system.cpu0.num_fp_insts 523276 # number of float instructions +system.cpu0.num_int_register_reads 780604880 # number of times the integer registers were read +system.cpu0.num_int_register_writes 422748329 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 843639 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 445096 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132982449 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132652363 # number of times the CC registers were written +system.cpu0.num_mem_refs 177183712 # number of memory refs +system.cpu0.num_load_insts 92070454 # Number of load instructions +system.cpu0.num_store_insts 85113258 # Number of store instructions +system.cpu0.num_idle_cycles 93931503589.334885 # Number of idle cycles +system.cpu0.num_busy_cycles 581581175.665107 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006153 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993847 # Percentage of idle cycles +system.cpu0.Branches 110567658 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction -system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction -system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction -system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 403027649 69.30% 69.30% # Class of executed instruction +system.cpu0.op_class::IntMult 1232673 0.21% 69.51% # Class of executed instruction +system.cpu0.op_class::IntDiv 59610 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 73071 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::MemRead 92070454 15.83% 85.37% # Class of executed instruction +system.cpu0.op_class::MemWrite 85113258 14.63% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 585300003 # Class of executed instruction -system.cpu0.dcache.tags.replacements 6272771 # number of replacements -system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6273283 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.420375 # Average number of references to valid blocks. +system.cpu0.op_class::total 581576758 # Class of executed instruction +system.cpu0.dcache.tags.replacements 6248192 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.818994 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 170762721 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6248704 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.327702 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.818994 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978162 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978162 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 363162248 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 363162248 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86214911 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86214911 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80912298 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80912298 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 262024 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 262024 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036634 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2036634 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 167127209 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 167127209 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 167342863 # number of overall hits -system.cpu0.dcache.overall_hits::total 167342863 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3309382 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3309382 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1483144 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1483144 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 831696 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 831696 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158509 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 158509 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4792526 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4792526 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5564665 # number of overall misses -system.cpu0.dcache.overall_misses::total 5564665 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1093720 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1093720 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018000 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018000 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760429 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072209 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072209 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027877 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027877 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032183 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032183 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 360582168 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 360582168 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85561344 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 85561344 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80310172 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80310172 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214412 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 214412 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259684 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 259684 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2079285 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2079285 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2039916 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2039916 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165871516 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 165871516 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 166085928 # number of overall hits +system.cpu0.dcache.overall_hits::total 166085928 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3292661 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3292661 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1484829 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1484829 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 774558 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 774558 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823198 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 823198 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 118361 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 118361 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156543 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 156543 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4777490 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4777490 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5552048 # number of overall misses +system.cpu0.dcache.overall_misses::total 5552048 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88854005 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 88854005 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81795001 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81795001 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 988970 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 988970 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082882 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1082882 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2197646 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2197646 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2196459 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2196459 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 170649006 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 170649006 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 171637976 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 171637976 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037057 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037057 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018153 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018153 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783197 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783197 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760192 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760192 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053858 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053858 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071271 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071271 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027996 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027996 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032347 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032347 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,50 +391,49 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6272771 # number of writebacks -system.cpu0.dcache.writebacks::total 6272771 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 6248192 # number of writebacks +system.cpu0.dcache.writebacks::total 6248192 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5539081 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5479450 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989014 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 489031557 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5479962 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 89.239954 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989014 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits -system.cpu0.icache.overall_hits::total 492212891 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses -system.cpu0.icache.overall_misses::total 5539598 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 994503015 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 994503015 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 489031557 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 489031557 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 489031557 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 489031557 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 489031557 # number of overall hits +system.cpu0.icache.overall_hits::total 489031557 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5479967 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5479967 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5479967 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5479967 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5479967 # number of overall misses +system.cpu0.icache.overall_misses::total 5479967 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 494511524 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 494511524 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 494511524 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 494511524 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 494511524 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 494511524 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011082 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011082 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011082 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011082 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011082 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011082 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,8 +442,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 5539081 # number of writebacks -system.cpu0.icache.writebacks::total 5539081 # number of writebacks +system.cpu0.icache.writebacks::writebacks 5479450 # number of writebacks +system.cpu0.icache.writebacks::total 5479450 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -452,139 +451,139 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2670833 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16144.496707 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15583793 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2686790 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.800153 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2651661 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16083.621220 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15456673 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2667641 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.794135 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16059.102143 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 41.665572 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 43.728993 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.980170 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002543 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.002669 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985382 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15907 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 15982.700506 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 46.812729 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 54.107985 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.975507 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002857 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003302 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981666 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15898 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 67 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1465 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4378 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5313 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4509 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970886 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 397685392 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 397685392 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 298097 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 159313 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 457410 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 4459579 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 4459579 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7350874 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7350874 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 760 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 760 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 635944 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 635944 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5035825 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 5035825 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2962064 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2962064 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 223971 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 223971 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 298097 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 159313 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5035825 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3598008 # number of demand (read+write) hits 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-system.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5539598 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5539598 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4201337 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 4201337 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 831335 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.InvalidateReq_accesses::total 831335 # number of InvalidateReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 309423 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 167731 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5545567 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11562319 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 309423 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 167731 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5545567 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11562319 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.050188 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.041379 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994543 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994543 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1468 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4776 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4826 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4604 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.970337 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 394866118 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 394866118 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 294519 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 156806 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 451325 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 4431483 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 4431483 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 7294760 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 7294760 # number of WritebackClean hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 771 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 771 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630855 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 630855 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4984424 # number 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misses +system.cpu0.l2cache.demand_misses::total 2465607 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11443 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8713 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 495543 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1949908 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2465607 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 305962 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 165519 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 471481 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4431483 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 4431483 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 7294760 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 7294760 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 141365 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 141365 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156543 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 156543 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1343834 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1343834 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5479967 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 5479967 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4185580 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 4185580 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 822828 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.InvalidateReq_accesses::total 822828 # number of InvalidateReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 305962 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 165519 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5479967 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5529414 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11480862 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 305962 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 165519 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5479967 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5529414 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11480862 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052640 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.042750 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.994546 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.994546 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526908 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.526908 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090940 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090940 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.294971 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.294971 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730589 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730589 # miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.050188 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090940 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.351192 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.213718 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036604 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.050188 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090940 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.351192 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.213718 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.530556 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.530556 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.090428 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.090428 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.295522 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.295522 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.734609 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.734609 # miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052640 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.090428 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.352643 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.214758 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037400 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052640 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.090428 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.352643 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.214758 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,52 +592,52 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1567377 # number of writebacks -system.cpu0.l2cache.writebacks::total 1567377 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1559370 # number of writebacks +system.cpu0.l2cache.writebacks::total 1559370 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 24282502 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12366009 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_requests 24116923 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12284721 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1399 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1791227 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1790958 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 623009 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4459579 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7350874 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 139275 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158509 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 297784 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5539598 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4201337 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 831335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 831335 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16703618 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19751529 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 37549877 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 709149780 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 756535625 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1470064325 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 6119333 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 30615399 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.066982 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.250025 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1786138 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1785867 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 271 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 618755 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10284302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 33226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 33226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 4431483 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7296159 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 141365 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156543 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 297908 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1343834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1343834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5479967 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4185580 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 822828 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 822828 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16525634 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19681122 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 362662 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 722420 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 37291838 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 701575188 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 753965416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1450648 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2889680 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1459880932 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6128014 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 30453385 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067263 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.250512 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 28565001 93.30% 93.30% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2050129 6.70% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 28405278 93.27% 93.27% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2047836 6.72% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 271 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 30615399 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 30453385 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -668,45 +667,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 144041 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 145097 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 145097 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 145097 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 145097 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 145097 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 112288 88.82% 88.82% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 14132 11.18% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 126420 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145097 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145097 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126420 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126420 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 271517 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90153061 # DTB read hits -system.cpu1.dtb.read_misses 111753 # DTB read misses -system.cpu1.dtb.write_hits 81132787 # DTB write hits -system.cpu1.dtb.write_misses 32288 # DTB write misses +system.cpu1.dtb.read_hits 90839106 # DTB read hits +system.cpu1.dtb.read_misses 112437 # DTB read misses +system.cpu1.dtb.write_hits 81787747 # DTB write hits +system.cpu1.dtb.write_misses 32660 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44645 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4653 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 90264814 # DTB read accesses -system.cpu1.dtb.write_accesses 81165075 # DTB write accesses +system.cpu1.dtb.perms_faults 11499 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90951543 # DTB read accesses +system.cpu1.dtb.write_accesses 81820407 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 171285848 # DTB hits -system.cpu1.dtb.misses 144041 # DTB misses -system.cpu1.dtb.accesses 171429889 # DTB accesses +system.cpu1.dtb.hits 172626853 # DTB hits +system.cpu1.dtb.misses 145097 # DTB misses +system.cpu1.dtb.accesses 172771950 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -736,187 +735,186 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 60885 # Table walker walks requested -system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 61573 # Table walker walks requested +system.cpu1.itb.walker.walksLong 61573 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 61573 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 61573 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 61573 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 54551 99.05% 99.05% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 525 0.95% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55076 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61573 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61573 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 478248118 # ITB inst hits -system.cpu1.itb.inst_misses 60885 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55076 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55076 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 116649 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 481656543 # ITB inst hits +system.cpu1.itb.inst_misses 61573 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49413 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31343 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses -system.cpu1.itb.hits 478248118 # DTB hits -system.cpu1.itb.misses 60885 # DTB misses -system.cpu1.itb.accesses 478309003 # DTB accesses -system.cpu1.numCycles 94433634550 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 481718116 # ITB inst accesses +system.cpu1.itb.hits 481656543 # DTB hits +system.cpu1.itb.misses 61573 # DTB misses +system.cpu1.itb.accesses 481718116 # DTB accesses +system.cpu1.numCycles 94513077683 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed -system.cpu1.committedInsts 477990846 # Number of instructions committed -system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses -system.cpu1.num_func_calls 28237407 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls -system.cpu1.num_int_insts 516282159 # number of integer instructions -system.cpu1.num_fp_insts 374678 # number of float instructions -system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read -system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written -system.cpu1.num_mem_refs 171406825 # number of memory refs -system.cpu1.num_load_insts 90251973 # Number of load instructions -system.cpu1.num_store_insts 81154852 # Number of store instructions -system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles -system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles -system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles -system.cpu1.Branches 106497601 # Number of branches fetched +system.cpu1.kern.inst.quiesce 6271 # number of quiesce instructions executed +system.cpu1.committedInsts 481403040 # Number of instructions committed +system.cpu1.committedOps 566527691 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 519926686 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 376275 # Number of float alu accesses +system.cpu1.num_func_calls 28379648 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 73708476 # number of instructions that are conditional controls +system.cpu1.num_int_insts 519926686 # number of integer instructions +system.cpu1.num_fp_insts 376275 # number of float instructions +system.cpu1.num_int_register_reads 767885454 # number of times the integer registers were read +system.cpu1.num_int_register_writes 413863113 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 612543 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 304496 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 127271010 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 126985650 # number of times the CC registers were written +system.cpu1.num_mem_refs 172748485 # number of memory refs +system.cpu1.num_load_insts 90938541 # Number of load instructions +system.cpu1.num_store_insts 81809944 # Number of store instructions +system.cpu1.num_idle_cycles 93946236472.485764 # Number of idle cycles +system.cpu1.num_busy_cycles 566841210.514243 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005997 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994003 # Percentage of idle cycles +system.cpu1.Branches 107246711 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction -system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction -system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction -system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 392852056 69.31% 69.31% # Class of executed instruction +system.cpu1.op_class::IntMult 1138487 0.20% 69.51% # Class of executed instruction +system.cpu1.op_class::IntDiv 60879 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 36493 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::MemRead 90938541 16.04% 85.57% # Class of executed instruction +system.cpu1.op_class::MemWrite 81809944 14.43% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 562879339 # Class of executed instruction -system.cpu1.dcache.tags.replacements 5945049 # number of replacements -system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. +system.cpu1.op_class::total 566836400 # Class of executed instruction +system.cpu1.dcache.tags.replacements 5963482 # number of replacements +system.cpu1.dcache.tags.tagsinuse 422.067067 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 166672957 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5963994 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.946533 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 422.067067 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.824350 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.824350 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 76981821 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 76981821 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 63451 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 63451 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048602 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2048602 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 160679385 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 160679385 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 160867239 # number of overall hits -system.cpu1.dcache.overall_hits::total 160867239 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1461655 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1461655 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 427048 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 427048 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159147 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 159147 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4819877 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4819877 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5612228 # number of overall misses -system.cpu1.dcache.overall_misses::total 5612228 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 490499 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 490499 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018633 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018633 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870640 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870640 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029123 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029123 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033711 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033711 # miss rate for overall accesses +system.cpu1.dcache.tags.tag_accesses 351517490 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 351517490 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 84375671 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 84375671 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 77626077 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 77626077 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188285 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 188285 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 64906 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 64906 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062470 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2062470 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2047972 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2047972 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 162001748 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 162001748 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 162190033 # number of overall hits +system.cpu1.dcache.overall_hits::total 162190033 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3369907 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3369907 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1463826 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1463826 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 790298 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 790298 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 435847 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 435847 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 145888 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 145888 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 159002 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 159002 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4833733 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4833733 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5624031 # number of overall misses +system.cpu1.dcache.overall_misses::total 5624031 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87745578 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87745578 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 79089903 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 79089903 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 978583 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 978583 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 500753 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 500753 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2208358 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2208358 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2206974 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2206974 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 166835481 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 166835481 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 167814064 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 167814064 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038405 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038405 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018508 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018508 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.807594 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.807594 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870383 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.870383 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066062 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066062 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.072045 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.072045 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028973 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.028973 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033513 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033513 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -925,49 +923,49 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5945049 # number of writebacks -system.cpu1.dcache.writebacks::total 5945049 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 5963482 # number of writebacks +system.cpu1.dcache.writebacks::total 5963482 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4741297 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 4804881 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.439171 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 476906226 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4805393 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.243959 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.439171 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969608 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969608 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits -system.cpu1.icache.overall_hits::total 473560604 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses -system.cpu1.icache.overall_misses::total 4741809 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 968228631 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 968228631 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 476906226 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 476906226 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 476906226 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 476906226 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 476906226 # number of overall hits +system.cpu1.icache.overall_hits::total 476906226 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4805393 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4805393 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4805393 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4805393 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4805393 # number of overall misses +system.cpu1.icache.overall_misses::total 4805393 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 481711619 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 481711619 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 481711619 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 481711619 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 481711619 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 481711619 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009976 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009976 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009976 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009976 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009976 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009976 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -976,8 +974,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 4741297 # number of writebacks -system.cpu1.icache.writebacks::total 4741297 # number of writebacks +system.cpu1.icache.writebacks::writebacks 4804881 # number of writebacks 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count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.327815 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9713557375000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 13222.980748 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 46.246601 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.385297 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.807067 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002823 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003991 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.813880 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 89 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1627 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6185 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4247 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3746 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005432 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 361919913 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 361919913 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 346945 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 153602 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 500547 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 4020160 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 4020160 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6665818 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6665818 # number of WritebackClean hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1056 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1056 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614983 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 614983 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4283593 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4283593 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3077520 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 3077520 # number of ReadSharedReq hits -system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161463 # number of InvalidateReq hits -system.cpu1.l2cache.InvalidateReq_hits::total 161463 # number of InvalidateReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 346945 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 153602 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4283593 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3692503 # number of demand (read+write) hits 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4741809 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10877862 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 359405 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 163365 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10877862 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059762 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.042510 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.992765 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.992765 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.tags.replacements 2273518 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13372.591247 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 14355328 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2289651 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.269658 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9713557312500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 13267.841352 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.789421 # Average occupied blocks per requestor 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blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 317 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1558 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5907 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3824 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980103 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 364667597 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 364667597 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 349833 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155576 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 505409 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 4030572 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 4030572 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 6737405 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 6737405 # number of WritebackClean hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1033 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1033 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 606896 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 606896 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4338388 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 4338388 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3076039 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 3076039 # number of ReadSharedReq hits +system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 163041 # number of InvalidateReq hits +system.cpu1.l2cache.InvalidateReq_hits::total 163041 # number of InvalidateReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 349833 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 155576 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4338388 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3682935 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8526732 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 349833 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 155576 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4338388 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3682935 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8526732 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12358 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9778 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 22136 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 147541 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 147541 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 159002 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 159002 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708595 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 708595 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 467005 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 467005 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1230054 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 1230054 # number of ReadSharedReq misses +system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 272567 # number of InvalidateReq misses +system.cpu1.l2cache.InvalidateReq_misses::total 272567 # number of InvalidateReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12358 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9778 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 467005 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1938649 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2427790 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12358 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9778 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 467005 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1938649 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2427790 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 362191 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 165354 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 527545 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 4030572 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 4030572 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 6737405 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 6737405 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 148574 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 148574 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 159002 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 159002 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315491 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1315491 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4805393 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 4805393 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4306093 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 4306093 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 435608 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.InvalidateReq_accesses::total 435608 # number of InvalidateReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 362191 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 165354 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4805393 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5621584 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10954522 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 362191 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 165354 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4805393 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5621584 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10954522 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059134 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.041960 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.993047 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.993047 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532649 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532649 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.096633 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.096633 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.283863 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.283863 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.621730 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.621730 # miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059762 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.096633 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.342185 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.220744 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034668 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059762 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.096633 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.342185 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.220744 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.538654 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.538654 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097184 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097184 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.285654 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.285654 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.625716 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.625716 # miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059134 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097184 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.344858 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.221624 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.034120 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059134 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097184 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.344858 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.221624 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1126,57 +1126,57 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1179503 # number of writebacks -system.cpu1.l2cache.writebacks::total 1179503 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1197492 # number of writebacks +system.cpu1.l2cache.writebacks::total 1197492 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 22049015 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11267078 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 368 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1760820 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1760650 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 170 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 606211 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4020160 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6665818 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 145967 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159147 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 305114 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4741809 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4297393 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 426846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 426846 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14225112 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18660714 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 34085270 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 606915272 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 739752124 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1351465172 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5690396 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 27910438 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.072996 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.260153 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 22219563 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11356978 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1770232 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1770046 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 186 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 610577 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9722063 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 5621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 5621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4030572 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6737791 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 148574 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 159002 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 307576 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1315491 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1315491 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4805393 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4306093 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 435608 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 435608 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14415927 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18715946 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 368094 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 841114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 34341081 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 615058056 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 741477723 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3364456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1361372611 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5728933 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 28119998 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.072981 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.260131 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 25873264 92.70% 92.70% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 2037004 7.30% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 170 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 26067955 92.70% 92.70% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 2051857 7.30% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 186 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 27910438 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution -system.iobus.trans_dist::WriteReq 136634 # Transaction distribution -system.iobus.trans_dist::WriteResp 136634 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.snoop_fanout::total 28119998 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40311 # Transaction distribution +system.iobus.trans_dist::ReadResp 40311 # Transaction distribution +system.iobus.trans_dist::WriteReq 136636 # Transaction distribution +system.iobus.trans_dist::WriteResp 136636 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -1189,13 +1189,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353894 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1208,54 +1208,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115585 # number of replacements -system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use +system.iobus.pkt_size::total 7496713 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115596 # number of replacements +system.iocache.tags.tagsinuse 11.294855 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.848747 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.446108 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240547 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465382 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705928 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040793 # Number of tag accesses -system.iocache.tags.data_accesses 1040793 # Number of data accesses +system.iocache.tags.tag_accesses 1040892 # Number of tag accesses +system.iocache.tags.data_accesses 1040892 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses -system.iocache.demand_misses::total 8916 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8887 # number of demand (read+write) misses +system.iocache.demand_misses::total 8927 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8876 # number of overall misses -system.iocache.overall_misses::total 8916 # number of overall misses +system.iocache.overall_misses::realview.ide 8887 # number of overall misses +system.iocache.overall_misses::total 8927 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8887 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8927 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8887 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8927 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1280,191 +1280,193 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1759418 # number of replacements -system.l2c.tags.tagsinuse 62296.253449 # Cycle average of tags in use -system.l2c.tags.total_refs 4473392 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1817492 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.461299 # Average number of references to valid blocks. +system.l2c.tags.replacements 1772759 # number of replacements +system.l2c.tags.tagsinuse 62623.636789 # Cycle average of tags in use +system.l2c.tags.total_refs 4610700 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1831680 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.517197 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 34373.643780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 42.521667 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 58.768031 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3224.697109 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7016.159468 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 270.222583 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 416.861208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2985.929949 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13907.449654 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.524500 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000897 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.049205 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.107058 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004123 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006361 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.045562 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.212211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.950565 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 212 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 57862 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 34513.616341 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.391588 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 102.836315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3358.057391 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7927.916069 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 241.822259 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 388.027254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2900.077291 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13121.892282 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.526636 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001059 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051240 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.120970 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.005921 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.044252 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.200224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.955561 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 194 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58727 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 539 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3515 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5475 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48284 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.882904 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 73042126 # Number of tag accesses -system.l2c.tags.data_accesses 73042126 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2746880 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2746880 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 14674 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12828 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 27502 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1473 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1269 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2742 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 316195 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 262623 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 578818 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4560 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 446108 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 731335 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5573 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 3622 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 416632 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 676220 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2290398 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4560 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 446108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 1047530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5573 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 416632 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 938843 # number of demand (read+write) hits -system.l2c.demand_hits::total 2869216 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4560 # number of overall hits -system.l2c.overall_hits::cpu0.inst 446108 # number of overall hits -system.l2c.overall_hits::cpu0.data 1047530 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5573 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3622 # number of overall hits -system.l2c.overall_hits::cpu1.inst 416632 # number of overall hits -system.l2c.overall_hits::cpu1.data 938843 # number of overall hits -system.l2c.overall_hits::total 2869216 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 68066 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 63332 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 131398 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7840 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7476 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 15316 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 815697 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 546954 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 1362651 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2376 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1983 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 57665 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 181479 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3468 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3439 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 41584 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 187193 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 479187 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2376 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1983 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 57665 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 997176 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3468 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3439 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 41584 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 734147 # number of demand (read+write) misses -system.l2c.demand_misses::total 1841838 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2376 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1983 # number of overall misses -system.l2c.overall_misses::cpu0.inst 57665 # number of overall misses -system.l2c.overall_misses::cpu0.data 997176 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3468 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3439 # number of overall misses -system.l2c.overall_misses::cpu1.inst 41584 # number of overall misses -system.l2c.overall_misses::cpu1.data 734147 # number of overall misses -system.l2c.overall_misses::total 1841838 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 2746880 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 2746880 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 82740 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 76160 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 158900 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9313 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8745 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18058 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1131892 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 809577 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1941469 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8724 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6543 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 503773 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 912814 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9041 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7061 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 458216 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 863413 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 2769585 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8724 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6543 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 503773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 2044706 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9041 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7061 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 458216 # number of demand (read+write) accesses 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0.173589 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.308861 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.118230 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.492987 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.471268 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.088290 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.431924 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.390914 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.281214 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.308861 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.118230 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.492987 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.382432 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.471268 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.088290 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.431924 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.390914 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1473,51 +1475,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1470290 # number of writebacks -system.l2c.writebacks::total 1470290 # number of writebacks +system.l2c.writebacks::writebacks 1476146 # number of writebacks +system.l2c.writebacks::total 1476146 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 82131 # Transaction distribution -system.membus.trans_dist::ReadResp 570231 # Transaction distribution -system.membus.trans_dist::WriteReq 38802 # Transaction distribution -system.membus.trans_dist::WriteResp 38802 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1576984 # Transaction distribution -system.membus.trans_dist::CleanEvict 244820 # Transaction distribution -system.membus.trans_dist::UpgradeReq 347427 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 314914 # Transaction distribution -system.membus.trans_dist::UpgradeResp 168909 # Transaction distribution -system.membus.trans_dist::ReadExReq 1611622 # Transaction distribution -system.membus.trans_dist::ReadExResp 1340459 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 488100 # Transaction distribution +system.membus.trans_dist::ReadReq 82185 # Transaction distribution +system.membus.trans_dist::ReadResp 571969 # Transaction distribution +system.membus.trans_dist::WriteReq 38847 # Transaction distribution +system.membus.trans_dist::WriteResp 38847 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1582840 # Transaction distribution +system.membus.trans_dist::CleanEvict 248395 # Transaction distribution +system.membus.trans_dist::UpgradeReq 346027 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 310425 # Transaction distribution +system.membus.trans_dist::UpgradeResp 161621 # Transaction distribution +system.membus.trans_dist::ReadExReq 1349349 # Transaction distribution +system.membus.trans_dist::ReadExResp 1343882 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 489784 # Transaction distribution system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6542117 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6692337 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 344320 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7036657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6280303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6430721 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346906 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6777627 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 210749660 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 210960657 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 218359505 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211450588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 211661967 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7399552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7399552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 219061519 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4814081 # Request fanout histogram +system.membus.snoop_fanout::samples 4554580 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4814081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4554580 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4814081 # Request fanout histogram +system.membus.snoop_fanout::total 4554580 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1570,41 +1572,41 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 11103531 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5720804 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1657088 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 128474 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 115294 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 13180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 82133 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3545235 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 2746880 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1000532 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 352734 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 317656 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 670390 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2212632 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2212632 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3463102 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9045879 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7635651 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 16681530 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295373981 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 244078084 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 539452065 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1992317 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 13215112 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.283607 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.452956 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 11149388 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5745365 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1662887 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 135292 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 121804 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 13488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 82187 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3554010 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38847 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38847 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 2756862 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2018423 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 360088 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 315545 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 675633 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2226645 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2226645 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3471823 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9531217 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8234338 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17765555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 294166716 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 247379555 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 541546271 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2005695 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 13274431 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.283856 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.453116 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 9480390 71.74% 71.74% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3721542 28.16% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 13180 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 9519891 71.72% 71.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3741052 28.18% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 13488 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 13215112 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 13274431 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 3d9d35410..f426a8e38 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111153 # Number of seconds simulated -sim_ticks 51111152682000 # Number of ticks simulated -final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111167 # Number of seconds simulated +sim_ticks 51111167216500 # Number of ticks simulated +final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 958498 # Simulator instruction rate (inst/s) -host_op_rate 1126393 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49757685011 # Simulator tick rate (ticks/s) -host_mem_usage 676912 # Number of bytes of host memory used -host_seconds 1027.20 # Real time elapsed on the host -sim_insts 984570519 # Number of instructions simulated -sim_ops 1157031967 # Number of ops (including micro ops) simulated +host_inst_rate 1152055 # Simulator instruction rate (inst/s) +host_op_rate 1353914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59949794817 # Simulator tick rate (ticks/s) +host_mem_usage 676672 # Number of bytes of host memory used +host_seconds 852.57 # Real time elapsed on the host +sim_insts 982203438 # Number of instructions simulated +sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 376704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5485940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 110128008 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 116845116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5485940 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103078272 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 414464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 373568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5483956 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 110253960 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 116962748 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5483956 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277504 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103098852 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5886 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 126125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1720763 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1866125 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610598 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103298084 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6476 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5837 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 126094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1722731 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1867963 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613711 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1613171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 107334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2154677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2286098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 107334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016747 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1616284 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7309 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 107295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2157140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2288399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 107295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020645 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2017150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016747 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 107334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2155079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4303248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021047 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 107295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2157543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4309446 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -103,45 +103,45 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 265715 # Table walker walks requested -system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 266586 # Table walker walks requested +system.cpu.dtb.walker.walksLong 266586 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 266586 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 266586 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 266586 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 204773 89.35% 89.35% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24417 10.65% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 229190 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 266586 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 266586 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 229190 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 229190 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 495776 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184014035 # DTB read hits -system.cpu.dtb.read_misses 194198 # DTB read misses -system.cpu.dtb.write_hits 168232768 # DTB write hits -system.cpu.dtb.write_misses 71517 # DTB write misses +system.cpu.dtb.read_hits 183545125 # DTB read hits +system.cpu.dtb.read_misses 195347 # DTB read misses +system.cpu.dtb.write_hits 167774776 # DTB write hits +system.cpu.dtb.write_misses 71239 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82503 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9079 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184208233 # DTB read accesses -system.cpu.dtb.write_accesses 168304285 # DTB write accesses +system.cpu.dtb.read_accesses 183740472 # DTB read accesses +system.cpu.dtb.write_accesses 167846015 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 352246803 # DTB hits -system.cpu.dtb.misses 265715 # DTB misses -system.cpu.dtb.accesses 352512518 # DTB accesses +system.cpu.dtb.hits 351319901 # DTB hits +system.cpu.dtb.misses 266586 # DTB misses +system.cpu.dtb.accesses 351586487 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,26 +171,26 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 126837 # Table walker walks requested -system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 126834 # Table walker walks requested +system.cpu.itb.walker.walksLong 126834 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126834 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126834 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126834 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 113574 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114696 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126834 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126834 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 985047321 # ITB inst hits -system.cpu.itb.inst_misses 126837 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114696 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114696 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241530 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 982680284 # ITB inst hits +system.cpu.itb.inst_misses 126834 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -199,159 +199,159 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58073 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 985174158 # ITB inst accesses -system.cpu.itb.hits 985047321 # DTB hits -system.cpu.itb.misses 126837 # DTB misses -system.cpu.itb.accesses 985174158 # DTB accesses -system.cpu.numCycles 102222322140 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 982807118 # ITB inst accesses +system.cpu.itb.hits 982680284 # DTB hits +system.cpu.itb.misses 126834 # DTB misses +system.cpu.itb.accesses 982807118 # DTB accesses +system.cpu.numCycles 102222351209 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.committedInsts 984570519 # Number of instructions committed -system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses -system.cpu.num_func_calls 57056367 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls -system.cpu.num_int_insts 1060455466 # number of integer instructions -system.cpu.num_fp_insts 880805 # number of float instructions -system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read -system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read -system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written -system.cpu.num_mem_refs 352465606 # number of memory refs -system.cpu.num_load_insts 184180431 # Number of load instructions -system.cpu.num_store_insts 168285175 # Number of store instructions -system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles -system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles -system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988675 # Percentage of idle cycles -system.cpu.Branches 220088562 # Number of branches fetched +system.cpu.committedInsts 982203438 # Number of instructions committed +system.cpu.committedOps 1154301153 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1057882257 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 881349 # Number of float alu accesses +system.cpu.num_func_calls 56834581 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151623749 # number of instructions that are conditional controls +system.cpu.num_int_insts 1057882257 # number of integer instructions +system.cpu.num_fp_insts 881349 # number of float instructions +system.cpu.num_int_register_reads 1560759680 # number of times the integer registers were read +system.cpu.num_int_register_writes 840517080 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1419767 # number of times the floating registers were read +system.cpu.num_fp_register_writes 748560 # number of times the floating registers were written +system.cpu.num_cc_register_reads 264018606 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263440831 # number of times the CC registers were written +system.cpu.num_mem_refs 351539335 # number of memory refs +system.cpu.num_load_insts 183712430 # Number of load instructions +system.cpu.num_store_insts 167826905 # Number of store instructions +system.cpu.num_idle_cycles 101067403446.976273 # Number of idle cycles +system.cpu.num_busy_cycles 1154947762.023731 # Number of busy cycles +system.cpu.not_idle_fraction 0.011298 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.988702 # Percentage of idle cycles +system.cpu.Branches 219534054 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction -system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction -system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 800833693 69.34% 69.34% # Class of executed instruction +system.cpu.op_class::IntMult 2354384 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntDiv 100543 0.01% 69.55% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu.op_class::MemRead 183712430 15.91% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 167826905 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1157666593 # Class of executed instruction -system.cpu.dcache.tags.replacements 11612141 # number of replacements +system.cpu.op_class::total 1154935820 # Class of executed instruction +system.cpu.dcache.tags.replacements 11606642 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 339855471 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11607154 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.279828 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 337709 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits -system.cpu.dcache.overall_hits::total 331514149 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1245349 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1245349 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1417457719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1417457719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 171110770 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171110770 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159073533 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159073533 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424465 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424465 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 336285 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 336285 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4303642 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4303642 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4555646 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 330184303 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 330184303 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 330608768 # number of overall hits +system.cpu.dcache.overall_hits::total 330608768 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6003373 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6003373 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2568142 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2568142 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1586202 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1586202 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1246770 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1246770 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253809 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253809 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses -system.cpu.dcache.overall_misses::total 10164734 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583058 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1583058 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786673 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 8571515 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8571515 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10157717 # number of overall misses +system.cpu.dcache.overall_misses::total 10157717 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177114143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 161641675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2010667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2010667 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1583055 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4555647 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 338755818 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 338755818 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 340766485 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 340766485 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033896 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033896 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015888 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015888 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788893 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788893 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787572 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055691 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055691 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025303 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029808 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,49 +360,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8921277 # number of writebacks -system.cpu.dcache.writebacks::total 8921277 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8917390 # number of writebacks +system.cpu.dcache.writebacks::total 8917390 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 14295641 # number of replacements +system.cpu.icache.tags.replacements 14265253 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 968529210 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses -system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits -system.cpu.icache.overall_hits::total 970865862 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses -system.cpu.icache.overall_misses::total 14296158 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 997060750 # Number of tag accesses +system.cpu.icache.tags.data_accesses 997060750 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 968529210 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 968529210 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 968529210 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 968529210 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 968529210 # number of overall hits +system.cpu.icache.overall_hits::total 968529210 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14265770 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14265770 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14265770 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14265770 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14265770 # number of overall misses +system.cpu.icache.overall_misses::total 14265770 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 982794980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 982794980 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 982794980 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014516 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014516 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses 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number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1723188 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65341.862570 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 46967342 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1786484 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 26.290379 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1725806 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65319.576270 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 46897183 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1788825 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 26.216753 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37239.479155 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.194068 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.716842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6119.396908 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 21229.075596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.568229 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.093375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.323930 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63018 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 37200.311271 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 312.624573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 447.819467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6075.912411 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21282.908549 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.567632 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004770 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006833 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.092711 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 320 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62699 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 320 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54670 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961578 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 426185861 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 426185861 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255620 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 762232 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14294063 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1692549 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1692549 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14213121 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 14213121 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7503843 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 7503843 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 694318 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 694318 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 255620 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14213121 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9196392 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24171745 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 255620 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14213121 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9196392 # number of overall hits -system.cpu.l2cache.overall_hits::total 24171745 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5886 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 12329 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 608 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4924 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956711 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 425634048 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 425634048 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 509091 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255953 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 765044 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 8917390 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 8917390 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 14263676 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 14263676 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 11205 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 11205 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1689414 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1689414 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14182764 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 14182764 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7499286 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 7499286 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 694547 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 694547 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 509091 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 255953 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14182764 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9188700 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24136508 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 509091 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 255953 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14182764 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9188700 # number of overall hits +system.cpu.l2cache.overall_hits::total 24136508 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6476 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5837 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 12313 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39924 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39924 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 826568 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 826568 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83037 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 83037 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344355 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 344355 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 551031 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 551031 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5886 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 83037 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1170923 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1266289 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5886 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 83037 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1170923 # number of overall misses -system.cpu.l2cache.overall_misses::total 1266289 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 774561 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 8921277 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 8921277 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 14294063 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 14294063 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 827599 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 827599 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83006 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 83006 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 344098 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 344098 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 552223 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 552223 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6476 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5837 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 83006 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1171697 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1267016 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6476 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5837 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 83006 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1171697 # number of overall misses +system.cpu.l2cache.overall_misses::total 1267016 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 515567 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261790 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 777357 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 8917390 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 8917390 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 14263676 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 14263676 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51129 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 51129 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14296158 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 14296158 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7848198 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7848198 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1245349 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1245349 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022508 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015917 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2517013 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2517013 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 14265770 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 14265770 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7843384 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1246770 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 515567 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 261790 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14265770 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10360397 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25403524 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 515567 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 261790 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14265770 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10360397 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25403524 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012561 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022296 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015840 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780848 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780848 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328118 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.328118 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005808 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442471 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442471 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022508 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005808 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.112944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.049779 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022508 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005808 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.112944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.049779 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328802 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005819 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043871 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.442923 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.442923 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012561 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022296 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005819 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.113094 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049876 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012561 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022296 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005819 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.113094 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049876 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,55 +557,55 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1503967 # number of writebacks -system.cpu.l2cache.writebacks::total 1503967 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1507080 # number of writebacks +system.cpu.l2cache.writebacks::total 1507080 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 52457192 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 26548378 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 52385887 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 26512957 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 1227763 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 1229988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23339142 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51129 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42972629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35073902 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 80348699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 3073814874 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1954989 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 55083286 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.010814 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103427 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 51130 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42883043 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35057556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758208 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1548410 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 80247217 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6193640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 3069352482 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1957577 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 55016338 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.010835 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103527 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 54487613 98.92% 98.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 595673 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 54420225 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 596113 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 55083286 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40246 # Transaction distribution -system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::total 55016338 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40242 # Transaction distribution +system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -622,11 +622,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -641,53 +641,53 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115463 # number of replacements -system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use +system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039686 # Number of tag accesses -system.iocache.tags.data_accesses 1039686 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses -system.iocache.demand_misses::total 8857 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8817 # number of overall misses -system.iocache.overall_misses::total 8857 # number of overall misses +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -713,47 +713,47 @@ system.iocache.writebacks::writebacks 106631 # nu system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 525254 # Transaction distribution +system.membus.trans_dist::ReadResp 524946 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1610598 # Transaction distribution -system.membus.trans_dist::CleanEvict 224691 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613711 # Transaction distribution +system.membus.trans_dist::CleanEvict 226320 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40491 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377033 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377033 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448575 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40492 # Transaction distribution +system.membus.trans_dist::ReadExReq 1379258 # Transaction distribution +system.membus.trans_dist::ReadExResp 1379258 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448267 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5527811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5657003 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6001377 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5534278 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5663470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6009963 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212719264 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212888314 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220279354 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213041440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213210490 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220601274 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3920464 # Request fanout histogram +system.membus.snoop_fanout::samples 3924997 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3920464 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3924997 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3920464 # Request fanout histogram +system.membus.snoop_fanout::total 3924997 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index afe64e1a8..1114600cf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.593744 # Number of seconds simulated -sim_ticks 47593744171500 # Number of ticks simulated -final_tick 47593744171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.602418 # Number of seconds simulated +sim_ticks 47602418253500 # Number of ticks simulated +final_tick 47602418253500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 618435 # Simulator instruction rate (inst/s) -host_op_rate 727668 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34163076444 # Simulator tick rate (ticks/s) -host_mem_usage 740160 # Number of bytes of host memory used -host_seconds 1393.13 # Real time elapsed on the host -sim_insts 861562684 # Number of instructions simulated -sim_ops 1013739401 # Number of ops (including micro ops) simulated +host_inst_rate 704375 # Simulator instruction rate (inst/s) +host_op_rate 828740 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38464814262 # Simulator tick rate (ticks/s) +host_mem_usage 746580 # Number of bytes of host memory used +host_seconds 1237.56 # Real time elapsed on the host +sim_insts 871704321 # Number of instructions simulated +sim_ops 1025613965 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 69440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 68224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3088500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37423496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 12959872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 98944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 107776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2567544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 15084176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 9154944 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory -system.physmem.bytes_read::total 81051908 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3088500 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2567544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5656044 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 68863296 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 106624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 114944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3306740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 39207752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13461760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 71360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 71552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2461816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 13970768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 8718016 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430784 # Number of bytes read from this memory +system.physmem.bytes_read::total 81922116 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3306740 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2461816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5768556 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69209472 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 68883880 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1066 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 88665 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 584755 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 202498 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1546 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1684 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 40206 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 235703 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 143046 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1306957 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1075989 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69230056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1796 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 612634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 210340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 38554 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 218306 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 136219 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6731 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1320554 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1081398 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1078563 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 786311 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 272302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 316936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 192356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1702995 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 118840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1446898 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1083972 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 823650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 282796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 293489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 183142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1720965 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51716 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 121182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1453907 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1447331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1446898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1433 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 786744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 272302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 316936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 192356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3150326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1306957 # Number of read requests accepted -system.physmem.writeReqs 1078563 # Number of write requests accepted -system.physmem.readBursts 1306957 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1078563 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 83609728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue -system.physmem.bytesWritten 68881216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 81051908 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 68883880 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 450744 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 74137 # Per bank write bursts -system.physmem.perBankRdBursts::1 79440 # Per bank write bursts -system.physmem.perBankRdBursts::2 74164 # Per bank write bursts -system.physmem.perBankRdBursts::3 81483 # Per bank write bursts -system.physmem.perBankRdBursts::4 82988 # Per bank write bursts -system.physmem.perBankRdBursts::5 89928 # Per bank write bursts -system.physmem.perBankRdBursts::6 78492 # Per bank write bursts -system.physmem.perBankRdBursts::7 81076 # Per bank write bursts -system.physmem.perBankRdBursts::8 74414 # Per bank write bursts -system.physmem.perBankRdBursts::9 117966 # Per bank write bursts -system.physmem.perBankRdBursts::10 72212 # Per bank write bursts -system.physmem.perBankRdBursts::11 83486 # Per bank write bursts -system.physmem.perBankRdBursts::12 77461 # Per bank write bursts -system.physmem.perBankRdBursts::13 81836 # Per bank write bursts -system.physmem.perBankRdBursts::14 80080 # Per bank write bursts -system.physmem.perBankRdBursts::15 77239 # Per bank write bursts -system.physmem.perBankWrBursts::0 62409 # Per bank write bursts -system.physmem.perBankWrBursts::1 67459 # Per bank write bursts -system.physmem.perBankWrBursts::2 64157 # Per bank write bursts -system.physmem.perBankWrBursts::3 68996 # Per bank write bursts -system.physmem.perBankWrBursts::4 69521 # Per bank write bursts -system.physmem.perBankWrBursts::5 74527 # Per bank write bursts -system.physmem.perBankWrBursts::6 66146 # Per bank write bursts -system.physmem.perBankWrBursts::7 68657 # Per bank write bursts -system.physmem.perBankWrBursts::8 63193 # Per bank write bursts -system.physmem.perBankWrBursts::9 66730 # Per bank write bursts -system.physmem.perBankWrBursts::10 63431 # Per bank write bursts -system.physmem.perBankWrBursts::11 70210 # Per bank write bursts -system.physmem.perBankWrBursts::12 65844 # Per bank write bursts -system.physmem.perBankWrBursts::13 70148 # Per bank write bursts -system.physmem.perBankWrBursts::14 68557 # Per bank write bursts -system.physmem.perBankWrBursts::15 66284 # Per bank write bursts +system.physmem.bw_write::total 1454339 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1453907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2415 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 824083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 282796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 293489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 183142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3175304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1320554 # Number of read requests accepted +system.physmem.writeReqs 1083972 # Number of write requests accepted +system.physmem.readBursts 1320554 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1083972 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 84482048 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33408 # Total number of bytes read from write queue +system.physmem.bytesWritten 69229248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 81922116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 69230056 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 522 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 79060 # Per bank write bursts +system.physmem.perBankRdBursts::1 84693 # Per bank write bursts +system.physmem.perBankRdBursts::2 79264 # Per bank write bursts +system.physmem.perBankRdBursts::3 82906 # Per bank write bursts +system.physmem.perBankRdBursts::4 76161 # Per bank write bursts +system.physmem.perBankRdBursts::5 86285 # Per bank write bursts +system.physmem.perBankRdBursts::6 80943 # Per bank write bursts +system.physmem.perBankRdBursts::7 81570 # Per bank write bursts +system.physmem.perBankRdBursts::8 74520 # Per bank write bursts +system.physmem.perBankRdBursts::9 121634 # Per bank write bursts +system.physmem.perBankRdBursts::10 72298 # Per bank write bursts +system.physmem.perBankRdBursts::11 79752 # Per bank write bursts +system.physmem.perBankRdBursts::12 77563 # Per bank write bursts +system.physmem.perBankRdBursts::13 85585 # Per bank write bursts +system.physmem.perBankRdBursts::14 78768 # Per bank write bursts +system.physmem.perBankRdBursts::15 79030 # Per bank write bursts +system.physmem.perBankWrBursts::0 65472 # Per bank write bursts +system.physmem.perBankWrBursts::1 70626 # Per bank write bursts +system.physmem.perBankWrBursts::2 66791 # Per bank write bursts +system.physmem.perBankWrBursts::3 69615 # Per bank write bursts +system.physmem.perBankWrBursts::4 63756 # Per bank write bursts +system.physmem.perBankWrBursts::5 71331 # Per bank write bursts +system.physmem.perBankWrBursts::6 67500 # Per bank write bursts +system.physmem.perBankWrBursts::7 68943 # Per bank write bursts +system.physmem.perBankWrBursts::8 63410 # Per bank write bursts +system.physmem.perBankWrBursts::9 68673 # Per bank write bursts +system.physmem.perBankWrBursts::10 63007 # Per bank write bursts +system.physmem.perBankWrBursts::11 67951 # Per bank write bursts +system.physmem.perBankWrBursts::12 66506 # Per bank write bursts +system.physmem.perBankWrBursts::13 73077 # Per bank write bursts +system.physmem.perBankWrBursts::14 66769 # Per bank write bursts +system.physmem.perBankWrBursts::15 68280 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 47593740806000 # Total gap between requests +system.physmem.numWrRetry 42 # Number of times write queue was full causing retry +system.physmem.totGap 47602414888000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1263732 # Read request sizes (log2) +system.physmem.readPktSize::6 1277329 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1075989 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1091015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 68737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22184 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 19490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 16927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 14904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 11891 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1081398 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1104957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 68933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 25891 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 22057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 19390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 16894 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 14853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 11934 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 532 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -188,163 +188,167 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 18318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 20896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 46603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 64132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 65344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 67196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 67473 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 69715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 73497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 68447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 71528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 63618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 840117 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 181.511175 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 111.812729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 240.875315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 520248 61.93% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 156423 18.62% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51977 6.19% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27385 3.26% 89.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18542 2.21% 92.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11713 1.39% 93.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8913 1.06% 94.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8910 1.06% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 36006 4.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 840117 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60330 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.654169 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 330.190002 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 60327 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 18639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 53739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 58424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 64493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 65899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 66079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 68869 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 71761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 68201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 69441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 73837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 67956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 64592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 63507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 129 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 850234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 180.786598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 111.487051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 240.213026 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 527654 62.06% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 158419 18.63% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52205 6.14% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27644 3.25% 90.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18445 2.17% 92.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11596 1.36% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9081 1.07% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9121 1.07% 95.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 36069 4.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 850234 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60429 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.843949 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 329.896328 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 60426 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60330 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.839698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.269040 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.176072 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56620 93.85% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1546 2.56% 96.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 276 0.46% 96.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 296 0.49% 97.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 110 0.18% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 266 0.44% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 180 0.30% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 98 0.16% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 97 0.16% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 84 0.14% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 48 0.08% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 66 0.11% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 398 0.66% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 43 0.07% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 35 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 96 0.16% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 19 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60330 # Writes before turning the bus around for reads -system.physmem.totQLat 28430560155 # Total ticks spent queuing -system.physmem.totMemAccLat 52925597655 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6532010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21762.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60429 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60429 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.900462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.285869 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.671229 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 56824 94.03% 94.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1552 2.57% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 279 0.46% 97.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 180 0.30% 97.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 145 0.24% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 117 0.19% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 182 0.30% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 82 0.14% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 275 0.46% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 67 0.11% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 44 0.07% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 253 0.42% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 30 0.05% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 37 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 152 0.25% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60429 # Writes before turning the bus around for reads +system.physmem.totQLat 28489428593 # Total ticks spent queuing +system.physmem.totMemAccLat 53240028593 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6600160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 21582.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40512.49 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.76 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 40332.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing -system.physmem.readRowHits 1047491 # Number of row buffer hits during reads -system.physmem.writeRowHits 495062 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 46.00 # Row buffer hit rate for writes -system.physmem.avgGap 19951096.95 # Average gap between requests -system.physmem.pageHitRate 64.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3221134560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1757563500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5005283400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3511330560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1216360497735 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27489261984750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31827709611225 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.737288 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45730304477620 # Time in different power states -system.physmem_0.memoryStateTime::REF 1589259620000 # Time in different power states +system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing +system.physmem.readRowHits 1056858 # Number of row buffer hits during reads +system.physmem.writeRowHits 494645 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 45.73 # Row buffer hit rate for writes +system.physmem.avgGap 19797005.68 # Average gap between requests +system.physmem.pageHitRate 64.60 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3250149840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1773395250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5076832800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3525340320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1224482966955 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27487341349500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31834608387225 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.760359 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45727050942416 # Time in different power states +system.physmem_0.memoryStateTime::REF 1589549260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 274179379380 # Time in different power states +system.physmem_0.memoryStateTime::ACT 285815210084 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3130149960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1707919125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5184613200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3462892560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1215861151230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27489700008000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31827638550795 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.735795 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45731003279682 # Time in different power states -system.physmem_1.memoryStateTime::REF 1589259620000 # Time in different power states +system.physmem_1.actEnergy 3177619200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1733820000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5219370000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3484121040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3109158352560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1221031665405 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27490368798750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31834173746955 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.751229 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45732072121963 # Time in different power states +system.physmem_1.memoryStateTime::REF 1589549260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 273478576568 # Time in different power states +system.physmem_1.memoryStateTime::ACT 280793976787 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -375,9 +379,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1670 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1674 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -408,68 +412,70 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 93408 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 93408 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7983 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 70276 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 93401 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.278370 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 85.074143 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 93400 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 112758 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 112758 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10038 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 87373 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 112734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.230631 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 77.436531 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 112733 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 93401 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 78266 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22499.341988 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 20923.382111 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16650.912887 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 77590 99.14% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 164 0.21% 99.35% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 417 0.53% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 25 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 78266 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 5219685476 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.596746 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.490551 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2104860204 40.33% 40.33% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 3114825272 59.67% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 5219685476 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 70276 89.80% 89.80% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 7983 10.20% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 78259 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 93408 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 112734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 97435 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23281.346539 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21381.718359 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 19258.937396 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 96246 98.78% 98.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 178 0.18% 98.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 868 0.89% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 20 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 17 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 97435 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 8883013024 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.766632 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.422974 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2073007704 23.34% 23.34% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 6810005320 76.66% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 8883013024 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 87373 89.70% 89.70% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10038 10.30% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 97411 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 112758 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 93408 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78259 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 112758 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97411 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78259 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 171667 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97411 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 210169 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 80327529 # DTB read hits -system.cpu0.dtb.read_misses 69973 # DTB read misses -system.cpu0.dtb.write_hits 72902451 # DTB write hits -system.cpu0.dtb.write_misses 23435 # DTB write misses +system.cpu0.dtb.read_hits 88968055 # DTB read hits +system.cpu0.dtb.read_misses 85634 # DTB read misses +system.cpu0.dtb.write_hits 80360369 # DTB write hits +system.cpu0.dtb.write_misses 27124 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 34709 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 39097 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4393 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 3879 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 8867 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 80397502 # DTB read accesses -system.cpu0.dtb.write_accesses 72925886 # DTB write accesses +system.cpu0.dtb.perms_faults 10141 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 89053689 # DTB read accesses +system.cpu0.dtb.write_accesses 80387493 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 153229980 # DTB hits -system.cpu0.dtb.misses 93408 # DTB misses -system.cpu0.dtb.accesses 153323388 # DTB accesses +system.cpu0.dtb.hits 169328424 # DTB hits +system.cpu0.dtb.misses 112758 # DTB misses +system.cpu0.dtb.accesses 169441182 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,235 +505,236 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 52417 # Table walker walks requested -system.cpu0.itb.walker.walksLong 52417 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 598 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46386 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 52417 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 52417 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 52417 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 46984 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25232.568534 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 22985.913240 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 21269.412068 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 46328 98.60% 98.60% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.09% 98.69% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 530 1.13% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 16 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 24 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 22 0.05% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 46984 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 62308 # Table walker walks requested +system.cpu0.itb.walker.walksLong 62308 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 814 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55869 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 62308 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 62308 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 62308 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 56683 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26679.454157 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23625.111342 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 26536.909948 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 55487 97.89% 97.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.07% 97.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 988 1.74% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 65 0.11% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 49 0.09% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 56683 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46386 98.73% 98.73% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 598 1.27% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 46984 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 55869 98.56% 98.56% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 814 1.44% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56683 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52417 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52417 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 62308 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 62308 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 46984 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 46984 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 99401 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 426699171 # ITB inst hits -system.cpu0.itb.inst_misses 52417 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 118991 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 472241024 # ITB inst hits +system.cpu0.itb.inst_misses 62308 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24801 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28001 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 426751588 # ITB inst accesses -system.cpu0.itb.hits 426699171 # DTB hits -system.cpu0.itb.misses 52417 # DTB misses -system.cpu0.itb.accesses 426751588 # DTB accesses -system.cpu0.numCycles 95186924479 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 472303332 # ITB inst accesses +system.cpu0.itb.hits 472241024 # DTB hits +system.cpu0.itb.misses 62308 # DTB misses +system.cpu0.itb.accesses 472303332 # DTB accesses +system.cpu0.numCycles 95204836507 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4674 # number of quiesce instructions executed -system.cpu0.committedInsts 426454163 # Number of instructions committed -system.cpu0.committedOps 501120280 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 460758133 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 395268 # Number of float alu accesses -system.cpu0.num_func_calls 25675920 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64224693 # number of instructions that are conditional controls -system.cpu0.num_int_insts 460758133 # number of integer instructions -system.cpu0.num_fp_insts 395268 # number of float instructions -system.cpu0.num_int_register_reads 666544840 # number of times the integer registers were read -system.cpu0.num_int_register_writes 365452769 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 661868 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 282064 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110079606 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 109774743 # number of times the CC registers were written -system.cpu0.num_mem_refs 153223313 # number of memory refs -system.cpu0.num_load_insts 80324545 # Number of load instructions -system.cpu0.num_store_insts 72898768 # Number of store instructions -system.cpu0.num_idle_cycles 94023627088.560516 # Number of idle cycles -system.cpu0.num_busy_cycles 1163297390.439485 # Number of busy cycles -system.cpu0.not_idle_fraction 0.012221 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.987779 # Percentage of idle cycles -system.cpu0.Branches 94888903 # Number of branches fetched +system.cpu0.kern.inst.quiesce 5131 # number of quiesce instructions executed +system.cpu0.committedInsts 471986732 # Number of instructions committed +system.cpu0.committedOps 554132163 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 509304939 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 463756 # Number of float alu accesses +system.cpu0.num_func_calls 28209702 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 71348449 # number of instructions that are conditional controls +system.cpu0.num_int_insts 509304939 # number of integer instructions +system.cpu0.num_fp_insts 463756 # number of float instructions +system.cpu0.num_int_register_reads 736700300 # number of times the integer registers were read +system.cpu0.num_int_register_writes 403898232 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 771652 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 344244 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 122509563 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 122079243 # number of times the CC registers were written +system.cpu0.num_mem_refs 169317654 # number of memory refs +system.cpu0.num_load_insts 88962856 # Number of load instructions +system.cpu0.num_store_insts 80354798 # Number of store instructions +system.cpu0.num_idle_cycles 93934250531.242035 # Number of idle cycles +system.cpu0.num_busy_cycles 1270585975.757973 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013346 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986654 # Percentage of idle cycles +system.cpu0.Branches 105166310 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 346960051 69.20% 69.20% # Class of executed instruction -system.cpu0.op_class::IntMult 1125201 0.22% 69.42% # Class of executed instruction -system.cpu0.op_class::IntDiv 62694 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 37154 0.01% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu0.op_class::MemRead 80324545 16.02% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 72898768 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 383762588 69.22% 69.22% # Class of executed instruction +system.cpu0.op_class::IntMult 1237276 0.22% 69.44% # Class of executed instruction +system.cpu0.op_class::IntDiv 66509 0.01% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 45552 0.01% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::MemRead 88962856 16.05% 85.51% # Class of executed instruction +system.cpu0.op_class::MemWrite 80354798 14.49% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 501408413 # Class of executed instruction -system.cpu0.dcache.tags.replacements 5237512 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.877232 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 147745204 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5237891 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.207002 # Average number of references to valid blocks. +system.cpu0.op_class::total 554429579 # Class of executed instruction +system.cpu0.dcache.tags.replacements 5824476 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.611071 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 163267162 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5824987 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.028760 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.877232 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988041 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988041 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 379 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 370 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.740234 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 311719457 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 311719457 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 74802484 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 74802484 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68840975 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 68840975 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186514 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 186514 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 133741 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 133741 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1712983 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1712983 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1673957 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1673957 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 143643459 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 143643459 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 143829973 # number of overall hits -system.cpu0.dcache.overall_hits::total 143829973 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2859232 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2859232 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1316810 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1316810 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 596453 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 596453 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 721743 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 721743 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153137 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 153137 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190741 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 190741 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4176042 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4176042 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4772495 # number of overall misses -system.cpu0.dcache.overall_misses::total 4772495 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45650819500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 45650819500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34330450500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34330450500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65187396500 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 65187396500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2390631500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2390631500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5489081000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 5489081000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7149000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7149000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 79981270000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 79981270000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 79981270000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 79981270000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 77661716 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 77661716 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 70157785 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 70157785 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 782967 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 782967 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 855484 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 855484 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1866120 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1866120 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1864698 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1864698 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 147819501 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 147819501 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 148602468 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 148602468 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036816 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036816 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018769 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.018769 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761786 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.761786 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843666 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843666 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082062 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082062 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102291 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102291 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028251 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028251 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032116 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032116 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15966.112404 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15966.112404 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26070.921773 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 26070.921773 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90319.402474 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90319.402474 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15611.063949 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15611.063949 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28777.667098 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28777.667098 # average StoreCondReq miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.611071 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989475 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989475 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 344508686 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 344508686 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 82887500 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 82887500 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75943802 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75943802 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196404 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 196404 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 140054 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 140054 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1847526 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1847526 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1825483 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1825483 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 158831302 # number of demand (read+write) hits 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+system.cpu0.dcache.LoadLockedReq_misses::total 174919 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195568 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 195568 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4628324 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4628324 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5285860 # number of overall misses +system.cpu0.dcache.overall_misses::total 5285860 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52614413500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 52614413500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36171191500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36171191500 # number of WriteReq miss cycles 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88785605000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 88785605000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 88785605000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 86076698 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 86076698 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 77382928 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 77382928 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 853940 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 853940 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 932854 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 932854 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2022445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2022445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2021051 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2021051 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 163459626 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 163459626 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164313566 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164313566 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037051 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037051 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018597 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018597 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770003 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770003 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.849865 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.849865 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086489 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086489 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.096765 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.096765 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028315 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.028315 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032169 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032169 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16497.694248 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16497.694248 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25134.138012 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25134.138012 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 83524.822780 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 83524.822780 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16055.857283 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16055.857283 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28993.173730 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28993.173730 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19152.410345 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19152.410345 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16758.795976 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16758.795976 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19183.100621 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19183.100621 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16796.813574 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16796.813574 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,156 +743,158 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 5237512 # number of writebacks -system.cpu0.dcache.writebacks::total 5237512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25341 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25341 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21295 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21295 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39838 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39838 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 46636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 46636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 46636 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 46636 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2833891 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2833891 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1295515 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1295515 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595169 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 595169 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 721743 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 721743 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113299 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113299 # number of LoadLockedReq MSHR misses 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-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64465653500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564895500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564895500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5298419000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5298419000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7070000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7070000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73495276000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 73495276000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 88313308000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 88313308000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897717500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897717500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3102799000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3102799000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6000516500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6000516500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036490 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018466 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760146 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760146 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.843666 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.843666 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060714 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060714 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102291 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102291 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027935 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031793 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031793 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14485.695110 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14485.695110 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25043.627438 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25043.627438 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24897.183825 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24897.183825 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89319.402474 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89319.402474 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13812.085720 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.085720 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27778.081273 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27778.081273 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5824476 # number of writebacks +system.cpu0.dcache.writebacks::total 5824476 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27468 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 27468 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21247 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21247 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43989 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43989 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 48715 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 48715 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 48715 # number of overall MSHR hits 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LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195568 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 195568 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4579609 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4579609 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5235861 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5235861 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14992 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14992 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15725 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 15725 # number of WriteReq MSHR uncacheable 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demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97851964000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 97851964000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2585195500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2585195500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2654242000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2654242000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5239437500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5239437500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036732 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036732 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018323 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018323 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768499 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768499 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.849865 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.849865 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064738 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064738 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096765 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096765 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028017 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028017 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031865 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031865 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15037.747847 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15037.747847 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24098.232994 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24098.232994 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24591.600483 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24591.600483 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 82524.822780 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 82524.822780 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13803.436951 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13803.436951 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27993.562341 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27993.562341 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17798.026157 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17798.026157 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18692.328516 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18692.328516 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173039.382539 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173039.382539 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172684.717275 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172684.717275 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172855.807455 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172855.807455 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17842.937465 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17842.937465 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18688.800944 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18688.800944 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172438.333778 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172438.333778 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 168791.224165 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168791.224165 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170571.263470 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170571.263470 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 4772370 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.827216 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 421926289 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 4772882 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.400738 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5187208 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 467053304 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5187720 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 90.030554 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827216 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 395 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 858171224 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 858171224 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 421926289 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 421926289 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 421926289 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 421926289 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 421926289 # number of overall hits -system.cpu0.icache.overall_hits::total 421926289 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 4772882 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 4772882 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 4772882 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 4772882 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 4772882 # number of overall misses -system.cpu0.icache.overall_misses::total 4772882 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52975952000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 52975952000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 52975952000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 52975952000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 52975952000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 52975952000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 426699171 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 426699171 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 426699171 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 426699171 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 426699171 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 426699171 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011186 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011186 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011186 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011186 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011186 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011186 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11099.363445 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 11099.363445 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 11099.363445 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 11099.363445 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 949669768 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 949669768 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 467053304 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 467053304 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 467053304 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 467053304 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 467053304 # number of overall hits +system.cpu0.icache.overall_hits::total 467053304 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5187720 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5187720 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5187720 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5187720 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5187720 # number of overall misses +system.cpu0.icache.overall_misses::total 5187720 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57877602000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 57877602000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 57877602000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 57877602000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 57877602000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 57877602000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 472241024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 472241024 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 472241024 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 472241024 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 472241024 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 472241024 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010985 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010985 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010985 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010985 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010985 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010985 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11156.654947 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 11156.654947 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 11156.654947 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11156.654947 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 11156.654947 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -894,248 +903,252 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 4772370 # number of writebacks -system.cpu0.icache.writebacks::total 4772370 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4772882 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 4772882 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 4772882 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 4772882 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 4772882 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 4772882 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 5187208 # number of writebacks +system.cpu0.icache.writebacks::total 5187208 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5187720 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 5187720 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 5187720 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 5187720 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 5187720 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 5187720 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 50589511000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 50589511000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 50589511000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 50589511000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 50589511000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 50589511000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 55283742000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 55283742000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 55283742000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 55283742000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 55283742000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 55283742000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011186 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011186 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011186 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.363445 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010985 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010985 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010985 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010985 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10656.654947 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10656.654947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10656.654947 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230591 # number of hwpf issued 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# Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2203636 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.402828 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 1030695 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2438237 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16163.287998 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 15536795 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2453930 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.331393 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15163.258465 # Average occupied blocks per requestor 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-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55879.462450 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32045.813087 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32045.813087 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20277.253421 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20277.253421 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 208951.612903 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 208951.612903 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57464.330352 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57464.330352 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33875.330141 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33812.007674 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33812.007674 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 106116.156414 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 106116.156414 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37449.415339 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42999.554401 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227289 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 40125.883979 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53710.651253 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 31385.864378 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31385.864378 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20490.595895 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20490.595895 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400966.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400966.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56072.696294 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56072.696294 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33233.793022 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35933.623236 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35933.623236 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 103366.722006 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 103366.722006 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38184.153016 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 37405.362009 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43402.883601 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33233.793022 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40169.962119 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53710.651253 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42808.499208 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165005.344560 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 140200.614655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165162.149377 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165162.149377 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164416.155283 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139300.006883 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 161266.772655 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161266.772655 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165086.506885 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145962.621565 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 162803.887098 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 143977.932613 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 20776945 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 10662406 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 659 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 1726264 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1726085 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 488069 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 8911186 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 17968 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 17968 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 4874700 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 6546722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 2139143 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 829102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 434919 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350602 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 501065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1159158 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1092705 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4772882 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4419934 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 726049 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 719547 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14404114 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17037537 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296236 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 495044 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 32232931 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 611051348 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 638823901 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1117728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1786944 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1252779921 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5965413 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 16750116 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.116655 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.321042 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 22819923 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11703604 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 1879398 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1879148 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 250 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 571604 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9815849 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 15726 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 15725 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5399709 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 7169213 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 2378526 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 893354 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 436778 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 349583 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 518285 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1259427 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1201684 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5187720 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4806547 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 796318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 790789 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15648898 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18825417 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 354875 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 604975 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 35434165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 664167892 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 709387519 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1351368 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2219552 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1377126331 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 6368237 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 18252902 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.116630 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.321021 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 14796306 88.34% 88.34% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 1953631 11.66% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 16124321 88.34% 88.34% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 2128331 11.66% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 250 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16750116 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 20546913496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 18252902 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 22598952997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 219185391 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 218107077 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7202448000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7824705000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7531952589 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8347252415 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 156520499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 185954998 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 271676000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 327531000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1387,69 +1400,69 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 101882 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 101882 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8030 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79527 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 101873 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.078529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 25.064580 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-511 101872 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 101873 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 87566 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23519.505287 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21365.105207 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20825.826742 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 86337 98.60% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 178 0.20% 98.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 904 1.03% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 19 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 91986 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 91986 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7535 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 69987 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 91981 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.271795 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 82.431072 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 91980 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 91981 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 77527 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23020.089775 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21173.462910 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18225.313395 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 76677 98.90% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 165 0.21% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 586 0.76% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 21 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 87566 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 239339024 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 9.661342 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2072997220 -866.13% -866.13% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 2312336244 966.13% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 239339024 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 79528 90.83% 90.83% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 8030 9.17% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 87558 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101882 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 77527 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -5562525576 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.783829 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.411632 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1202455220 21.62% 21.62% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -4360070356 78.38% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -5562525576 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 69988 90.28% 90.28% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 7535 9.72% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 77523 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 91986 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101882 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87558 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 91986 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77523 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87558 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 189440 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77523 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 169509 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 82176038 # DTB read hits -system.cpu1.dtb.read_misses 74927 # DTB read misses -system.cpu1.dtb.write_hits 74775352 # DTB write hits -system.cpu1.dtb.write_misses 26955 # DTB write misses +system.cpu1.dtb.read_hits 75524944 # DTB read hits +system.cpu1.dtb.read_misses 67300 # DTB read misses +system.cpu1.dtb.write_hits 69031204 # DTB write hits +system.cpu1.dtb.write_misses 24686 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37701 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 34037 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4186 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4586 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10277 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 82250965 # DTB read accesses -system.cpu1.dtb.write_accesses 74802307 # DTB write accesses +system.cpu1.dtb.perms_faults 9261 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 75592244 # DTB read accesses +system.cpu1.dtb.write_accesses 69055890 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 156951390 # DTB hits -system.cpu1.dtb.misses 101882 # DTB misses -system.cpu1.dtb.accesses 157053272 # DTB accesses +system.cpu1.dtb.hits 144556148 # DTB hits +system.cpu1.dtb.misses 91986 # DTB misses +system.cpu1.dtb.accesses 144648134 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1479,236 +1492,237 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 63786 # Table walker walks requested -system.cpu1.itb.walker.walksLong 63786 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 574 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58046 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 63786 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 63786 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 63786 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 58620 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 26694.208461 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23680.273613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 26398.773524 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 57379 97.88% 97.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 45 0.08% 97.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1025 1.75% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 33 0.06% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 49 0.08% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 9 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 58620 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 58046 99.02% 99.02% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 574 0.98% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58620 # Table walker page sizes translated +system.cpu1.itb.walker.walks 54155 # Table walker walks requested +system.cpu1.itb.walker.walksLong 54155 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 390 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 48650 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 54155 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 54155 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 54155 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 49040 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26306.504894 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23642.829205 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24027.787857 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 48185 98.26% 98.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 51 0.10% 98.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 689 1.40% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 22 0.04% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 39 0.08% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 29 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 49040 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -2103778220 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -2103778220 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -2103778220 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 48650 99.20% 99.20% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 390 0.80% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 49040 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63786 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63786 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54155 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54155 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58620 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58620 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 122406 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 435405767 # ITB inst hits -system.cpu1.itb.inst_misses 63786 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 103195 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 400011912 # ITB inst hits +system.cpu1.itb.inst_misses 54155 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26334 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 39919 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23432 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 435469553 # ITB inst accesses -system.cpu1.itb.hits 435405767 # DTB hits -system.cpu1.itb.misses 63786 # DTB misses -system.cpu1.itb.accesses 435469553 # DTB accesses -system.cpu1.numCycles 95187488343 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 400066067 # ITB inst accesses +system.cpu1.itb.hits 400011912 # DTB hits +system.cpu1.itb.misses 54155 # DTB misses +system.cpu1.itb.accesses 400066067 # DTB accesses +system.cpu1.numCycles 95204836507 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14345 # number of quiesce instructions executed -system.cpu1.committedInsts 435108521 # Number of instructions committed -system.cpu1.committedOps 512619121 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 471360298 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 517037 # Number of float alu accesses -system.cpu1.num_func_calls 26310177 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66181606 # number of instructions that are conditional controls -system.cpu1.num_int_insts 471360298 # number of integer instructions -system.cpu1.num_fp_insts 517037 # number of float instructions -system.cpu1.num_int_register_reads 683625420 # number of times the integer registers were read -system.cpu1.num_int_register_writes 373659475 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 819092 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 470852 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 112718016 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 112414585 # number of times the CC registers were written -system.cpu1.num_mem_refs 156939308 # number of memory refs -system.cpu1.num_load_insts 82171340 # Number of load instructions -system.cpu1.num_store_insts 74767968 # Number of store instructions -system.cpu1.num_idle_cycles 94109373851.176025 # Number of idle cycles -system.cpu1.num_busy_cycles 1078114491.823977 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011326 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988674 # Percentage of idle cycles -system.cpu1.Branches 97258514 # Number of branches fetched +system.cpu1.kern.inst.quiesce 14080 # number of quiesce instructions executed +system.cpu1.committedInsts 399717589 # Number of instructions committed +system.cpu1.committedOps 471481802 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 433690793 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 447669 # Number of float alu accesses +system.cpu1.num_func_calls 24290810 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 60559296 # number of instructions that are conditional controls +system.cpu1.num_int_insts 433690793 # number of integer instructions +system.cpu1.num_fp_insts 447669 # number of float instructions +system.cpu1.num_int_register_reads 628918503 # number of times the integer registers were read +system.cpu1.num_int_register_writes 343906147 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 709471 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 405960 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102969972 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 102767338 # number of times the CC registers were written +system.cpu1.num_mem_refs 144547138 # number of memory refs +system.cpu1.num_load_insts 75521772 # Number of load instructions +system.cpu1.num_store_insts 69025366 # Number of store instructions +system.cpu1.num_idle_cycles 94207572529.552017 # Number of idle cycles +system.cpu1.num_busy_cycles 997263977.447979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010475 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989525 # Percentage of idle cycles +system.cpu1.Branches 89155171 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 354775953 69.17% 69.17% # Class of executed instruction -system.cpu1.op_class::IntMult 1066461 0.21% 69.38% # Class of executed instruction -system.cpu1.op_class::IntDiv 59336 0.01% 69.39% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.39% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 75375 0.01% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu1.op_class::MemRead 82171340 16.02% 85.42% # Class of executed instruction -system.cpu1.op_class::MemWrite 74767968 14.58% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 326125112 69.13% 69.13% # Class of executed instruction +system.cpu1.op_class::IntMult 978063 0.21% 69.33% # Class of executed instruction +system.cpu1.op_class::IntDiv 57214 0.01% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 68664 0.01% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.36% # Class of executed instruction +system.cpu1.op_class::MemRead 75521772 16.01% 85.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 69025366 14.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 512916476 # Class of executed instruction -system.cpu1.dcache.tags.replacements 5113111 # number of replacements -system.cpu1.dcache.tags.tagsinuse 443.711015 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 151630595 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5113623 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.652283 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.711015 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.866623 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.866623 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 319002554 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 319002554 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 76632055 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 76632055 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 70902064 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 70902064 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183506 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 183506 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 192465 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 192465 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1673719 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1673719 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1647145 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1647145 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 147534119 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 147534119 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 147717625 # number of overall hits -system.cpu1.dcache.overall_hits::total 147717625 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2895739 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2895739 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1291835 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1291835 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 599128 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 599128 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 515597 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 515597 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170116 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170116 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195350 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 195350 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4187574 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4187574 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4786702 # number of overall misses -system.cpu1.dcache.overall_misses::total 4786702 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44430252500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 44430252500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 29275459500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 29275459500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21176769000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 21176769000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2717509500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2717509500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5539928000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5539928000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5730000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5730000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 73705712000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 73705712000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 73705712000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 73705712000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 79527794 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 79527794 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72193899 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72193899 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 782634 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 782634 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 708062 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 708062 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843835 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1843835 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1842495 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1842495 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 151721693 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 151721693 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 152504327 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 152504327 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036412 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036412 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017894 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.017894 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765528 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765528 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728181 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.728181 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092262 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092262 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106025 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106025 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027600 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027600 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031387 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031387 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.320824 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.320824 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22661.918511 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22661.918511 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41072.327806 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41072.327806 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.449787 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.449787 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28358.986435 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28358.986435 # average StoreCondReq miss latency +system.cpu1.op_class::total 471776234 # Class of executed instruction +system.cpu1.dcache.tags.replacements 4623789 # number of replacements +system.cpu1.dcache.tags.tagsinuse 430.899907 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 139725575 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4624300 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.215508 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8408408114000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.899907 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.841601 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.841601 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 293714645 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 293714645 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 70428619 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 70428619 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 65452147 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 65452147 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 175356 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 175356 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 181976 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 181976 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1569435 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1569435 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1531483 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1531483 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 135880766 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 135880766 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 136056122 # number of overall hits +system.cpu1.dcache.overall_hits::total 136056122 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2625513 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2625513 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1190956 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1190956 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 551150 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 551150 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 454381 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 454381 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150766 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 150766 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187526 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 187526 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 3816469 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 3816469 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4367619 # number of overall misses +system.cpu1.dcache.overall_misses::total 4367619 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39306904500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 39306904500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28030249500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 28030249500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20535959500 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 20535959500 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2343079000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2343079000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5222807000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 5222807000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5948500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5948500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67337154000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67337154000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67337154000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67337154000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 73054132 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 73054132 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 66643103 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 66643103 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 726506 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 726506 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 636357 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 636357 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1720201 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1720201 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1719009 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1719009 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 139697235 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 139697235 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 140423741 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 140423741 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035939 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035939 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017871 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.017871 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.758631 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.758631 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.714035 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.714035 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087644 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087644 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109090 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109090 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027320 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027320 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031103 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.031103 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14971.133070 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14971.133070 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23535.923661 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23535.923661 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45195.462618 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45195.462618 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15541.163127 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15541.163127 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27851.108646 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27851.108646 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17601.053020 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17601.053020 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15398.015586 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15398.015586 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17643.836227 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17643.836227 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15417.359893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15417.359893 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1717,158 +1731,157 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 5113111 # number of writebacks -system.cpu1.dcache.writebacks::total 5113111 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16657 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 16657 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46028 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46028 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 17059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 17059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 17059 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 17059 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879082 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2879082 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1291433 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1291433 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599128 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 599128 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 515597 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 515597 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 124088 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 124088 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195350 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 195350 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4170515 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4170515 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4769643 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4769643 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21793 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42209 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40268780500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40268780500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27960090500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27960090500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13604579000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13604579000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20661172000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20661172000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751690500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751690500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344637000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344637000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5671000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5671000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68228871000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 68228871000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81833450000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 81833450000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4030825000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4030825000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3797015500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3797015500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7827840500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7827840500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036202 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036202 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017888 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765528 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765528 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728181 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728181 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067299 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067299 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106025 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106025 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027488 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027488 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031275 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.031275 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.673704 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.673704 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21650.438312 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21650.438312 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22707.299609 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22707.299609 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40072.327806 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40072.327806 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14116.518116 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14116.518116 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27359.288457 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27359.288457 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4623789 # number of writebacks +system.cpu1.dcache.writebacks::total 4623789 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13826 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 13826 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 458 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 458 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43478 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43478 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 14284 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 14284 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 14284 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 14284 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2611687 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2611687 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1190498 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1190498 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 551150 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 551150 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454381 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 454381 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 107288 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 107288 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187526 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 187526 # number of StoreCondReq MSHR misses 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+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 35578565500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 35578565500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26805763500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26805763500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12511151000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12511151000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20081578500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20081578500 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1492978000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1492978000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5035346000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5035346000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5883500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5883500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62384329000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 62384329000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74895480000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 74895480000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4378993500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4378993500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4297960500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4297960500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8676954000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8676954000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035750 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035750 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017864 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017864 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758631 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.758631 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.714035 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.714035 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062369 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062369 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109090 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109090 # mshr miss rate for StoreCondReq accesses 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22700.083462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44195.462618 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44195.462618 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13915.610320 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13915.610320 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26851.455265 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26851.455265 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 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overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10807.859257 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10807.859257 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 804847209 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 804847209 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 395188527 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 395188527 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 395188527 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 395188527 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 395188527 # number of overall hits +system.cpu1.icache.overall_hits::total 395188527 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4823385 # 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number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 4822868 # number of writebacks +system.cpu1.icache.writebacks::total 4822868 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4823385 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 4823385 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 4823385 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 4823385 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 4823385 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 4823385 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of 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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10307.859257 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49817184000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 49817184000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49817184000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49817184000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49817184000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 49817184000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14655500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14655500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14655500 # number of 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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 40065.171060 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43785.328080 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31874.992652 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31874.992652 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19854.780249 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19854.780249 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 348566.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 348566.666667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44710.637580 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44710.637580 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32004.071508 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31158.050230 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31158.050230 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61513.666347 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61513.666347 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33588.698998 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36537.046190 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176944.775845 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176694.151486 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178460.692594 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178460.692594 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 177678.007060 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 177546.385784 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.221168 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33021.438953 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45228.472646 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31448.558621 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31448.558621 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19347.062525 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19347.062525 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 299777.777778 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 299777.777778 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45478.321421 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45478.321421 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32444.358530 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28974.177244 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28974.177244 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63336.932661 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63336.932661 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32620.144319 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31892.938497 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34345.747266 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32444.358530 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32683.006303 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45228.472646 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36217.034917 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173505.119595 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173288.263938 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177032.033665 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 177032.033665 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125731.818182 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 175237.518719 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 175122.924602 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 21257827 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10899393 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 1702072 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1701871 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 509534 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9349922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 20416 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 20416 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4305236 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 7031230 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 2216107 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 785182 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 389899 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353464 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 462412 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 19593534 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10054336 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1096 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 1611494 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1611307 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 187 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 454071 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 8632529 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 23288 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 23288 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 3935373 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6517651 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 2069350 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 732453 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 387389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344195 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 449127 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1157273 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1096575 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5153566 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4436249 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 522065 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 513183 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15459725 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16561050 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365076 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544187 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32930038 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 659580536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 633491086 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395488 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1977568 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1296444678 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5547167 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 16615326 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.116559 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.320932 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1061448 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1001075 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4823385 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4143057 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 462376 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 452130 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14469858 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15078885 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 308515 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 488328 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 30345586 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 617360632 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 574871104 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1172512 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1763528 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1195167776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5321649 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 15507476 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.118236 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.322925 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14678862 88.35% 88.35% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1936263 11.65% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 201 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 13674115 88.18% 88.18% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1833174 11.82% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 187 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 16615326 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 21053645498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15507476 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 19383363503 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 168856163 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 170060906 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7730459000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7235187500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7526670911 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 6851260042 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 190640499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 161951000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 296991000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 267887000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40402 # Transaction distribution -system.iobus.trans_dist::ReadResp 40402 # Transaction distribution -system.iobus.trans_dist::WriteReq 136652 # Transaction distribution -system.iobus.trans_dist::WriteResp 136652 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47834 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40445 # Transaction distribution +system.iobus.trans_dist::ReadResp 40445 # Transaction distribution +system.iobus.trans_dist::WriteReq 136989 # Transaction distribution +system.iobus.trans_dist::WriteResp 136989 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47854 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2360,15 +2375,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122768 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122996 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231792 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231792 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354108 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47854 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47874 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2379,23 +2394,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155875 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7339056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156011 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355520 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7355520 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497017 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37033500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7513617 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 37057000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2409,467 +2424,467 @@ system.iobus.reqLayer16.occupancy 13000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26450500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26714502 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565570401 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568759261 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92847000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92994000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147956000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148232000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115605 # number of replacements -system.iocache.tags.tagsinuse 11.294118 # Cycle average of tags in use -system.iocache.tags.total_refs 10 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115621 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000086 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9206098021000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.822126 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.471992 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.238883 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705882 # Average percentage of cache occupancy +system.iocache.tags.replacements 115885 # number of replacements +system.iocache.tags.tagsinuse 11.295009 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115901 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 9206049239000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.821414 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.473594 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.467100 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705938 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1041013 # Number of tag accesses -system.iocache.tags.data_accesses 1041013 # Number of data accesses -system.iocache.WriteLineReq_hits::realview.ide 5 # number of WriteLineReq hits -system.iocache.WriteLineReq_hits::total 5 # number of WriteLineReq hits +system.iocache.tags.tag_accesses 1043421 # Number of tag accesses +system.iocache.tags.data_accesses 1043421 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106723 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106723 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses -system.iocache.demand_misses::total 8942 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses +system.iocache.demand_misses::total 8952 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8902 # number of overall misses -system.iocache.overall_misses::total 8942 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1679170514 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1684370014 # number of ReadReq miss cycles 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(read+write) miss cycles -system.iocache.demand_miss_latency::total 1684739014 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1679170514 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1684739014 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13574924276 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13574924276 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5632500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1680350485 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1685982985 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5632500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1680350485 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1685982985 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses 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system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 188628.455853 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 188429.356080 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142256.756757 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188549.201638 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188357.803665 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130941.731276 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130941.731276 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 188407.404831 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 188407.404831 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 35755 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126887.424998 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126887.424998 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 188335.900916 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 140812.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 188549.201638 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 188335.900916 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33982 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3742 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3504 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.555051 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.698059 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106695 # number of writebacks -system.iocache.writebacks::total 106695 # number of writebacks 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WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234070514 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1237420014 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3413500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234750485 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1238163985 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638344387 # number of WriteLineReq MSHR miss cycles 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for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999953 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.999953 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138628.455853 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 138429.356080 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92256.756757 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138549.201638 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 138357.803665 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80941.731276 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80941.731276 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76826.417595 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76826.417595 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90812.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 138549.201638 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 138335.900916 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1201728 # number of replacements -system.l2c.tags.tagsinuse 62776.329461 # Cycle average of tags in use -system.l2c.tags.total_refs 5149298 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1259663 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.087838 # Average number of references to valid blocks. +system.l2c.tags.replacements 1212335 # number of replacements +system.l2c.tags.tagsinuse 62688.740428 # Cycle average of tags in use +system.l2c.tags.total_refs 5318857 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1271612 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.182767 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 23700.762045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 102.528322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 175.969290 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4011.755779 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5217.555279 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7227.978697 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.263944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 281.111554 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3722.000784 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8039.407020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10130.996747 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.361645 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001564 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.079614 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110290 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056793 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.122672 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.154587 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.957891 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 9737 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 265 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 47933 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 277 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9401 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5230 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 40901 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.148575 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004044 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.731400 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66235328 # Number of tag accesses -system.l2c.tags.data_accesses 66235328 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 2474359 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2474359 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 150616 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 127305 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 277921 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 34718 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 37539 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72257 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 146279 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 167990 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 314269 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4627 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3559 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 390104 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 513889 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 259608 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5392 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4493 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 410490 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 516454 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 291033 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2399649 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4627 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 390104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 660168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 259608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5392 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4493 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 410490 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 684444 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 291033 # number of demand (read+write) hits -system.l2c.demand_hits::total 2713918 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4627 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3559 # number of overall hits -system.l2c.overall_hits::cpu0.inst 390104 # number of overall hits -system.l2c.overall_hits::cpu0.data 660168 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 259608 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5392 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4493 # number of overall hits -system.l2c.overall_hits::cpu1.inst 410490 # number of overall hits -system.l2c.overall_hits::cpu1.data 684444 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 291033 # number of overall hits -system.l2c.overall_hits::total 2713918 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 62469 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 57486 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 119955 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 13684 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 12909 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 26593 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 477377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 148178 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 625555 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1066 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 45695 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 111052 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1684 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 40203 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 92070 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 640180 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1085 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1066 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 45695 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 588429 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1546 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1684 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 40203 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 240248 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) misses -system.l2c.demand_misses::total 1265735 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1085 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1066 # number of overall misses -system.l2c.overall_misses::cpu0.inst 45695 # number of overall misses -system.l2c.overall_misses::cpu0.data 588429 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 202654 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1546 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1684 # number of overall misses -system.l2c.overall_misses::cpu1.inst 40203 # number of overall misses -system.l2c.overall_misses::cpu1.data 240248 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 143125 # number of overall misses -system.l2c.overall_misses::total 1265735 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 928670500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1025251000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1953921500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 178207000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182538500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 360745500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 63116930500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 19400961500 # number of ReadExReq miss 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ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 96202750409 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 153728000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149604000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 6143069000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 78366838000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 212651500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 233752000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 5417778000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 32123178000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 178720642409 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 153728000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149604000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 6143069000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 78366838000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 212651500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 233752000 # number of overall miss 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number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6177 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 450693 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 924692 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 434158 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3979653 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.293165 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311087 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.301488 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.282716 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.255887 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.269024 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.765449 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468669 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.665609 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.177657 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151263 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210512 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.317987 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.317987 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73691.983224 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73479.812476 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73590.304698 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76632.527039 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76541.211558 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76588.199902 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122216.111166 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120930.107708 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 121911.489797 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127327.340689 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128180.440427 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140288.519066 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.278346 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.324769 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.297932 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.262730 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.248795 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.256392 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.739638 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468756 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.650315 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.191362 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.131286 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.208450 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.451765 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.254629 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.313124 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.235211 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.291843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.099553 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.451765 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.409397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.166368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.185930 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091785 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.254629 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.344750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.313124 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70983.253951 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70664.365748 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70836.596675 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73879.657228 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73723.546561 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73810.759158 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122124.893100 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120848.037179 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 121821.399319 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126986.191240 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128708.397674 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140079.123882 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123206.068345 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123419.535342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 131096.531077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126166.268307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128408.408686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124606.775532 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123206.068345 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 150872.877032 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128893.722870 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131836.766547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124366.696672 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123419.535342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153135.988396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 131096.531077 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 147000.358295 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158957.895461 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131977.137651 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148142.002449 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161445.067594 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155217.746978 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146409.886006 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155515.816633 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131303.061689 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144246.646804 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160019.263397 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153661.782662 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147591.274414 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160160.968560 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 139401.382370 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145302.455709 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107722.727273 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157727.976102 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 138490.550103 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 81772 # Transaction distribution -system.membus.trans_dist::ReadResp 730632 # Transaction distribution -system.membus.trans_dist::WriteReq 38384 # Transaction distribution -system.membus.trans_dist::WriteResp 38384 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1075989 # Transaction distribution -system.membus.trans_dist::CleanEvict 189758 # Transaction distribution -system.membus.trans_dist::UpgradeReq 405662 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 313696 # Transaction distribution -system.membus.trans_dist::UpgradeResp 154281 # Transaction distribution -system.membus.trans_dist::ReadExReq 640388 # Transaction distribution -system.membus.trans_dist::ReadExResp 617827 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 648860 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106721 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106721 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122768 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 82348 # Transaction distribution +system.membus.trans_dist::ReadResp 741199 # Transaction distribution +system.membus.trans_dist::WriteReq 39013 # Transaction distribution +system.membus.trans_dist::WriteResp 39013 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1081398 # Transaction distribution +system.membus.trans_dist::CleanEvict 196468 # Transaction distribution +system.membus.trans_dist::UpgradeReq 401198 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 306316 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 643986 # Transaction distribution +system.membus.trans_dist::ReadExResp 621414 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 658851 # Transaction distribution +system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122996 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4655021 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4803735 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5146104 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155875 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4525576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4676700 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4915252 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156011 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51708 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142678316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 142886103 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7257472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 150143575 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 590609 # Total snoops (count) -system.membus.snoop_fanout::samples 3503595 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143876076 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 144088363 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7276096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 151364459 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 576558 # Total snoops (count) +system.membus.snoop_fanout::samples 3516604 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3503595 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3516604 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3503595 # Request fanout histogram -system.membus.reqLayer0.occupancy 101306500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3516604 # Request fanout histogram +system.membus.reqLayer0.occupancy 101595998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21492499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 23093498 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 7402591959 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 7460114319 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7154332547 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6921315949 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 228436684 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45614101 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3213,52 +3227,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 10356989 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5641244 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1705825 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 115755 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 104698 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 11057 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 81774 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3879147 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38384 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38384 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3550378 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1245199 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 675855 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 385953 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1061806 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1071844 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1071844 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 3804622 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 106721 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7596632 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6529428 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14126060 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 228502049 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185064310 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 413566359 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2887820 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7482662 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.359179 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.482830 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 10579543 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5766836 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1724769 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 116961 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 105875 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 11086 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 82350 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3947474 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 39013 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 39013 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3635231 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2252852 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 680846 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 382953 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1063799 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 141 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 141 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1092357 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1092357 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3872368 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8825237 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6597118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15422355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252378371 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 173059496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 425437867 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2867232 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7585274 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.353752 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.481180 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4806103 64.23% 64.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2665502 35.62% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 11057 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4913057 64.77% 64.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2661131 35.08% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 11086 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7482662 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8118734038 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7585274 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8312830316 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2606433 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2630923 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4223747952 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4557123754 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3725557524 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3526163360 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index b27222f80..f5f82f47e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811415 # Number of seconds simulated -sim_ticks 51811415265500 # Number of ticks simulated -final_tick 51811415265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.811400 # Number of seconds simulated +sim_ticks 51811399994500 # Number of ticks simulated +final_tick 51811399994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 625298 # Simulator instruction rate (inst/s) -host_op_rate 734839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39084409400 # Simulator tick rate (ticks/s) -host_mem_usage 677180 # Number of bytes of host memory used -host_seconds 1325.63 # Real time elapsed on the host -sim_insts 828913449 # Number of instructions simulated -sim_ops 974124045 # Number of ops (including micro ops) simulated +host_inst_rate 805770 # Simulator instruction rate (inst/s) +host_op_rate 946938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50389185573 # Simulator tick rate (ticks/s) +host_mem_usage 678984 # Number of bytes of host memory used +host_seconds 1028.22 # Real time elapsed on the host +sim_insts 828512987 # Number of instructions simulated +sim_ops 973664549 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 133696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 141376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4656308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65123848 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401856 # Number of bytes read from this memory -system.physmem.bytes_read::total 70457084 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4656308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4656308 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61286080 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 141952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4623732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65034376 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 398080 # Number of bytes read from this memory +system.physmem.bytes_read::total 70331708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4623732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4623732 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61230400 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 61306660 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 113162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1017573 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6279 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1141312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 957595 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61250980 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 112653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1016175 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1139353 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 956725 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 960168 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 2729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 89870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1256940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1359876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1182868 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 959298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 2740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 89242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1255214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1357456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1181794 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1183265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1182868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 2729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1257337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2543141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1141312 # Number of read requests accepted -system.physmem.writeReqs 960168 # Number of write requests accepted -system.physmem.readBursts 1141312 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 960168 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72995200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48768 # Total number of bytes read from write queue -system.physmem.bytesWritten 61305216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70457084 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 61306660 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 762 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 295918 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70676 # Per bank write bursts -system.physmem.perBankRdBursts::1 76921 # Per bank write bursts -system.physmem.perBankRdBursts::2 71652 # Per bank write bursts -system.physmem.perBankRdBursts::3 67938 # Per bank write bursts -system.physmem.perBankRdBursts::4 64385 # Per bank write bursts -system.physmem.perBankRdBursts::5 70205 # Per bank write bursts -system.physmem.perBankRdBursts::6 66024 # Per bank write bursts -system.physmem.perBankRdBursts::7 63727 # Per bank write bursts -system.physmem.perBankRdBursts::8 65795 # Per bank write bursts -system.physmem.perBankRdBursts::9 109889 # Per bank write bursts -system.physmem.perBankRdBursts::10 68785 # Per bank write bursts -system.physmem.perBankRdBursts::11 70022 # Per bank write bursts -system.physmem.perBankRdBursts::12 67859 # Per bank write bursts -system.physmem.perBankRdBursts::13 71968 # Per bank write bursts -system.physmem.perBankRdBursts::14 68874 # Per bank write bursts -system.physmem.perBankRdBursts::15 65830 # Per bank write bursts -system.physmem.perBankWrBursts::0 58715 # Per bank write bursts -system.physmem.perBankWrBursts::1 63168 # Per bank write bursts -system.physmem.perBankWrBursts::2 61317 # Per bank write bursts -system.physmem.perBankWrBursts::3 60411 # Per bank write bursts -system.physmem.perBankWrBursts::4 56741 # Per bank write bursts -system.physmem.perBankWrBursts::5 60657 # Per bank write bursts -system.physmem.perBankWrBursts::6 57878 # Per bank write bursts -system.physmem.perBankWrBursts::7 57357 # Per bank write bursts -system.physmem.perBankWrBursts::8 58434 # Per bank write bursts -system.physmem.perBankWrBursts::9 60882 # Per bank write bursts -system.physmem.perBankWrBursts::10 59842 # Per bank write bursts -system.physmem.perBankWrBursts::11 61839 # Per bank write bursts -system.physmem.perBankWrBursts::12 59187 # Per bank write bursts -system.physmem.perBankWrBursts::13 62791 # Per bank write bursts -system.physmem.perBankWrBursts::14 60690 # Per bank write bursts -system.physmem.perBankWrBursts::15 57985 # Per bank write bursts +system.physmem.bw_write::total 1182191 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1181794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 2740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1255611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2539647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1139353 # Number of read requests accepted +system.physmem.writeReqs 959298 # Number of write requests accepted +system.physmem.readBursts 1139353 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 959298 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72868032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 50560 # Total number of bytes read from write queue +system.physmem.bytesWritten 61249856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70331708 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 61250980 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 790 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69574 # Per bank write bursts +system.physmem.perBankRdBursts::1 73483 # Per bank write bursts +system.physmem.perBankRdBursts::2 70905 # Per bank write bursts +system.physmem.perBankRdBursts::3 67568 # Per bank write bursts +system.physmem.perBankRdBursts::4 64326 # Per bank write bursts +system.physmem.perBankRdBursts::5 70688 # Per bank write bursts +system.physmem.perBankRdBursts::6 65575 # Per bank write bursts +system.physmem.perBankRdBursts::7 64409 # Per bank write bursts +system.physmem.perBankRdBursts::8 65562 # Per bank write bursts +system.physmem.perBankRdBursts::9 110058 # Per bank write bursts +system.physmem.perBankRdBursts::10 69387 # Per bank write bursts +system.physmem.perBankRdBursts::11 70852 # Per bank write bursts +system.physmem.perBankRdBursts::12 67727 # Per bank write bursts +system.physmem.perBankRdBursts::13 71395 # Per bank write bursts +system.physmem.perBankRdBursts::14 70177 # Per bank write bursts +system.physmem.perBankRdBursts::15 66877 # Per bank write bursts +system.physmem.perBankWrBursts::0 57914 # Per bank write bursts +system.physmem.perBankWrBursts::1 61200 # Per bank write bursts +system.physmem.perBankWrBursts::2 60974 # Per bank write bursts +system.physmem.perBankWrBursts::3 59703 # Per bank write bursts +system.physmem.perBankWrBursts::4 56782 # Per bank write bursts +system.physmem.perBankWrBursts::5 61096 # Per bank write bursts +system.physmem.perBankWrBursts::6 57709 # Per bank write bursts +system.physmem.perBankWrBursts::7 57516 # Per bank write bursts +system.physmem.perBankWrBursts::8 58389 # Per bank write bursts +system.physmem.perBankWrBursts::9 61168 # Per bank write bursts +system.physmem.perBankWrBursts::10 60736 # Per bank write bursts +system.physmem.perBankWrBursts::11 62143 # Per bank write bursts +system.physmem.perBankWrBursts::12 59319 # Per bank write bursts +system.physmem.perBankWrBursts::13 62705 # Per bank write bursts +system.physmem.perBankWrBursts::14 61087 # Per bank write bursts +system.physmem.perBankWrBursts::15 58588 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 35 # Number of times write queue was full causing retry -system.physmem.totGap 51811412436500 # Total gap between requests +system.physmem.numWrRetry 61 # Number of times write queue was full causing retry +system.physmem.totGap 51811397057500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1098196 # Read request sizes (log2) +system.physmem.readPktSize::6 1096237 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 957595 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1113641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 956725 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,117 +159,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 56655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 57800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 58177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 63114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 58508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 57924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 55949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 55254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 54682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 451440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.492681 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.675079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.019607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 180783 40.05% 40.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 110069 24.38% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39371 8.72% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22726 5.03% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15993 3.54% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11772 2.61% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9986 2.21% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8783 1.95% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51957 11.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 451440 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 53917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.153458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.779025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 53915 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 13396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57047 # What write queue length does an incoming req see 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write queue length does an incoming req see +system.physmem.wrQLenPdf::32 56000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 450226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.889433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.979745 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.177331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 179632 39.90% 39.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 110318 24.50% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39188 8.70% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22734 5.05% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15887 3.53% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11846 2.63% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9963 2.21% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8722 1.94% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51936 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 450226 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 53627 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.230425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 337.691151 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 53625 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 53917 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 53917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.766085 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.131013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.603955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51657 95.81% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 251 0.47% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 85 0.16% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 305 0.57% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 0.11% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 347 0.64% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 210 0.39% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.03% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 56 0.10% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 148 0.27% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 23 0.04% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 456 0.85% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 32 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 152 0.28% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 53627 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 53627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.846029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.135395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.325860 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51578 96.18% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 290 0.54% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 64 0.12% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 105 0.20% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 36 0.07% 97.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 101 0.19% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 231 0.43% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.05% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 324 0.60% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 70 0.13% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.05% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 55 0.10% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 281 0.52% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 24 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 150 0.28% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 183 0.34% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 53917 # Writes before turning the bus around for reads -system.physmem.totQLat 14358242809 # Total ticks spent queuing -system.physmem.totMemAccLat 35743555309 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5702750000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12588.88 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 16 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 53627 # Writes before turning the bus around for reads +system.physmem.totQLat 14356871098 # Total ticks spent queuing +system.physmem.totMemAccLat 35704927348 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5692815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12609.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31338.88 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31359.64 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s @@ -279,40 +285,40 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing -system.physmem.readRowHits 919470 # Number of row buffer hits during reads -system.physmem.writeRowHits 727533 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 24654725.45 # Average gap between requests -system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1712392920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 934341375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4301879400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3086061120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1295992039365 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29950012638750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34640108967570 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.580666 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49823953491004 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730096940000 # Time in different power states +system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing +system.physmem.readRowHits 917761 # Number of row buffer hits during reads +system.physmem.writeRowHits 727604 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.03 # Row buffer hit rate for writes +system.physmem.avgGap 24687952.91 # Average gap between requests +system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1698338880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 926673000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4262879400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3064353120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1294076187855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951683866750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34639780896525 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.574535 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49826749097915 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730096420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 257364177996 # Time in different power states +system.physmem_0.memoryStateTime::ACT 254553819585 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1700493480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 927848625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4594371600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3121092000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1294725453480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29951123679000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34640262552825 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.583630 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49825763906946 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730096940000 # Time in different power states +system.physmem_1.actEnergy 1705369680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 930509250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4617873000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3137194800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1296366805530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29949674553000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34640500902780 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.588432 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49823352477739 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730096420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 255552101804 # Time in different power states +system.physmem_1.memoryStateTime::ACT 257948478511 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -366,71 +372,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 185222 # Table walker walks requested -system.cpu.dtb.walker.walksLong 185222 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12899 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144060 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 185205 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.215977 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.785904 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 185203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 185086 # Table walker walks requested +system.cpu.dtb.walker.walksLong 185086 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12788 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144037 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 185071 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.216133 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.811526 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 185069 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 185205 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 156976 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24757.998038 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20851.674753 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17681.260030 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 155823 99.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1006 0.64% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 72 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 185071 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 156840 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24753.656593 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20840.255945 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17740.873102 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 155696 99.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 981 0.63% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 36 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 156976 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 3935879148 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.602257 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489432 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1565466704 39.77% 39.77% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 2370412444 60.23% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 3935879148 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 144061 91.78% 91.78% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12899 8.22% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 156960 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 156840 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -374556148 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 5.053125 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1518122704 -405.31% -405.31% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -1892678852 505.31% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -374556148 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 144038 91.85% 91.85% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12788 8.15% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 156826 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185086 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185222 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156960 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185086 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156826 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156960 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 342182 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156826 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 341912 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 156096920 # DTB read hits -system.cpu.dtb.read_misses 137670 # DTB read misses -system.cpu.dtb.write_hits 141678029 # DTB write hits -system.cpu.dtb.write_misses 47552 # DTB write misses +system.cpu.dtb.read_hits 156026006 # DTB read hits +system.cpu.dtb.read_misses 137641 # DTB read misses +system.cpu.dtb.write_hits 141600690 # DTB write hits +system.cpu.dtb.write_misses 47445 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70722 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 70612 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6537 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 156234590 # DTB read accesses -system.cpu.dtb.write_accesses 141725581 # DTB write accesses +system.cpu.dtb.read_accesses 156163647 # DTB read accesses +system.cpu.dtb.write_accesses 141648135 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 297774949 # DTB hits -system.cpu.dtb.misses 185222 # DTB misses -system.cpu.dtb.accesses 297960171 # DTB accesses +system.cpu.dtb.hits 297626696 # DTB hits +system.cpu.dtb.misses 185086 # DTB misses +system.cpu.dtb.accesses 297811782 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,44 +465,42 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 118503 # Table walker walks requested -system.cpu.itb.walker.walksLong 118503 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walks 118473 # Table walker walks requested +system.cpu.itb.walker.walksLong 118473 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107075 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 118503 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 118503 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 118503 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108185 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28674.682257 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24804.583165 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21241.542539 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 106795 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1213 1.12% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 69 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 33 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108185 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107045 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 118473 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 118473 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 118473 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108155 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28668.184550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24838.617630 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 20892.143337 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 106773 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1223 1.13% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 21 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 63 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 24 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 37 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108155 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107075 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107045 98.97% 98.97% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108185 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108155 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118503 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 118503 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118473 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 118473 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108185 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108185 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 226688 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 829424054 # ITB inst hits -system.cpu.itb.inst_misses 118503 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108155 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108155 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 226628 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829023400 # ITB inst hits +system.cpu.itb.inst_misses 118473 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -506,48 +509,48 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50494 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 50418 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 829542557 # ITB inst accesses -system.cpu.itb.hits 829424054 # DTB hits -system.cpu.itb.misses 118503 # DTB misses -system.cpu.itb.accesses 829542557 # DTB accesses -system.cpu.numCycles 103622830531 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 829141873 # ITB inst accesses +system.cpu.itb.hits 829023400 # DTB hits +system.cpu.itb.misses 118473 # DTB misses +system.cpu.itb.accesses 829141873 # DTB accesses +system.cpu.numCycles 103622799989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed -system.cpu.committedInsts 828913449 # Number of instructions committed -system.cpu.committedOps 974124045 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 895594684 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899411 # Number of float alu accesses -system.cpu.num_func_calls 49818288 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 125653589 # number of instructions that are conditional controls -system.cpu.num_int_insts 895594684 # number of integer instructions -system.cpu.num_fp_insts 899411 # number of float instructions -system.cpu.num_int_register_reads 1295586183 # number of times the integer registers were read -system.cpu.num_int_register_writes 709722189 # number of times the integer registers were written +system.cpu.kern.inst.quiesce 15972 # number of quiesce instructions executed +system.cpu.committedInsts 828512987 # Number of instructions committed +system.cpu.committedOps 973664549 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 895161313 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 899443 # Number of float alu accesses +system.cpu.num_func_calls 49782138 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 125600972 # number of instructions that are conditional controls +system.cpu.num_int_insts 895161313 # number of integer instructions +system.cpu.num_fp_insts 899443 # number of float instructions +system.cpu.num_int_register_reads 1295047006 # number of times the integer registers were read +system.cpu.num_int_register_writes 709396185 # number of times the integer registers were written system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read -system.cpu.num_fp_register_writes 757584 # number of times the floating registers were written -system.cpu.num_cc_register_reads 214510161 # number of times the CC registers were read -system.cpu.num_cc_register_writes 213901888 # number of times the CC registers were written -system.cpu.num_mem_refs 297752944 # number of memory refs -system.cpu.num_load_insts 156086585 # Number of load instructions -system.cpu.num_store_insts 141666359 # Number of store instructions -system.cpu.num_idle_cycles 100538909625.142059 # Number of idle cycles -system.cpu.num_busy_cycles 3083920905.857941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029761 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970239 # Percentage of idle cycles -system.cpu.Branches 184946450 # Number of branches fetched +system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written +system.cpu.num_cc_register_reads 214441530 # number of times the CC registers were read +system.cpu.num_cc_register_writes 213833710 # number of times the CC registers were written +system.cpu.num_mem_refs 297604519 # number of memory refs +system.cpu.num_load_insts 156015499 # Number of load instructions +system.cpu.num_store_insts 141589020 # Number of store instructions +system.cpu.num_idle_cycles 100541051528.316055 # Number of idle cycles +system.cpu.num_busy_cycles 3081748460.683940 # Number of busy cycles +system.cpu.not_idle_fraction 0.029740 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970260 # Percentage of idle cycles +system.cpu.Branches 184855625 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 674595310 69.21% 69.21% # Class of executed instruction -system.cpu.op_class::IntMult 2119774 0.22% 69.43% # Class of executed instruction -system.cpu.op_class::IntDiv 97321 0.01% 69.44% # Class of executed instruction +system.cpu.op_class::IntAlu 674284702 69.21% 69.21% # Class of executed instruction +system.cpu.op_class::IntMult 2119126 0.22% 69.43% # Class of executed instruction +system.cpu.op_class::IntDiv 97314 0.01% 69.44% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction @@ -574,120 +577,120 @@ system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::MemRead 156086585 16.01% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 141666359 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 156015499 16.01% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 141589020 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 974677774 # Class of executed instruction -system.cpu.dcache.tags.replacements 9257096 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.942792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288320002 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9257608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.144114 # Average number of references to valid blocks. +system.cpu.op_class::total 974218086 # Class of executed instruction +system.cpu.dcache.tags.replacements 9250712 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.942785 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288177954 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9251224 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.150251 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.942792 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.942785 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1200023494 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1200023494 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146178724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146178724 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 134536913 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 134536913 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 373150 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 373150 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333652 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333652 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286715 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3286715 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3569347 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3569347 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 280715637 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 280715637 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 281088787 # number of overall hits -system.cpu.dcache.overall_hits::total 281088787 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4832437 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4832437 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1969504 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1969504 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1107960 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1107960 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1218811 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1218811 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 284252 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 284252 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 6801941 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6801941 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7909901 # number of overall misses -system.cpu.dcache.overall_misses::total 7909901 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82966383500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82966383500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66911897500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66911897500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73402202000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 73402202000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4352844000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4352844000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 248500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 248500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149878281000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149878281000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149878281000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149878281000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 151011161 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 151011161 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 136506417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 136506417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481110 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1481110 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552463 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1552463 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570967 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3570967 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3569350 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3569350 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 287517578 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 287517578 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 288998688 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 288998688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014428 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014428 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748061 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.748061 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785082 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785082 # miss rate for WriteLineReq accesses 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(read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031981 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.031981 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014426 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014426 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748088 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.748088 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785220 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785220 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079559 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079559 # miss rate for LoadLockedReq accesses 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miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15286.789636 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22015.390612 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22015.390612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18928.327010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18928.327010 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,154 +699,154 @@ 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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161480323000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161480323000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199653000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199653000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217623500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217623500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417276500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417276500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746887 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746887 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785220 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785220 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060619 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060619 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023502 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023502 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15966.200087 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15966.200087 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32839.707505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32839.707505 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18954.098790 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18954.098790 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59224.433485 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59224.433485 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13766.935863 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13766.935863 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81833.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81833.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20831.002673 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20831.002673 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20566.973180 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20566.973180 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183957.776987 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.776987 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.966180 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.966180 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184206.393710 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184206.393710 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023491 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023491 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027201 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15964.950470 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15964.950470 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32772.321750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32772.321750 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18964.116647 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.116647 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59158.309455 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59158.309455 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13728.343491 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13728.343491 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20812.092609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20812.092609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20551.852406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20551.852406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.047178 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.047178 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.426012 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.426012 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.258864 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.258864 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13398086 # number of replacements +system.cpu.icache.tags.replacements 13387387 # number of replacements system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816025451 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13398598 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.903794 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 815635496 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13387899 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.923338 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id 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13398603 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13398603 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13398603 # number of overall misses -system.cpu.icache.overall_misses::total 13398603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182979269500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182979269500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182979269500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182979269500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182979269500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182979269500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 829424054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 829424054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 829424054 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 829424054 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 829424054 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 829424054 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016154 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016154 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016154 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016154 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016154 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016154 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13656.593116 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13656.593116 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13656.593116 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13656.593116 # average overall miss latency +system.cpu.icache.tags.tag_accesses 842411304 # Number of tag accesses +system.cpu.icache.tags.data_accesses 842411304 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 815635496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 815635496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 815635496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 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0.016149 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016149 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016149 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016149 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016149 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13652.955347 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13652.955347 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13652.955347 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13652.955347 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13652.955347 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13652.955347 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -852,231 +855,231 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 13398086 # number of writebacks -system.cpu.icache.writebacks::total 13398086 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13398603 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13398603 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13398603 # number of demand (read+write) MSHR misses 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system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169580666500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 169580666500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169580666500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 169580666500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169580666500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 169580666500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169396551500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 169396551500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169396551500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 169396551500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169396551500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 169396551500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # 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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12656.593116 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12656.593116 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12656.593116 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12656.593116 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016149 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016149 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016149 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12652.955347 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12652.955347 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1001888 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65194.742933 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 41566827 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1063831 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 39.072773 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 999968 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65207.127423 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 41555308 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1062213 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 39.121446 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 56076472500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37699.189777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 214.416551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 325.189859 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8460.753962 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 18495.192784 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575244 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003272 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.004962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.129101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.282214 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994793 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 190 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61753 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 37737.548410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 210.383401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 313.931857 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8489.634618 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 18455.629136 # Average occupied blocks per requestor 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per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2436 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53334 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.002899 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942276 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 371499011 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 371499011 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309547 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 241826 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 551373 # number of ReadReq hits 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ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 738219 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 738219 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 309547 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 241826 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13328529 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7500633 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 21380535 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 309547 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 241826 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13328529 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7500633 # number of overall hits -system.cpu.l2cache.overall_hits::total 21380535 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2089 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2209 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4298 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 32700 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 32700 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 317418 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 317418 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 70074 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 70074 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 220760 # number of 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65598436500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 74713153500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 263148500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 283510500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8568058000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65598436500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 74713153500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 262755500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 280620500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 543376000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2212537500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2212537500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 38353068500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 38353068500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8512201000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8512201000 # number of ReadCleanReq MSHR miss cycles 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 262755500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 280620500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8512201000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65515058000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 74570635000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777666500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675391000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829955000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829955000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777574500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5829970500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5829970500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607621500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505346000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787990 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787990 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607545000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505269500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.007749 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786413 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786413 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166475 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166475 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005230 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036001 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036001 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394312 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394312 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066947 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.027852 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006703 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009052 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005230 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066947 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.027852 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127189.157748 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70683.669725 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70683.669725 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70333.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70333.333333 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121018.798556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121018.798556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122271.570055 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122271.570055 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123142.288005 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123142.288005 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120264.067026 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120264.067026 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122271.570055 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121889.851499 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 121970.701984 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125968.645285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128343.368040 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122271.570055 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121889.851499 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 121970.701984 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166206 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005196 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036011 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036011 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393790 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393790 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.027813 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.027813 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126219.744483 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67946.365507 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67946.365507 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121102.587946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121102.587946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122363.271760 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122363.271760 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123109.369405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123109.369405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120254.867813 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120254.867813 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171433.935671 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138953.636091 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.639848 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.639848 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171431.205863 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.438596 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172955.099680 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172955.099680 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172194.355437 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149322.350387 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.220590 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.658298 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 45828995 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23172776 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2709 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2709 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 45794965 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23155820 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2699 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2699 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 972528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20504109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 972147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20487667 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8210793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13396481 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2163559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 41501 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 41504 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1906703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1906703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13398603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6140983 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1325475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1218811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40279937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27990886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853214 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69722195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715057876 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978932526 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1952280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2493088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2698435770 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1573850 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24936909 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019271 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137475 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8203050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13387387 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2163174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 41410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 41412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1905461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1905461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13387904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6135636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1325691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1219027 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40249445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27971705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598323 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 852523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69671996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1713791124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978068334 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1954320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2489888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2696303666 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1571708 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 24917471 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019294 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.137557 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24456353 98.07% 98.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 480556 1.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24436707 98.07% 98.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 480764 1.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24936909 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43847676000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 24917471 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43812763500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1611389 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1591387 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20141029500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20124981000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12738944468 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12729124462 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 354123000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 354033000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 541578000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 541287000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40323 # Transaction distribution -system.iobus.trans_dist::ReadResp 40323 # Transaction distribution +system.iobus.trans_dist::ReadReq 40324 # Transaction distribution +system.iobus.trans_dist::ReadResp 40324 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1286,11 +1289,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1305,12 +1308,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42147000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1332,73 +1335,73 @@ system.iobus.reqLayer16.occupancy 16500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25743500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25712000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565463411 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566837671 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115483 # number of replacements -system.iocache.tags.tagsinuse 10.446937 # Cycle average of tags in use +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.446945 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183709784000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511467 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935470 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219467 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433467 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183709781000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511462 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935482 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433468 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039875 # Number of tag accesses -system.iocache.tags.data_accesses 1039875 # Number of data accesses +system.iocache.tags.tag_accesses 1039884 # Number of tag accesses +system.iocache.tags.data_accesses 1039884 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses -system.iocache.demand_misses::total 8878 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses +system.iocache.demand_misses::total 8879 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8838 # number of overall misses -system.iocache.overall_misses::total 8878 # number of overall misses +system.iocache.overall_misses::realview.ide 8839 # number of overall misses +system.iocache.overall_misses::total 8879 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1645846130 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1650916630 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1648554138 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1653624638 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13863091781 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13863091781 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13411902033 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13411902033 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1645846130 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1651267630 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1648554138 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1653975638 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1645846130 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1651267630 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1648554138 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1653975638 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1413,54 +1416,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186223.821000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186018.775211 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186509.122978 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186302.910996 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129969.734690 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129969.734690 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.725053 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125739.725053 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185995.452805 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186279.495213 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185995.452805 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33963 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186279.495213 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32796 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3509 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3360 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.678826 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.760714 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203946130 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1207166630 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206604138 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1209824638 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8529891781 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8529891781 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073565122 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8073565122 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1203946130 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1207367630 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1206604138 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1210025638 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1203946130 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1207367630 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1206604138 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1210025638 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1475,72 +1478,71 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136223.821000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136018.775211 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136509.122978 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136302.910996 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79969.734690 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79969.734690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.565308 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.565308 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 380834 # Transaction distribution +system.membus.trans_dist::ReadResp 380206 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 957595 # Transaction distribution -system.membus.trans_dist::CleanEvict 155985 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33274 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33277 # Transaction distribution -system.membus.trans_dist::ReadExReq 797439 # Transaction distribution -system.membus.trans_dist::ReadExResp 797439 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 304007 # Transaction distribution +system.membus.trans_dist::WritebackDirty 956725 # Transaction distribution +system.membus.trans_dist::CleanEvict 157718 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33138 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 796168 # Transaction distribution +system.membus.trans_dist::ReadExResp 796168 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 303379 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3343278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3472970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3814166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3304162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3433854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3671101 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124537568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124707394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7226176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131933570 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3258 # Total snoops (count) -system.membus.snoop_fanout::samples 2468309 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124360288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124530114 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7222400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7222400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131752514 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3318 # Total snoops (count) +system.membus.snoop_fanout::samples 2464390 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2468309 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2464390 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2468309 # Request fanout histogram -system.membus.reqLayer0.occupancy 106920500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2464390 # Request fanout histogram +system.membus.reqLayer0.occupancy 106890000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5785500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5800500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6298398949 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6292280855 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6051404500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5974901047 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227572547 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44724954 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index c8bf2f829..e3f33ed21 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111153 # Number of seconds simulated -sim_ticks 51111152682000 # Number of ticks simulated -final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111167 # Number of seconds simulated +sim_ticks 51111167216500 # Number of ticks simulated +final_tick 51111167216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 965225 # Simulator instruction rate (inst/s) -host_op_rate 1134298 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50106889543 # Simulator tick rate (ticks/s) -host_mem_usage 675900 # Number of bytes of host memory used -host_seconds 1020.04 # Real time elapsed on the host -sim_insts 984570519 # Number of instructions simulated -sim_ops 1157031967 # Number of ops (including micro ops) simulated +host_inst_rate 1097269 # Simulator instruction rate (inst/s) +host_op_rate 1289528 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57098875481 # Simulator tick rate (ticks/s) +host_mem_usage 677960 # Number of bytes of host memory used +host_seconds 895.13 # Real time elapsed on the host +sim_insts 982203438 # Number of instructions simulated +sim_ops 1154301153 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3272948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 64755976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 188480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2212992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 45372224 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 442112 # Number of bytes read from this memory -system.physmem.bytes_read::total 116844476 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3272948 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2212992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5485940 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103078400 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 206336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 188160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3278004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 64990856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 207616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 185216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2205952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 45263168 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 436800 # Number of bytes read from this memory +system.physmem.bytes_read::total 116962108 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3278004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2205952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5483956 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103098980 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 91547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1011825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 34578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 708941 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6908 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1866115 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1610600 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2940 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91626 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1015495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 707237 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6825 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1867953 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1613173 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 64036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1266964 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3688 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 43298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 887717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2286086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 64036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 43298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 107334 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2016750 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 4037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 64135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1271559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 885583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8546 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2288387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 64135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43160 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 107295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2020646 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2017152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2016750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 64036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1267366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 43298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 887717 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4303238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2020646 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 64135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1271961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 885583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4309435 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -121,45 +121,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 144734 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 145509 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 145509 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 145509 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 145509 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 145509 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 108299 85.66% 85.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18127 14.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126426 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 145509 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 145509 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126426 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126426 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 271935 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91873100 # DTB read hits -system.cpu0.dtb.read_misses 107254 # DTB read misses -system.cpu0.dtb.write_hits 84300346 # DTB write hits -system.cpu0.dtb.write_misses 37480 # DTB write misses -system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 91814095 # DTB read hits +system.cpu0.dtb.read_misses 108271 # DTB read misses +system.cpu0.dtb.write_hits 84019310 # DTB write hits +system.cpu0.dtb.write_misses 37238 # DTB write misses +system.cpu0.dtb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25423 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56716 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4781 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91980354 # DTB read accesses -system.cpu0.dtb.write_accesses 84337826 # DTB write accesses +system.cpu0.dtb.perms_faults 10952 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91922366 # DTB read accesses +system.cpu0.dtb.write_accesses 84056548 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176173446 # DTB hits -system.cpu0.dtb.misses 144734 # DTB misses -system.cpu0.dtb.accesses 176318180 # DTB accesses +system.cpu0.dtb.hits 175833405 # DTB hits +system.cpu0.dtb.misses 145509 # DTB misses +system.cpu0.dtb.accesses 175978914 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -189,219 +189,219 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 70623 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 70811 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70811 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70811 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70811 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70811 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 62036 96.03% 96.03% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2564 3.97% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64600 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70811 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70811 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493558289 # ITB inst hits -system.cpu0.itb.inst_misses 70623 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135411 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 492376819 # ITB inst hits +system.cpu0.itb.inst_misses 70811 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51122 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25423 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 574 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40510 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses -system.cpu0.itb.hits 493558289 # DTB hits -system.cpu0.itb.misses 70623 # DTB misses -system.cpu0.itb.accesses 493628912 # DTB accesses -system.cpu0.numCycles 98036732821 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 492447630 # ITB inst accesses +system.cpu0.itb.hits 492376819 # DTB hits +system.cpu0.itb.misses 70811 # DTB misses +system.cpu0.itb.accesses 492447630 # DTB accesses +system.cpu0.numCycles 98037037144 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.committedInsts 493343054 # Number of instructions committed -system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses -system.cpu0.num_func_calls 28504103 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls -system.cpu0.num_int_insts 530703417 # number of integer instructions -system.cpu0.num_fp_insts 453665 # number of float instructions -system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written -system.cpu0.num_mem_refs 176296730 # number of memory refs -system.cpu0.num_load_insts 91967123 # Number of load instructions -system.cpu0.num_store_insts 84329607 # Number of store instructions -system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles -system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles -system.cpu0.Branches 110281342 # Number of branches fetched +system.cpu0.committedInsts 492158167 # Number of instructions committed +system.cpu0.committedOps 578111598 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 529632754 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 450817 # Number of float alu accesses +system.cpu0.num_func_calls 28493916 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76040779 # number of instructions that are conditional controls +system.cpu0.num_int_insts 529632754 # number of integer instructions +system.cpu0.num_fp_insts 450817 # number of float instructions +system.cpu0.num_int_register_reads 782886511 # number of times the integer registers were read +system.cpu0.num_int_register_writes 420745648 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 732502 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 369640 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 132702438 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132380757 # number of times the CC registers were written +system.cpu0.num_mem_refs 175957130 # number of memory refs +system.cpu0.num_load_insts 91908746 # Number of load instructions +system.cpu0.num_store_insts 84048384 # Number of store instructions +system.cpu0.num_idle_cycles 96929538971.519501 # Number of idle cycles +system.cpu0.num_busy_cycles 1107498172.480497 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011297 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988703 # Percentage of idle cycles +system.cpu0.Branches 110098677 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction -system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction -system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 401203105 69.36% 69.36% # Class of executed instruction +system.cpu0.op_class::IntMult 1174268 0.20% 69.56% # Class of executed instruction +system.cpu0.op_class::IntDiv 49936 0.01% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 53536 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::MemRead 91908746 15.89% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 84048384 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 579643698 # Class of executed instruction -system.cpu0.dcache.tags.replacements 11612141 # number of replacements +system.cpu0.op_class::total 578437975 # Class of executed instruction +system.cpu0.dcache.tags.replacements 11606642 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid 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number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 337709 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2250403 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2312061 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165516288 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165573626 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 331089914 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165724818 # number of overall hits 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hits +system.cpu0.dcache.StoreCondReq_hits::total 4555646 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165146293 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165037797 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 330184090 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165355623 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165252780 # number of overall hits +system.cpu0.dcache.overall_hits::total 330608403 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3016518 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2987065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6003583 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1295456 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1272689 # number of WriteReq misses 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number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4320843 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4259709 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 8580552 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5113751 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5050889 # number of overall misses -system.cpu0.dcache.overall_misses::total 10164640 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88696385 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88880954 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81140746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 80952381 # 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(read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033995 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033698 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016091 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015622 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.786673 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 4311974 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4259754 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 8571728 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5100211 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5057415 # number of overall misses +system.cpu0.dcache.overall_misses::total 10157626 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88617297 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 88496846 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177114143 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 80840970 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 80800705 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 161641675 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 997567 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1012644 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 2010211 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 905731 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 677324 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1583055 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2275973 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2281478 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4557451 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275074 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2280573 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4555647 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169458267 # number of demand (read+write) accesses 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miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.790159 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.787701 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788921 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.840746 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.716467 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787572 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055731 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055692 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055712 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025441 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025082 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029933 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029565 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025446 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025161 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025304 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029921 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029695 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029808 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,63 +410,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8921277 # number of writebacks -system.cpu0.dcache.writebacks::total 8921277 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8917390 # number of writebacks +system.cpu0.dcache.writebacks::total 8917390 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14295641 # number of replacements +system.cpu0.icache.tags.replacements 14265253 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 968529210 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14265765 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.891852 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476043 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.596946 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.387653 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.524603 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.475367 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 970865862 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 486466334 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 486466334 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits -system.cpu0.icache.overall_hits::total 970865862 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14296158 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses -system.cpu0.icache.overall_misses::total 14296158 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 997060750 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 997060750 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 485302740 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 483226470 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 968529210 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 485302740 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 483226470 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 968529210 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 485302740 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 483226470 # number of overall hits +system.cpu0.icache.overall_hits::total 968529210 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7138679 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7127091 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14265770 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7138679 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7127091 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14265770 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7138679 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7127091 # number of overall misses +system.cpu0.icache.overall_misses::total 14265770 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 492441419 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 490353561 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 982794980 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 492441419 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 490353561 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 982794980 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 492441419 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 490353561 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 982794980 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014497 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014535 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014516 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014497 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014535 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014516 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014497 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014535 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014516 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -475,8 +475,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 14295641 # number of writebacks -system.cpu0.icache.writebacks::total 14295641 # number of writebacks +system.cpu0.icache.writebacks::writebacks 14265253 # number of writebacks +system.cpu0.icache.writebacks::total 14265253 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -507,45 +507,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 143589 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 143142 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143142 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143142 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143142 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143142 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 106698 85.48% 85.48% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18131 14.52% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124829 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143142 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143142 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124829 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124829 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 267971 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92120843 # DTB read hits -system.cpu1.dtb.read_misses 106565 # DTB read misses -system.cpu1.dtb.write_hits 83929435 # DTB write hits -system.cpu1.dtb.write_misses 37024 # DTB write misses -system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 91711522 # DTB read hits +system.cpu1.dtb.read_misses 106128 # DTB read misses +system.cpu1.dtb.write_hits 83752453 # DTB write hits +system.cpu1.dtb.write_misses 37014 # DTB write misses +system.cpu1.dtb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24348 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56325 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4754 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92227408 # DTB read accesses -system.cpu1.dtb.write_accesses 83966459 # DTB write accesses +system.cpu1.dtb.perms_faults 10699 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 91817650 # DTB read accesses +system.cpu1.dtb.write_accesses 83789467 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 176050278 # DTB hits -system.cpu1.dtb.misses 143589 # DTB misses -system.cpu1.dtb.accesses 176193867 # DTB accesses +system.cpu1.dtb.hits 175463975 # DTB hits +system.cpu1.dtb.misses 143142 # DTB misses +system.cpu1.dtb.accesses 175607117 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -575,109 +575,109 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69863 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 69345 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69345 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69345 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69345 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69345 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 60894 96.02% 96.02% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2524 3.98% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63418 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69345 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69345 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 491475383 # ITB inst hits -system.cpu1.itb.inst_misses 69863 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63418 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63418 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 132763 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 490290143 # ITB inst hits +system.cpu1.itb.inst_misses 69345 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51111 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24348 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 565 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40528 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses -system.cpu1.itb.hits 491475383 # DTB hits -system.cpu1.itb.misses 69863 # DTB misses -system.cpu1.itb.accesses 491545246 # DTB accesses -system.cpu1.numCycles 97463064529 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 490359488 # ITB inst accesses +system.cpu1.itb.hits 490290143 # DTB hits +system.cpu1.itb.misses 69345 # DTB misses +system.cpu1.itb.accesses 490359488 # DTB accesses +system.cpu1.numCycles 97462077146 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 491227465 # Number of instructions committed -system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses -system.cpu1.num_func_calls 28552264 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls -system.cpu1.num_int_insts 529752049 # number of integer instructions -system.cpu1.num_fp_insts 427140 # number of float instructions -system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read -system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written -system.cpu1.num_mem_refs 176168876 # number of memory refs -system.cpu1.num_load_insts 92213308 # Number of load instructions -system.cpu1.num_store_insts 83955568 # Number of store instructions -system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles -system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles -system.cpu1.Branches 109807220 # Number of branches fetched +system.cpu1.committedInsts 490045271 # Number of instructions committed +system.cpu1.committedOps 576189555 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 528249503 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 430532 # Number of float alu accesses +system.cpu1.num_func_calls 28340665 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75582970 # number of instructions that are conditional controls +system.cpu1.num_int_insts 528249503 # number of integer instructions +system.cpu1.num_fp_insts 430532 # number of float instructions +system.cpu1.num_int_register_reads 777873169 # number of times the integer registers were read +system.cpu1.num_int_register_writes 419771432 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 687265 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 378920 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131316168 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131060074 # number of times the CC registers were written +system.cpu1.num_mem_refs 175582205 # number of memory refs +system.cpu1.num_load_insts 91803684 # Number of load instructions +system.cpu1.num_store_insts 83778521 # Number of store instructions +system.cpu1.num_idle_cycles 96357522330.236954 # Number of idle cycles +system.cpu1.num_busy_cycles 1104554815.763041 # Number of busy cycles +system.cpu1.not_idle_fraction 0.011333 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.988667 # Percentage of idle cycles +system.cpu1.Branches 109435377 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction -system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction -system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 399630588 69.32% 69.32% # Class of executed instruction +system.cpu1.op_class::IntMult 1180116 0.20% 69.53% # Class of executed instruction +system.cpu1.op_class::IntDiv 50607 0.01% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54286 0.01% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::MemRead 91803684 15.92% 85.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 83778521 14.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 578022895 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40246 # Transaction distribution -system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.cpu1.op_class::total 576497845 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40242 # Transaction distribution +system.iobus.trans_dist::ReadResp 40242 # Transaction distribution system.iobus.trans_dist::WriteReq 136515 # Transaction distribution system.iobus.trans_dist::WriteResp 136515 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) @@ -694,11 +694,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353514 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -713,53 +713,53 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115463 # number of replacements -system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use +system.iobus.pkt_size::total 7491944 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.407111 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ethernet 3.554597 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852514 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039686 # Number of tag accesses -system.iocache.tags.data_accesses 1039686 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses -system.iocache.demand_misses::total 8857 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8817 # number of overall misses -system.iocache.overall_misses::total 8857 # number of overall misses +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -784,209 +784,209 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1723178 # number of replacements -system.l2c.tags.tagsinuse 65341.862566 # Cycle average of tags in use -system.l2c.tags.total_refs 47049406 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1786474 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 26.336463 # Average number of references to valid blocks. +system.l2c.tags.replacements 1725796 # number of replacements +system.l2c.tags.tagsinuse 65319.576265 # Cycle average of tags in use +system.l2c.tags.total_refs 46978291 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1788815 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 26.262241 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37238.861730 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.459058 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 243.477138 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3478.418369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9618.970377 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.652979 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2640.978192 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11611.804335 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.568220 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.053076 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.146774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040298 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.177182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 63020 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 276 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 37199.693838 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 157.541812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.130433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3426.948929 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9570.300685 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 153.000068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 205.689904 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2648.963417 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11714.307180 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.567622 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002404 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003710 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.052291 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002335 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003139 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040420 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.178746 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996698 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62701 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2714 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4910 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54672 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.961609 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 426842331 # Number of tag accesses -system.l2c.tags.data_accesses 426842331 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 142757 # number of ReadReq hits -system.l2c.ReadReq_hits::total 844303 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8921277 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8921277 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 14294063 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 14294063 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 864865 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 827683 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1692548 # number of ReadExReq hits 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+system.l2c.ReadSharedReq_accesses::total 7843384 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 761490 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 485280 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1246770 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 283945 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 148805 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7138679 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5201020 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 280632 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 145102 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7127091 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5159377 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25484651 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 283945 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 148805 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7138679 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5201020 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 280632 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 145102 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7127091 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5159377 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25484651 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011354 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019757 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011560 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019945 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.014330 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779173 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782612 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780861 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.324291 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.332072 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.328119 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006770 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004845 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.005808 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045063 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042686 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.043877 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.548950 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.272814 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.442472 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006770 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.113635 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.020212 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004845 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112245 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049619 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006770 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.113635 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.020212 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004845 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112245 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049619 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.328611 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.328997 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328802 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006797 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004838 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005819 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.045159 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042577 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.043871 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.553213 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.269861 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.442924 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011354 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019757 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006797 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.114341 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011560 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.019945 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004838 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.111836 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049716 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011354 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019757 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006797 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.114341 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011560 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.019945 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004838 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.111836 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049716 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -995,51 +995,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1503969 # number of writebacks -system.l2c.writebacks::total 1503969 # number of writebacks +system.l2c.writebacks::writebacks 1507081 # number of writebacks +system.l2c.writebacks::total 1507081 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76679 # Transaction distribution -system.membus.trans_dist::ReadResp 525242 # Transaction distribution +system.membus.trans_dist::ReadResp 524934 # Transaction distribution system.membus.trans_dist::WriteReq 33606 # Transaction distribution system.membus.trans_dist::WriteResp 33606 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1610600 # Transaction distribution -system.membus.trans_dist::CleanEvict 224679 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40488 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1613712 # Transaction distribution +system.membus.trans_dist::CleanEvict 226309 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40494 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40489 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377035 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377035 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 448563 # Transaction distribution +system.membus.trans_dist::UpgradeResp 40495 # Transaction distribution +system.membus.trans_dist::ReadExReq 1379260 # Transaction distribution +system.membus.trans_dist::ReadExResp 1379260 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 448255 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5527785 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5656977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 344374 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6001351 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5534254 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5663446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 346493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6009939 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212718752 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 212887802 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7391040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 220278842 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213040864 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 213209914 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7390784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 220600698 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3920446 # Request fanout histogram +system.membus.snoop_fanout::samples 3924980 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3920446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3924980 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3920446 # Request fanout histogram +system.membus.snoop_fanout::total 3924980 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1092,49 +1092,49 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 52477792 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26568978 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1747 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2724 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2724 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 52405672 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26532742 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1744 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2693 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2693 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1320350 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1320342 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23429496 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8921277 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 14294063 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2690695 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 8917390 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 14265253 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2689252 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51132 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 14296158 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7848198 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1245349 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1245349 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42972629 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35073906 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 80533877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1829946644 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1234659558 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3074555570 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1954979 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 55175865 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.011169 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105093 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51133 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2517013 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2517013 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 14265770 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7843384 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1246770 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1246770 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 42883043 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35057562 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 830208 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1657118 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 80427931 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1826157972 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1233968038 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3320832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6628472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3070075314 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1957567 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 55106685 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.011176 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105126 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 54559594 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 616271 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 54490790 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 615895 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 55175865 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 55106685 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index 13ac1b801..b9cfad15e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,192 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.318151 # Number of seconds simulated -sim_ticks 51318151431000 # Number of ticks simulated -final_tick 51318151431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.278396 # Number of seconds simulated +sim_ticks 51278396244000 # Number of ticks simulated +final_tick 51278396244000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 262276 # Simulator instruction rate (inst/s) -host_op_rate 308198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15864240835 # Simulator tick rate (ticks/s) -host_mem_usage 687920 # Number of bytes of host memory used -host_seconds 3234.83 # Real time elapsed on the host -sim_insts 848418690 # Number of instructions simulated -sim_ops 996969189 # Number of ops (including micro ops) simulated +host_inst_rate 287420 # Simulator instruction rate (inst/s) +host_op_rate 337741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17381457033 # Simulator tick rate (ticks/s) +host_mem_usage 688188 # Number of bytes of host memory used +host_seconds 2950.18 # Real time elapsed on the host +sim_insts 847940135 # Number of instructions simulated +sim_ops 996397451 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 76672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 79744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2462068 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 43565640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 25536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 20992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 433216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 6171840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 28864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 29440 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1450304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 8009024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 65344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 58432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1793920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 14730432 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 421568 # Number of bytes read from this memory -system.physmem.bytes_read::total 79423036 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2462068 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 433216 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1450304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1793920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6139508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67636992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 80128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 85632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2427380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 43615880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 26944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 6225152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 27008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 28160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1496000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 7976640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 59008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 56384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1720000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 14392384 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory +system.physmem.bytes_read::total 79110012 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2427380 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1496000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1720000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6092084 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 67404672 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 67657572 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1246 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 78877 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 680726 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 328 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 96435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 451 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 460 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 22661 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 125141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1021 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 913 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 28030 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 230163 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6587 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1281405 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1056828 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 67425252 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 78335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 681511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 97268 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 440 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 23375 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 124635 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 922 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 881 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 26875 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 224881 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1276514 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1053198 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1059401 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1554 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 47977 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 848932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8442 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 120266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 28261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 156066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 34957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 287041 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1547660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 47977 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8442 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 28261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 34957 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 119636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1317994 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1055771 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 47337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 850570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 8750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 121399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 29174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 155556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 33542 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 280671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1542755 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 47337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 8750 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 29174 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 33542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 118804 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1314485 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1318395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1317994 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1554 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 47977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 849333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8442 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 120266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 28261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 156066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 34957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 287041 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2866054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 517103 # Number of read requests accepted -system.physmem.writeReqs 450227 # Number of write requests accepted -system.physmem.readBursts 517103 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 450227 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 33073280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue -system.physmem.bytesWritten 28812544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 33094592 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 28814528 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1314886 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1314485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 47337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 850972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 8750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 121399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 29174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 155556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 33542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 280671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2857641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 511823 # Number of read requests accepted +system.physmem.writeReqs 447580 # Number of write requests accepted +system.physmem.readBursts 511823 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 447580 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 32737280 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19392 # Total number of bytes read from write queue +system.physmem.bytesWritten 28644032 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 32756672 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 28645120 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 303 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 174284 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 32820 # Per bank write bursts -system.physmem.perBankRdBursts::1 35061 # Per bank write bursts -system.physmem.perBankRdBursts::2 31334 # Per bank write bursts -system.physmem.perBankRdBursts::3 30738 # Per bank write bursts -system.physmem.perBankRdBursts::4 32772 # Per bank write bursts -system.physmem.perBankRdBursts::5 36727 # Per bank write bursts -system.physmem.perBankRdBursts::6 31736 # Per bank write bursts -system.physmem.perBankRdBursts::7 32381 # Per bank write bursts -system.physmem.perBankRdBursts::8 29681 # Per bank write bursts -system.physmem.perBankRdBursts::9 35684 # Per bank write bursts -system.physmem.perBankRdBursts::10 31546 # Per bank write bursts -system.physmem.perBankRdBursts::11 32698 # Per bank write bursts -system.physmem.perBankRdBursts::12 33025 # Per bank write bursts -system.physmem.perBankRdBursts::13 31465 # Per bank write bursts -system.physmem.perBankRdBursts::14 29673 # Per bank write bursts -system.physmem.perBankRdBursts::15 29429 # Per bank write bursts -system.physmem.perBankWrBursts::0 27864 # Per bank write bursts -system.physmem.perBankWrBursts::1 28674 # Per bank write bursts -system.physmem.perBankWrBursts::2 26960 # Per bank write bursts -system.physmem.perBankWrBursts::3 27504 # Per bank write bursts -system.physmem.perBankWrBursts::4 29012 # Per bank write bursts -system.physmem.perBankWrBursts::5 31175 # Per bank write bursts -system.physmem.perBankWrBursts::6 28381 # Per bank write bursts -system.physmem.perBankWrBursts::7 29346 # Per bank write bursts -system.physmem.perBankWrBursts::8 26700 # Per bank write bursts -system.physmem.perBankWrBursts::9 31017 # Per bank write bursts -system.physmem.perBankWrBursts::10 26800 # Per bank write bursts -system.physmem.perBankWrBursts::11 28289 # Per bank write bursts -system.physmem.perBankWrBursts::12 28254 # Per bank write bursts -system.physmem.perBankWrBursts::13 27295 # Per bank write bursts -system.physmem.perBankWrBursts::14 26424 # Per bank write bursts -system.physmem.perBankWrBursts::15 26501 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 29703 # Per bank write bursts +system.physmem.perBankRdBursts::1 34345 # Per bank write bursts +system.physmem.perBankRdBursts::2 31026 # Per bank write bursts +system.physmem.perBankRdBursts::3 30271 # Per bank write bursts +system.physmem.perBankRdBursts::4 32199 # Per bank write bursts +system.physmem.perBankRdBursts::5 37423 # Per bank write bursts +system.physmem.perBankRdBursts::6 31570 # Per bank write bursts +system.physmem.perBankRdBursts::7 30956 # Per bank write bursts +system.physmem.perBankRdBursts::8 30714 # Per bank write bursts +system.physmem.perBankRdBursts::9 34361 # Per bank write bursts +system.physmem.perBankRdBursts::10 33202 # Per bank write bursts +system.physmem.perBankRdBursts::11 32791 # Per bank write bursts +system.physmem.perBankRdBursts::12 32230 # Per bank write bursts +system.physmem.perBankRdBursts::13 32440 # Per bank write bursts +system.physmem.perBankRdBursts::14 29459 # Per bank write bursts +system.physmem.perBankRdBursts::15 28830 # Per bank write bursts +system.physmem.perBankWrBursts::0 25970 # Per bank write bursts +system.physmem.perBankWrBursts::1 28442 # Per bank write bursts +system.physmem.perBankWrBursts::2 26808 # Per bank write bursts +system.physmem.perBankWrBursts::3 27272 # Per bank write bursts +system.physmem.perBankWrBursts::4 29035 # Per bank write bursts +system.physmem.perBankWrBursts::5 31977 # Per bank write bursts +system.physmem.perBankWrBursts::6 28169 # Per bank write bursts +system.physmem.perBankWrBursts::7 28603 # Per bank write bursts +system.physmem.perBankWrBursts::8 27151 # Per bank write bursts +system.physmem.perBankWrBursts::9 29537 # Per bank write bursts +system.physmem.perBankWrBursts::10 28051 # Per bank write bursts +system.physmem.perBankWrBursts::11 28561 # Per bank write bursts +system.physmem.perBankWrBursts::12 27796 # Per bank write bursts +system.physmem.perBankWrBursts::13 28123 # Per bank write bursts +system.physmem.perBankWrBursts::14 26050 # Per bank write bursts +system.physmem.perBankWrBursts::15 26018 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 51317151101500 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 51277395805500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 517103 # Read request sizes (log2) +system.physmem.readPktSize::6 511823 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 450227 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 365842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 95262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 435 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 491 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 222 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 244 # What read queue length does an incoming req see +system.physmem.writePktSize::6 447580 # Write request sizes (log2) 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req see -system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 87 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -198,187 +198,182 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 556 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::12 550 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 8261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 18409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 21789 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 24777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 26143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 27073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 27056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 27725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 27794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 27996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 30008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 27705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 27676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 29590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 26243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 26383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 25171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 260816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 237.276486 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.923814 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.776542 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 119999 46.01% 46.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 65306 25.04% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 23923 9.17% 80.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 11962 4.59% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8906 3.41% 88.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5685 2.18% 90.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4538 1.74% 92.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3514 1.35% 93.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16983 6.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 260816 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 25134 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.558447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 13.007693 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-31 22781 90.64% 90.64% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-63 2174 8.65% 99.29% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-95 141 0.56% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-127 17 0.07% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-159 6 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::192-223 6 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-287 1 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::320-351 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::576-607 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::672-703 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 25134 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 25134 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.911833 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.251303 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.505158 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 24 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 17 0.07% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 14 0.06% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 60 0.24% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 23322 92.79% 93.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 527 2.10% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 146 0.58% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 283 1.13% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 54 0.21% 97.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 168 0.67% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 80 0.32% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 22 0.09% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.10% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 58 0.23% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.08% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.04% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 213 0.85% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.04% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.14% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 25134 # Writes before turning the bus around for reads -system.physmem.totQLat 10819472737 # Total ticks spent queuing -system.physmem.totMemAccLat 20508910237 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2583850000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20936.73 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::14 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 8731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 19434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 21637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 24704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 25741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 25599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 25799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 26532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 27053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 28426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 27490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 27929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 30961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 26710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 26732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 25592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 71 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 257915 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.988981 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.092695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.727383 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 118797 46.06% 46.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 64316 24.94% 71.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 23486 9.11% 80.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11936 4.63% 84.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8805 3.41% 88.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5543 2.15% 90.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4520 1.75% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3591 1.39% 93.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16921 6.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 257915 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 24705 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.705080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 14.399508 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-63 24532 99.30% 99.30% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-127 158 0.64% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-191 5 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::192-255 5 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-319 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-575 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-703 2 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1088-1151 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 24705 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 24705 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.116292 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.314740 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.551029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 22 0.09% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 13 0.05% 0.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 13 0.05% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 49 0.20% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 23047 93.29% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 446 1.81% 95.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 165 0.67% 96.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 178 0.72% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 51 0.21% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 35 0.14% 97.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 69 0.28% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.04% 97.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 185 0.75% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 38 0.15% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.06% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 28 0.11% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 125 0.51% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.06% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 68 0.28% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 94 0.38% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 10 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 24705 # Writes before turning the bus around for reads +system.physmem.totQLat 10604540202 # Total ticks spent queuing +system.physmem.totMemAccLat 20195540202 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2557600000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20731.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39686.73 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 39481.43 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.56 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage -system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 13.27 # Average write queue length when enqueuing -system.physmem.readRowHits 394016 # Number of row buffer hits during reads -system.physmem.writeRowHits 312132 # Number of row buffer hits during writes +system.physmem.avgWrQLen 6.40 # Average write queue length when enqueuing +system.physmem.readRowHits 390042 # Number of row buffer hits during reads +system.physmem.writeRowHits 311121 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.33 # Row buffer hit rate for writes -system.physmem.avgGap 53050304.55 # Average gap between requests -system.physmem.pageHitRate 73.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1012329360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 550658625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2055807000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1483375680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3312957669840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1179842633775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29693796398250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34191698872530 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.616546 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48906772559460 # Time in different power states -system.physmem_0.memoryStateTime::REF 1693741140000 # Time in different power states +system.physmem.writeRowHitRate 69.51 # Row buffer hit rate for writes +system.physmem.avgGap 53447191.44 # Average gap between requests +system.physmem.pageHitRate 73.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 987139440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 536905875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2008390800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1466203680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3310428600960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1177085104875 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 30106909725750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34599422071380 # Total energy per rank (pJ) +system.physmem_0.averagePower 666.667509 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48872262134916 # Time in different power states +system.physmem_0.memoryStateTime::REF 1692448160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 122637370540 # Time in different power states +system.physmem_0.memoryStateTime::ACT 119734785584 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 959439600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 521932125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1974960000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1433894400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3312957669840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1178190529245 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 30742990092750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 35239028517960 # Total energy per rank (pJ) -system.physmem_1.averagePower 665.379239 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48909312036157 # Time in different power states -system.physmem_1.memoryStateTime::REF 1693741140000 # Time in different power states +system.physmem_1.actEnergy 962629920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 523549125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1981395000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1433900880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3310428600960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1177786265580 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29667035331750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34160151673215 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.621174 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48871271616428 # Time in different power states +system.physmem_1.memoryStateTime::REF 1692448160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120107401343 # Time in different power states +system.physmem_1.memoryStateTime::ACT 120718837572 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -438,47 +433,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 90147 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 90147 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 90147 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 90147 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 90147 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 390083894328 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.522589 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -203853691422 -52.26% -52.26% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 593937585750 152.26% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 390083894328 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 65853 84.82% 84.82% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11789 15.18% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 77642 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90147 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 90127 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90127 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90127 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90127 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90127 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 389002834492 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.524244 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -203932266508 -52.42% -52.42% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 592935101000 152.42% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 389002834492 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 65772 85.00% 85.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11604 15.00% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 77376 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90127 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90147 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77642 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90127 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77376 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77642 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 167789 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77376 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 167503 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64842340 # DTB read hits -system.cpu0.dtb.read_misses 68503 # DTB read misses -system.cpu0.dtb.write_hits 59153195 # DTB write hits -system.cpu0.dtb.write_misses 21644 # DTB write misses -system.cpu0.dtb.flush_tlb 1197 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 64859725 # DTB read hits +system.cpu0.dtb.read_misses 68631 # DTB read misses +system.cpu0.dtb.write_hits 59094124 # DTB write hits +system.cpu0.dtb.write_misses 21496 # DTB write misses +system.cpu0.dtb.flush_tlb 1195 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16138 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41112 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16177 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 384 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 40401 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2836 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2751 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7541 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64910843 # DTB read accesses -system.cpu0.dtb.write_accesses 59174839 # DTB write accesses +system.cpu0.dtb.perms_faults 7419 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64928356 # DTB read accesses +system.cpu0.dtb.write_accesses 59115620 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 123995535 # DTB hits -system.cpu0.dtb.misses 90147 # DTB misses -system.cpu0.dtb.accesses 124085682 # DTB accesses +system.cpu0.dtb.hits 123953849 # DTB hits +system.cpu0.dtb.misses 90127 # DTB misses +system.cpu0.dtb.accesses 124043976 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -508,699 +503,699 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 53264 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53264 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53264 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53264 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53264 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 390083894328 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.522690 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -203892956422 -52.27% -52.27% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 593976850750 152.27% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 390083894328 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 46252 94.85% 94.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2512 5.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 48764 # Table walker page sizes translated +system.cpu0.itb.walker.walks 53226 # Table walker walks requested +system.cpu0.itb.walker.walksLong 53226 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 53226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 53226 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 53226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 389002834492 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.524351 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -203974019508 -52.44% -52.44% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 592976854000 152.44% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 389002834492 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 46188 94.90% 94.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2484 5.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 48672 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53264 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53264 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53226 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48764 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48764 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 102028 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 346149733 # ITB inst hits -system.cpu0.itb.inst_misses 53264 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48672 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48672 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 101898 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 346140401 # ITB inst hits +system.cpu0.itb.inst_misses 53226 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1197 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1195 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16138 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 390 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 28909 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16177 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 384 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 28414 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 346202997 # ITB inst accesses -system.cpu0.itb.hits 346149733 # DTB hits -system.cpu0.itb.misses 53264 # DTB misses -system.cpu0.itb.accesses 346202997 # DTB accesses -system.cpu0.numCycles 417561800 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 346193627 # ITB inst accesses +system.cpu0.itb.hits 346140401 # DTB hits +system.cpu0.itb.misses 53226 # DTB misses +system.cpu0.itb.accesses 346193627 # DTB accesses +system.cpu0.numCycles 417471005 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16515 # number of quiesce instructions executed -system.cpu0.committedInsts 346008550 # Number of instructions committed -system.cpu0.committedOps 406987651 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 373920117 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 356678 # Number of float alu accesses -system.cpu0.num_func_calls 20899397 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 52499689 # number of instructions that are conditional controls -system.cpu0.num_int_insts 373920117 # number of integer instructions -system.cpu0.num_fp_insts 356678 # number of float instructions -system.cpu0.num_int_register_reads 546105589 # number of times the integer registers were read -system.cpu0.num_int_register_writes 296761298 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 572858 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 307664 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 90112158 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89900490 # number of times the CC registers were written -system.cpu0.num_mem_refs 124068171 # number of memory refs -system.cpu0.num_load_insts 64899300 # Number of load instructions -system.cpu0.num_store_insts 59168871 # Number of store instructions -system.cpu0.num_idle_cycles 407652478.881758 # Number of idle cycles -system.cpu0.num_busy_cycles 9909321.118242 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023731 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976269 # Percentage of idle cycles -system.cpu0.Branches 77190718 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16511 # number of quiesce instructions executed +system.cpu0.committedInsts 345998217 # Number of instructions committed +system.cpu0.committedOps 406905705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 373867604 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 363074 # Number of float alu accesses +system.cpu0.num_func_calls 20947482 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 52475381 # number of instructions that are conditional controls +system.cpu0.num_int_insts 373867604 # number of integer instructions +system.cpu0.num_fp_insts 363074 # number of float instructions +system.cpu0.num_int_register_reads 545388282 # number of times the integer registers were read +system.cpu0.num_int_register_writes 296679828 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 584270 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 311304 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89963697 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89731719 # number of times the CC registers were written +system.cpu0.num_mem_refs 124026394 # number of memory refs +system.cpu0.num_load_insts 64916857 # Number of load instructions +system.cpu0.num_store_insts 59109537 # Number of store instructions +system.cpu0.num_idle_cycles 408121506.428325 # Number of idle cycles +system.cpu0.num_busy_cycles 9349498.571675 # Number of busy cycles +system.cpu0.not_idle_fraction 0.022396 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.977604 # Percentage of idle cycles +system.cpu0.Branches 77230042 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 282157616 69.29% 69.29% # Class of executed instruction -system.cpu0.op_class::IntMult 905041 0.22% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 41769 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 48126 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::MemRead 64899300 15.94% 85.47% # Class of executed instruction -system.cpu0.op_class::MemWrite 59168871 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 282115014 69.29% 69.29% # Class of executed instruction +system.cpu0.op_class::IntMult 908017 0.22% 69.51% # Class of executed instruction +system.cpu0.op_class::IntDiv 41532 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 48729 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 64916857 15.94% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 59109537 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 407220723 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9652340 # number of replacements +system.cpu0.op_class::total 407139686 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9649816 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999717 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 292908190 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9652852 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.344212 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 292739937 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9650328 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.334714 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.670724 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.324705 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.721037 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.283251 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970060 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008447 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011174 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.010319 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.097568 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.975954 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 4.503732 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 4.422464 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.972847 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009719 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.008796 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.008638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1241214397 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1241214397 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 60685320 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 18803520 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26329065 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 44829860 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 150647765 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55967588 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17443504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23296963 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 37688434 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134396489 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 158786 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47711 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 76477 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112686 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395660 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 125958 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 46133 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 59042 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 98089 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329222 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1437510 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 434789 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583575 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933284 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3389158 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1528933 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 473870 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 632507 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1071003 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3706313 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 116652908 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 36247024 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 49626028 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 82518294 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 285044254 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 116811694 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 36294735 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 49702505 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 82630980 # number of overall hits -system.cpu0.dcache.overall_hits::total 285439914 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2050128 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 627869 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 999043 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 3448243 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7125283 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 845493 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 257929 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 592373 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 3452560 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5148355 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 464960 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 152113 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 201110 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 351568 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1169751 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 684118 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 112802 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu2.data 149261 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu3.data 279937 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1226118 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 92149 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 39328 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 49168 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 175617 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 356262 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1240452518 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1240452518 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 60697634 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 18777257 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 26142693 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 44948482 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 150566066 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55906928 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17271712 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23345865 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 37782358 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134306863 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 159073 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47007 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 77709 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113008 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 396797 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 126017 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 45823 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 59716 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 97286 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 328842 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1444166 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 434424 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 579867 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 933968 # 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rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024221 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023855 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031072 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.077174 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.041281 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027965 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027802 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034810 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080686 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.044979 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16558.383994 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17221.784248 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17597.375388 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12389.939529 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38752.228326 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36802.187980 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 34278.467562 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29163.570105 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 32809.746281 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 35773.601276 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 40588.964406 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16640.291904 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14175.371237 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15023.765457 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13407.463400 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10247.390965 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 31375 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25100 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23020.846175 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24510.200664 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25943.139149 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19425.881509 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19646.982737 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21760.312263 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24685.512154 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17735.575268 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 14877388 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 44459 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 886775 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 413 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.776959 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 107.648910 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024217 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024472 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030717 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.076885 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.041252 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027919 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028440 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034562 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.080382 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.044948 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16567.781104 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17286.941404 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 17453.909058 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12307.919483 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38218.715233 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36847.384692 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 33783.453653 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28852.560905 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 34331.719061 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 34818.174897 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 39573.470845 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 16359.673206 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14200.946877 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14882.189368 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 13340.594163 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10202.699483 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 82000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 41000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 22765.541821 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24734.316717 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 25629.357569 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19252.389245 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19483.681045 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21861.370694 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 24387.931049 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17576.395912 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14582944 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 41803 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 883633 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 391 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.503395 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 106.913043 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7483477 # number of writebacks -system.cpu0.dcache.writebacks::total 7483477 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3222 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 130575 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1920030 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2053827 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 4922 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 261783 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2870322 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3137027 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 26 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2099 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2125 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8352 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10672 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 107753 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 126777 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 8144 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 392358 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 4790352 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5190854 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 8144 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 392358 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 4790352 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5190854 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 624647 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 868468 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1528213 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3021328 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 253007 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 330590 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 582238 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1165835 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 151732 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 198469 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 344358 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 694559 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 112802 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 149235 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 277838 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 539875 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 30976 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 38496 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 67864 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137336 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 877654 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1199058 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2110451 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4187163 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1029386 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1397527 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2454809 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4881722 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6935 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6911 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 6765 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20611 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 6456 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6468 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6500 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19424 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 13391 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 13379 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13265 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40035 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9554770500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 13722884500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 26401240500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49678895500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9526378000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 11636542500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 21578675477 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42741595977 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 3041699000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3963544500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 6809698000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13814941500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 3588203000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 5189095500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10959309429 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 19736607929 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 400391000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 515235000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 967704000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1883330000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 121500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 121500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19081148500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25359427000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 47979915977 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 92420491477 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22122847500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29322971500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 54789613977 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 106235432977 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1364610000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1364502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1307720500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4036833000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1311207000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1311882500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1281361955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3904451455 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2675817000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2676385000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2589082455 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7941284455 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032146 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031779 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031654 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019150 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014293 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013838 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014152 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008355 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759328 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.714979 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.741745 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.443691 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.709737 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716432 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.734971 # mshr miss rate for WriteLineReq accesses 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average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37652.626212 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35199.317886 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 37061.606211 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36661.788312 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20046.522817 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19970.597423 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19775.053868 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19890.234667 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 31809.746281 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 34771.303649 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 39444.962277 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36557.736382 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12925.845816 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13384.117830 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.460097 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.301683 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 30375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 30375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21741.083046 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21149.458158 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22734.437320 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22072.341458 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21491.304039 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20982.042923 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22319.298152 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21761.876849 # average overall mshr miss latency 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LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1874239000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19259683000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 25121528500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 47536531790 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 91917743290 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22379793500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 29162218500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 54310482790 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 105852494790 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1362861000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1366136000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1368520000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4097517000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1303404500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1305231500 # number of WriteReq MSHR uncacheable cycles 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ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019151 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013913 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014123 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008386 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762262 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.716912 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.740462 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.446359 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.702894 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.716561 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.736431 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.345497 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064632 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.063514 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.059942 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036560 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024250 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023109 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023579 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.014099 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028209 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026945 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027269 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15314.125294 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15841.786159 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17146.322257 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16390.897160 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37114.933907 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35144.915463 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 36557.702052 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36276.276532 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20535.013591 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 19858.995719 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 19726.411276 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19940.829702 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 33331.719061 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 33815.541695 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 38418.062499 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36097.627366 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12955.759736 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 13304.665451 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 14259.752308 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13689.169844 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21492.495358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21291.487906 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 22495.535957 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21941.849637 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21353.684880 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 21080.791626 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 22108.446764 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21655.774548 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197430.247718 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196906.313059 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 190867.503487 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 195017.705012 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 203561.533656 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 202173.404585 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 194866.989255 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200075.202826 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 200380.692920 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 199445.087353 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 192826.986910 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 197467.967588 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15741403 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.971353 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 557979460 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15741915 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.445463 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 15707105 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.971411 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 557754178 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 15707617 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.508517 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 11785355500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.989508 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.251405 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 22.715639 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.014801 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.935526 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006350 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.044366 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.013701 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.312770 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.251841 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 23.846438 # Average occupied blocks per requestor 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id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 589817883 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 589817883 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 340610645 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 106018813 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 63853653 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu3.inst 47496349 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 557979460 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 340610645 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 106018813 # number of demand (read+write) hits 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# number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53501368000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 66794187305 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 143021271805 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 22725716500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 53501368000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu3.inst 66794187305 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 143021271805 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 22725716500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 53501368000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu3.inst 66794187305 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 143021271805 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 346198497 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 107701123 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 67751473 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu3.inst 52424793 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 574075886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 346198497 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 107701123 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 67751473 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu3.inst 52424793 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 574075886 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 346198497 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 107701123 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 67751473 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu3.inst 52424793 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 574075886 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016141 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015620 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057531 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.094010 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028039 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016141 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015620 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057531 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu3.inst 0.094010 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028039 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016141 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015620 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057531 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu3.inst 0.094010 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028039 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13508.637825 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13725.971954 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13552.794209 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8885.281230 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13508.637825 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13725.971954 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13552.794209 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8885.281230 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13508.637825 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13725.971954 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13552.794209 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8885.281230 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 61852 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 589528421 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 589528421 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 340625874 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 105592046 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 63997933 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu3.inst 47538325 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 557754178 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 340625874 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 105592046 # number of demand (read+write) hits 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# number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 53176348000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 67096069815 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 142837273315 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 22564855500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 53176348000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu3.inst 67096069815 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 142837273315 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 22564855500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 53176348000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu3.inst 67096069815 # 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+system.cpu0.icache.overall_mshr_miss_rate::total 0.017679 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12529.583299 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12753.953887 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.275451 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12758.569386 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12529.583299 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12753.953887 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.275451 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12758.569386 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12529.583299 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12753.953887 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.275451 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12758.569386 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1231,72 +1226,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 31832 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 31832 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4623 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23155 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 31889 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31889 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4559 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23393 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31826 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1.131151 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 163.231245 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 31824 99.99% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::samples 31883 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.878211 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 156.811692 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 31882 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31826 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 27784 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25027.875756 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21593.645021 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16285.465271 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 18174 65.41% 65.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9447 34.00% 99.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 1 0.00% 99.42% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 131 0.47% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 8 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 27784 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -2880889132 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.351726 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkWaitTime::total 31883 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27958 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25168.842550 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21742.406424 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16076.029843 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 18219 65.17% 65.17% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9556 34.18% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 2 0.01% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 143 0.51% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 15 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 12 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27958 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1140126012 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.890541 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1013283500 -35.17% -35.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -3894172632 135.17% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -2880889132 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 23155 83.36% 83.36% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4623 16.64% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 27778 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31832 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::0 1015329500 -89.05% -89.05% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -2155455512 189.05% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1140126012 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 23393 83.69% 83.69% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4559 16.31% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27952 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31889 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31832 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27778 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31889 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27952 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27778 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 59610 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27952 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 59841 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20112265 # DTB read hits -system.cpu1.dtb.read_misses 24546 # DTB read misses -system.cpu1.dtb.write_hits 18343322 # DTB write hits -system.cpu1.dtb.write_misses 7286 # DTB write misses -system.cpu1.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 20102110 # DTB read hits +system.cpu1.dtb.read_misses 24529 # DTB read misses +system.cpu1.dtb.write_hits 18166884 # DTB write hits +system.cpu1.dtb.write_misses 7360 # DTB write misses +system.cpu1.dtb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5429 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 141 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 18466 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5389 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 18327 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 996 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2613 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20136811 # DTB read accesses -system.cpu1.dtb.write_accesses 18350608 # DTB write accesses +system.cpu1.dtb.perms_faults 2685 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20126639 # DTB read accesses +system.cpu1.dtb.write_accesses 18174244 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 38455587 # DTB hits -system.cpu1.dtb.misses 31832 # DTB misses -system.cpu1.dtb.accesses 38487419 # DTB accesses +system.cpu1.dtb.hits 38268994 # DTB hits +system.cpu1.dtb.misses 31889 # DTB misses +system.cpu1.dtb.accesses 38300883 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1326,130 +1319,130 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 20094 # Table walker walks requested -system.cpu1.itb.walker.walksLong 20094 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 971 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17728 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 20094 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 20094 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 20094 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18699 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28327.343708 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25076.534832 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18332.547535 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 18529 99.09% 99.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 145 0.78% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 20281 # Table walker walks requested +system.cpu1.itb.walker.walksLong 20281 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 944 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17917 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 20281 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 20281 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 20281 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18861 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28459.466624 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25212.666818 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18596.263354 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 18677 99.02% 99.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 158 0.84% 99.86% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::196608-262143 7 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 8 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 6 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 5 0.03% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18699 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18861 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17728 94.81% 94.81% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 971 5.19% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18699 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17917 94.99% 94.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 944 5.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18861 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20094 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20094 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20281 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20281 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18699 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18699 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 38793 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 107701123 # ITB inst hits -system.cpu1.itb.inst_misses 20094 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18861 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18861 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 39142 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 107259862 # ITB inst hits +system.cpu1.itb.inst_misses 20281 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5429 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 141 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13720 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5389 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 137 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13712 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 107721217 # ITB inst accesses -system.cpu1.itb.hits 107701123 # DTB hits -system.cpu1.itb.misses 20094 # DTB misses -system.cpu1.itb.accesses 107721217 # DTB accesses -system.cpu1.numCycles 1188094365 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 107280143 # ITB inst accesses +system.cpu1.itb.hits 107259862 # DTB hits +system.cpu1.itb.misses 20281 # DTB misses +system.cpu1.itb.accesses 107280143 # DTB accesses +system.cpu1.numCycles 1186091604 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 107621607 # Number of instructions committed -system.cpu1.committedOps 126383134 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 116203246 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 115467 # Number of float alu accesses -system.cpu1.num_func_calls 6450925 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16259693 # number of instructions that are conditional controls -system.cpu1.num_int_insts 116203246 # number of integer instructions -system.cpu1.num_fp_insts 115467 # number of float instructions -system.cpu1.num_int_register_reads 168004862 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92163558 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 188871 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 91760 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 27757608 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27690244 # number of times the CC registers were written -system.cpu1.num_mem_refs 38453101 # number of memory refs -system.cpu1.num_load_insts 20111693 # Number of load instructions -system.cpu1.num_store_insts 18341408 # Number of store instructions -system.cpu1.num_idle_cycles 1162766845.919452 # Number of idle cycles -system.cpu1.num_busy_cycles 25327519.080548 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021318 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978682 # Percentage of idle cycles -system.cpu1.Branches 23943919 # Number of branches fetched +system.cpu1.committedInsts 107180280 # Number of instructions committed +system.cpu1.committedOps 125798339 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 115609456 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 108829 # Number of float alu accesses +system.cpu1.num_func_calls 6343191 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16252887 # number of instructions that are conditional controls +system.cpu1.num_int_insts 115609456 # number of integer instructions +system.cpu1.num_fp_insts 108829 # number of float instructions +system.cpu1.num_int_register_reads 167399256 # number of times the integer registers were read +system.cpu1.num_int_register_writes 91770929 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 176307 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 89468 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 27813306 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27752983 # number of times the CC registers were written +system.cpu1.num_mem_refs 38266694 # number of memory refs +system.cpu1.num_load_insts 20101554 # Number of load instructions +system.cpu1.num_store_insts 18165140 # Number of store instructions +system.cpu1.num_idle_cycles 1160685667.067715 # Number of idle cycles +system.cpu1.num_busy_cycles 25405936.932285 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021420 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978580 # Percentage of idle cycles +system.cpu1.Branches 23816903 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 87732322 69.37% 69.37% # Class of executed instruction -system.cpu1.op_class::IntMult 254511 0.20% 69.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 10291 0.01% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 12383 0.01% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu1.op_class::MemRead 20111693 15.90% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 18341408 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 87315881 69.37% 69.37% # Class of executed instruction +system.cpu1.op_class::IntMult 273375 0.22% 69.58% # Class of executed instruction +system.cpu1.op_class::IntDiv 10716 0.01% 69.59% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.59% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 11213 0.01% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.60% # Class of executed instruction +system.cpu1.op_class::MemRead 20101554 15.97% 85.57% # Class of executed instruction +system.cpu1.op_class::MemWrite 18165140 14.43% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 126462650 # Class of executed instruction -system.cpu2.branchPred.lookups 39591395 # Number of BP lookups -system.cpu2.branchPred.condPredicted 27402166 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2021243 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 28606558 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20093171 # Number of BTB hits +system.cpu1.op_class::total 125877921 # Class of executed instruction +system.cpu2.branchPred.lookups 39521108 # Number of BP lookups +system.cpu2.branchPred.condPredicted 27394498 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1977688 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 28624019 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20176228 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.239737 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4887391 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 324081 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.487055 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4882878 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 320724 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1479,61 +1472,60 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 95006 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 95006 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6740 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29708 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 95006 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 95006 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 95006 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 36448 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 25417.457748 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22182.749988 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 16592.444485 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 36232 99.41% 99.41% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.41% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 183 0.50% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 9 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 9 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 93699 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93699 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6670 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29108 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93699 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93699 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93699 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 35778 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 25406.269216 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 22092.991962 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 16331.424603 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 35575 99.43% 99.43% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 169 0.47% 99.90% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 13 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::327680-393215 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::393216-458751 8 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::589824-655359 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 36448 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 35778 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000224000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000224000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000224000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 29708 81.51% 81.51% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 6740 18.49% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 36448 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 95006 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 29108 81.36% 81.36% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 6670 18.64% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 35778 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93699 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 95006 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36448 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93699 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 35778 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36448 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 131454 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 35778 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 129477 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28518980 # DTB read hits -system.cpu2.dtb.read_misses 79318 # DTB read misses -system.cpu2.dtb.write_hits 24832866 # DTB write hits -system.cpu2.dtb.write_misses 15688 # DTB write misses -system.cpu2.dtb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28306173 # DTB read hits +system.cpu2.dtb.read_misses 78188 # DTB read misses +system.cpu2.dtb.write_hits 24883433 # DTB write hits +system.cpu2.dtb.write_misses 15511 # DTB write misses +system.cpu2.dtb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 6544 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 184 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22314 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2052 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 6582 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 193 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22329 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 81 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 1959 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3674 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28598298 # DTB read accesses -system.cpu2.dtb.write_accesses 24848554 # DTB write accesses +system.cpu2.dtb.perms_faults 3725 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28384361 # DTB read accesses +system.cpu2.dtb.write_accesses 24898944 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53351846 # DTB hits -system.cpu2.dtb.misses 95006 # DTB misses -system.cpu2.dtb.accesses 53446852 # DTB accesses +system.cpu2.dtb.hits 53189606 # DTB hits +system.cpu2.dtb.misses 93699 # DTB misses +system.cpu2.dtb.accesses 53283305 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1563,86 +1555,86 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 27923 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27923 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1838 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 23508 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27923 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27923 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27923 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 25346 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28940.858518 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25854.889269 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 17791.815030 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 13319 52.55% 52.55% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11735 46.30% 98.85% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 221 0.87% 99.72% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 46 0.18% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 3 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 12 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 25346 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walks 27049 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27049 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1824 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22699 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27049 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27049 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27049 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24523 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 29055.621254 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 25956.010792 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 17576.904821 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 12420 50.65% 50.65% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 11833 48.25% 98.90% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 203 0.83% 99.73% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 48 0.20% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 7 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24523 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 23508 92.75% 92.75% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1838 7.25% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 25346 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 22699 92.56% 92.56% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1824 7.44% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24523 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27923 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27923 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27049 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27049 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 25346 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 25346 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 53269 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 67809364 # ITB inst hits -system.cpu2.itb.inst_misses 27923 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24523 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24523 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51572 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 67920418 # ITB inst hits +system.cpu2.itb.inst_misses 27049 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1188 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1186 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 6544 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 184 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 17096 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 6582 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 193 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16678 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 54805 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 53297 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 67837287 # ITB inst accesses -system.cpu2.itb.hits 67809364 # DTB hits -system.cpu2.itb.misses 27923 # DTB misses -system.cpu2.itb.accesses 67837287 # DTB accesses -system.cpu2.numCycles 6729019952 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 67947467 # ITB inst accesses +system.cpu2.itb.hits 67920418 # DTB hits +system.cpu2.itb.misses 27049 # DTB misses +system.cpu2.itb.accesses 67947467 # DTB accesses +system.cpu2.numCycles 6665733461 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 145507421 # Number of instructions committed -system.cpu2.committedOps 170762991 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 13321557 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1585 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 95906188119 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 46.245201 # CPI: cycles per instruction -system.cpu2.ipc 0.021624 # IPC: instructions per cycle +system.cpu2.committedInsts 145260015 # Number of instructions committed +system.cpu2.committedOps 170560320 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 13528820 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1578 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 95889999557 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 45.888288 # CPI: cycles per instruction +system.cpu2.ipc 0.021792 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 269790363 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 6459229589 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 72990389 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49393926 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3261178 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 49526964 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 35642873 # Number of BTB hits +system.cpu2.tickCycles 269818486 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 6395914975 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 73106744 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49439775 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3283160 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 49494170 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 35647247 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 71.966602 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9524201 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 103362 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 72.023123 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9537276 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 105421 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1672,85 +1664,85 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 500429 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 500429 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8187 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49422 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 313054 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 187375 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2308.042695 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 13865.789258 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-65535 186198 99.37% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-131071 657 0.35% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-196607 362 0.19% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-262143 70 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-327679 56 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walks 494727 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 494727 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8139 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49597 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 307402 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 187325 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2316.431336 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 13967.085425 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 186132 99.36% 99.36% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 667 0.36% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 353 0.19% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 78 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 59 0.03% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::327680-393215 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-458751 9 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-524287 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 187375 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 233412 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22762.724282 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18452.196764 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 18647.508849 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 228859 98.05% 98.05% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3345 1.43% 99.48% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 881 0.38% 99.86% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 33 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 195 0.08% 99.96% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 30 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 233412 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -23888540384 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean -0.243050 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -24451568384 102.36% 102.36% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 309528500 -1.30% 101.06% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 106605000 -0.45% 100.61% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 67439500 -0.28% 100.33% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 25633500 -0.11% 100.23% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 15083500 -0.06% 100.16% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 13632500 -0.06% 100.11% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 20996500 -0.09% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 3974500 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 102000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 25000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 6000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 1500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -23888540384 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 49422 85.79% 85.79% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8187 14.21% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 57609 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 500429 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 187325 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 229787 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 22726.216017 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 18353.180951 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 18914.444967 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-65535 225128 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3594 1.56% 99.54% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-196607 720 0.31% 99.85% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-262143 65 0.03% 99.88% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-327679 153 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 229787 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -29283845516 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.245317 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -29839367516 101.90% 101.90% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 306582000 -1.05% 100.85% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 107118000 -0.37% 100.48% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 65892000 -0.23% 100.26% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 24591000 -0.08% 100.18% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 14226000 -0.05% 100.13% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 14020500 -0.05% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 18907500 -0.06% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 4030000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 146000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 9000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -29283845516 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 49597 85.90% 85.90% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8139 14.10% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 57736 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 494727 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 500429 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 57609 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 494727 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 57736 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 57609 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 558038 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 57736 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 552463 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 58164219 # DTB read hits -system.cpu3.dtb.read_misses 342154 # DTB read misses -system.cpu3.dtb.write_hits 45137816 # DTB write hits -system.cpu3.dtb.write_misses 158275 # DTB write misses -system.cpu3.dtb.flush_tlb 1187 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 58246352 # DTB read hits +system.cpu3.dtb.read_misses 339748 # DTB read misses +system.cpu3.dtb.write_hits 45232753 # DTB write hits +system.cpu3.dtb.write_misses 154979 # DTB write misses +system.cpu3.dtb.flush_tlb 1185 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11250 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 304 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29745 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 69 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4820 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11213 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 305 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29617 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 79 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 4718 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 32652 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 58506373 # DTB read accesses -system.cpu3.dtb.write_accesses 45296091 # DTB write accesses +system.cpu3.dtb.perms_faults 32277 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 58586100 # DTB read accesses +system.cpu3.dtb.write_accesses 45387732 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 103302035 # DTB hits -system.cpu3.dtb.misses 500429 # DTB misses -system.cpu3.dtb.accesses 103802464 # DTB accesses +system.cpu3.dtb.hits 103479105 # DTB hits +system.cpu3.dtb.misses 494727 # DTB misses +system.cpu3.dtb.accesses 103973832 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1780,386 +1772,385 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 60030 # Table walker walks requested -system.cpu3.itb.walker.walksLong 60030 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1961 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41132 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8185 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 51845 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1585.842415 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 9699.543374 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 51363 99.07% 99.07% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 302 0.58% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 36 0.07% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 44 0.08% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 73 0.14% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 15 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walks 60127 # Table walker walks requested +system.cpu3.itb.walker.walksLong 60127 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1977 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41370 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8202 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51925 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1583.187289 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 9631.832849 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 51469 99.12% 99.12% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 278 0.54% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 39 0.08% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 41 0.08% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 70 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 14 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::262144-294911 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 51845 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 51278 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 29392.673271 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 24917.769531 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 21411.451197 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 50198 97.89% 97.89% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 365 0.71% 98.61% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-196607 621 1.21% 99.82% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 29 0.06% 99.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 49 0.10% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 9 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 51278 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -28186036180 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.973417 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.149857 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -706639900 2.51% 2.51% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -27517172780 97.63% 100.13% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 33476500 -0.12% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 3852500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 369000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 47500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::6 31000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -28186036180 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 41132 95.45% 95.45% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 1961 4.55% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 43093 # Table walker page sizes translated +system.cpu3.itb.walker.walkWaitTime::total 51925 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 51549 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 29040.146269 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 24568.436348 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 21519.136506 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-65535 50502 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-131071 358 0.69% 98.66% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-196607 600 1.16% 99.83% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-262143 30 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-327679 32 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 51549 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -29286303016 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.896957 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.299007 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2976637360 10.16% 10.16% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -26347752656 89.97% 100.13% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 35165500 -0.12% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 2840000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 71000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 10500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -29286303016 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 41370 95.44% 95.44% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 1977 4.56% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 43347 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60030 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60030 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60127 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60127 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43093 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43093 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 103123 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 52557456 # ITB inst hits -system.cpu3.itb.inst_misses 60030 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43347 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43347 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 103474 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 52640414 # ITB inst hits +system.cpu3.itb.inst_misses 60127 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1187 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1185 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11250 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 304 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 23210 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11213 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 305 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 23184 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 115031 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 115097 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 52617486 # ITB inst accesses -system.cpu3.itb.hits 52557456 # DTB hits -system.cpu3.itb.misses 60030 # DTB misses -system.cpu3.itb.accesses 52617486 # DTB accesses -system.cpu3.numCycles 367681719 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 52700541 # ITB inst accesses +system.cpu3.itb.hits 52640414 # DTB hits +system.cpu3.itb.misses 60127 # DTB misses +system.cpu3.itb.accesses 52700541 # DTB accesses +system.cpu3.numCycles 367415947 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 137382452 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 324487112 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 72990389 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45167074 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 207382227 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7378767 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1499130 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 9416 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 2414 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2929845 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 92895 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 5499 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 52424871 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2006412 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 23984 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 352993106 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.076120 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.324101 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 138047852 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 324925438 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 73106744 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45184523 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 206488551 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7421915 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1494390 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 8711 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1919 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2933513 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 92576 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 5529 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 52507671 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2023167 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 24008 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 352783845 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.078296 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.326372 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 272962947 77.33% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10013633 2.84% 80.16% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10141075 2.87% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7427569 2.10% 85.14% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15412828 4.37% 89.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5010537 1.42% 90.93% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5410828 1.53% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4793943 1.36% 93.82% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 21819746 6.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 272678491 77.29% 77.29% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 9999177 2.83% 80.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10154215 2.88% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7447502 2.11% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15397984 4.36% 89.48% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5025734 1.42% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5401897 1.53% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4807386 1.36% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 21871459 6.20% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 352993106 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.198515 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.882522 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 112311908 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 171536917 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 59078029 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7166258 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2898243 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 10967565 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 802193 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 354637256 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2468190 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 2898243 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 116412746 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 14091886 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 135873689 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 62053830 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 21660921 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 346387617 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 69362 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1230764 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 966889 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 11283496 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2101 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 331152482 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 530946274 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 409391445 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 488669 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 278384590 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 52767887 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 7985124 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6877230 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 39792362 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 55963963 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 47449628 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7288791 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 7899727 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 329013774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7979579 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 328894803 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 473789 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 44157935 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 28349943 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 195322 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 352993106 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.931732 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.657853 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 352783845 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.198975 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.884353 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 112906719 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 170627658 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 59194480 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7143620 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2909626 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 10993587 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 812434 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 355125435 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2492983 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 2909626 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 117007450 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 13956942 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 135354583 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 62147599 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 21405678 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 346848000 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 65680 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1218522 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 931993 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 11105485 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2097 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 331495484 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 531299079 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 409883872 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 498256 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 278579121 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 52916358 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7952838 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6842362 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39655118 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 56090576 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 47550992 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7265418 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 7939600 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 329496362 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7936863 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 329269236 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 468664 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 44300133 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 28411196 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 197124 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 352783845 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.933346 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.659424 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 225053646 63.76% 63.76% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 52887195 14.98% 78.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24125112 6.83% 85.57% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17152120 4.86% 90.43% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 12799961 3.63% 94.06% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9006883 2.55% 96.61% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6061659 1.72% 98.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3555429 1.01% 99.33% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2351101 0.67% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 224815035 63.73% 63.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 52801661 14.97% 78.69% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24147394 6.84% 85.54% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17186087 4.87% 90.41% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 12829115 3.64% 94.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9014914 2.56% 96.60% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6070700 1.72% 98.32% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3552216 1.01% 99.33% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2366723 0.67% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 352993106 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 352783845 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1666434 25.55% 25.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 16334 0.25% 25.81% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1493 0.02% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.83% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2666569 40.89% 66.72% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2170161 33.28% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1655726 25.42% 25.42% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 16802 0.26% 25.68% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1467 0.02% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2658135 40.82% 66.52% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2180482 33.48% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 222970071 67.79% 67.79% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 784272 0.24% 68.03% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 39650 0.01% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 183 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 1 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 1 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 42230 0.01% 68.06% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 59327329 18.04% 86.10% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 45731029 13.90% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 223168493 67.78% 67.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 780707 0.24% 68.01% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 40175 0.01% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 174 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 1 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 42531 0.01% 68.04% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 59412355 18.04% 86.08% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 45824773 13.92% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 328894803 # Type of FU issued -system.cpu3.iq.rate 0.894510 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6520991 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019827 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1017124188 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 381195731 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 316969788 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 653304 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 324459 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 290942 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 335066450 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 349307 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2611645 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 329269236 # Type of FU issued +system.cpu3.iq.rate 0.896176 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6512612 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019779 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1017639354 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 381768294 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 317351059 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 664239 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 330816 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 296027 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 335426759 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 355062 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2617033 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 8878101 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11627 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 374989 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4859757 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 8910571 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 11930 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 371819 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4873914 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2089653 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 4248814 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2093383 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 4209996 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2898243 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8732301 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 4121646 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 337068759 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 994758 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 55963963 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 47449628 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6728240 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 117681 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 3958014 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 374989 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1476989 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1294241 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 2771230 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 325158275 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 58155452 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3242017 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 2909626 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8686652 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 4058716 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 337508586 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 999497 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 56090576 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 47550992 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6693033 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 115188 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 3897473 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 371819 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1479948 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1304525 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 2784473 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 325518299 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 58237072 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3261982 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 75406 # number of nop insts executed -system.cpu3.iew.exec_refs 103291863 # number of memory reference insts executed -system.cpu3.iew.exec_branches 60348156 # Number of branches executed -system.cpu3.iew.exec_stores 45136411 # Number of stores executed -system.cpu3.iew.exec_rate 0.884347 # Inst execution rate -system.cpu3.iew.wb_sent 317931631 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 317260730 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 156804040 # num instructions producing a value -system.cpu3.iew.wb_consumers 272237503 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.862868 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.575983 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 44184156 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7784257 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2469882 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 345475115 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.847631 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.845112 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 75361 # number of nop insts executed +system.cpu3.iew.exec_refs 103468304 # number of memory reference insts executed +system.cpu3.iew.exec_branches 60421077 # Number of branches executed +system.cpu3.iew.exec_stores 45231232 # Number of stores executed +system.cpu3.iew.exec_rate 0.885967 # Inst execution rate +system.cpu3.iew.wb_sent 318319204 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 317647086 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 156971025 # num instructions producing a value +system.cpu3.iew.wb_consumers 272519290 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.864544 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576000 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 44325764 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7739739 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2481675 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 345244332 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.849060 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.846955 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 238965063 69.17% 69.17% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 51652898 14.95% 84.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18588674 5.38% 89.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8404155 2.43% 91.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6041826 1.75% 93.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3641114 1.05% 94.74% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3441360 1.00% 95.73% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2148532 0.62% 96.36% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12591493 3.64% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 238738698 69.15% 69.15% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 51567808 14.94% 84.09% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18622481 5.39% 89.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8388535 2.43% 91.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6065452 1.76% 93.67% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3663652 1.06% 94.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3429214 0.99% 95.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2148576 0.62% 96.34% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 12619916 3.66% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 345475115 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 249281112 # Number of instructions committed -system.cpu3.commit.committedOps 292835413 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 345244332 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 249501623 # Number of instructions committed +system.cpu3.commit.committedOps 293133087 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 89675732 # Number of memory references committed -system.cpu3.commit.loads 47085861 # Number of loads committed -system.cpu3.commit.membars 1972703 # Number of memory barriers committed -system.cpu3.commit.branches 55678709 # Number of branches committed -system.cpu3.commit.fp_insts 279951 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 269023900 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7382684 # Number of function calls committed. +system.cpu3.commit.refs 89857082 # Number of memory references committed +system.cpu3.commit.loads 47180004 # Number of loads committed +system.cpu3.commit.membars 1961101 # Number of memory barriers committed +system.cpu3.commit.branches 55730410 # Number of branches committed +system.cpu3.commit.fp_insts 284466 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 269318634 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7382541 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 202481834 69.15% 69.15% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 611500 0.21% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 29936 0.01% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 36411 0.01% 69.38% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 47085861 16.08% 85.46% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 42589871 14.54% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 202599565 69.12% 69.12% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 609386 0.21% 69.32% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 30413 0.01% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 36641 0.01% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 47180004 16.10% 85.44% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 42677078 14.56% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 292835413 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12591493 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 667852271 # The number of ROB reads -system.cpu3.rob.rob_writes 681568770 # The number of ROB writes -system.cpu3.timesIdled 2347442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 14688613 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98704312464 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 249281112 # Number of Instructions Simulated -system.cpu3.committedOps 292835413 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.474968 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.474968 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.677981 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.677981 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 383320839 # number of integer regfile reads -system.cpu3.int_regfile_writes 226802116 # number of integer regfile writes -system.cpu3.fp_regfile_reads 566354 # number of floating regfile reads -system.cpu3.fp_regfile_writes 353692 # number of floating regfile writes -system.cpu3.cc_regfile_reads 69391716 # number of cc regfile reads -system.cpu3.cc_regfile_writes 70028526 # number of cc regfile writes -system.cpu3.misc_regfile_reads 653217985 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7838267 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40272 # Transaction distribution -system.iobus.trans_dist::ReadResp 40272 # Transaction distribution -system.iobus.trans_dist::WriteReq 136541 # Transaction distribution -system.iobus.trans_dist::WriteResp 136541 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47702 # Packet count per connected master and slave (bytes) +system.cpu3.commit.op_class_0::total 293133087 # Class of committed instruction +system.cpu3.commit.bw_lim_events 12619916 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 668027626 # The number of ROB reads +system.cpu3.rob.rob_writes 682469296 # The number of ROB writes +system.cpu3.timesIdled 2366991 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 14632102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98631076285 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 249501623 # Number of Instructions Simulated +system.cpu3.committedOps 293133087 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.472599 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.472599 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.679071 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.679071 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 383683244 # number of integer regfile reads +system.cpu3.int_regfile_writes 227091338 # number of integer regfile writes +system.cpu3.fp_regfile_reads 575742 # number of floating regfile reads +system.cpu3.fp_regfile_writes 354224 # number of floating regfile writes +system.cpu3.cc_regfile_reads 69408942 # number of cc regfile reads +system.cpu3.cc_regfile_writes 70047711 # number of cc regfile writes +system.cpu3.misc_regfile_reads 653726404 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7798013 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40238 # Transaction distribution +system.iobus.trans_dist::ReadResp 40238 # Transaction distribution +system.iobus.trans_dist::WriteReq 136511 # Transaction distribution +system.iobus.trans_dist::WriteResp 136511 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2170,15 +2161,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29444 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122464 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353626 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47722 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2189,19 +2180,19 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155714 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 34502500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7491974 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 34324500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 217500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 218500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -2213,66 +2204,66 @@ system.iobus.reqLayer16.occupancy 5500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 12266000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13530000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21519500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21519000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 257935387 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 268744919 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 58894000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 59904000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 75406000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 77390000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115463 # number of replacements -system.iocache.tags.tagsinuse 10.424920 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.420604 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089166486009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544579 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.880341 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221536 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430021 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651557 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089166746509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547315 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.873289 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221707 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429581 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651288 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039686 # Number of tag accesses -system.iocache.tags.data_accesses 1039686 # Number of data accesses +system.iocache.tags.tag_accesses 1039650 # Number of tag accesses +system.iocache.tags.data_accesses 1039650 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8813 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8850 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses -system.iocache.demand_misses::total 8857 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8813 # number of demand (read+write) misses +system.iocache.demand_misses::total 8853 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8817 # number of overall misses -system.iocache.overall_misses::total 8857 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 1102393747 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1102393747 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 6261704640 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6261704640 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 1102393747 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1102393747 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 1102393747 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1102393747 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8813 # number of overall misses +system.iocache.overall_misses::total 8853 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 1097461741 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1097461741 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 6290187178 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 6290187178 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 1097461741 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1097461741 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 1097461741 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1097461741 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8813 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8853 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8813 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8853 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2286,507 +2277,506 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 125030.480549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124507.990400 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58704.948624 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 58704.948624 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125030.480549 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124465.817658 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125030.480549 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124465.817658 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 24279 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124527.600250 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124006.976384 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 58971.979093 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 58971.979093 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124527.600250 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123964.954366 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124527.600250 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123964.954366 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22895 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2397 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2302 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.128911 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.945699 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 5695 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 5695 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 48080 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 48080 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 5695 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 5695 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 5695 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 5695 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 817643747 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 817643747 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3857704640 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3857704640 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 817643747 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 817643747 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 817643747 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 817643747 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.645911 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.643212 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.450761 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.450761 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.645911 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.642994 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.645911 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.642994 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143572.211940 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 143572.211940 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.121464 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.121464 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 143572.211940 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 143572.211940 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 143572.211940 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 143572.211940 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 5727 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 5727 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 50000 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 50000 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 5727 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 5727 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 5727 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 5727 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 811111741 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 811111741 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3787932075 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3787932075 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 811111741 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 811111741 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 811111741 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 811111741 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.647119 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.468762 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.468762 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.646899 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.649835 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.646899 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141629.429195 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 141629.429195 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75758.641500 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75758.641500 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 141629.429195 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 141629.429195 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 141629.429195 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 141629.429195 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1138666 # number of replacements -system.l2c.tags.tagsinuse 65322.262178 # Cycle average of tags in use -system.l2c.tags.total_refs 47289153 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1201213 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 39.367833 # Average number of references to valid blocks. +system.l2c.tags.replacements 1134655 # number of replacements +system.l2c.tags.tagsinuse 65348.585655 # Cycle average of tags in use +system.l2c.tags.total_refs 47218951 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1196839 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 39.453052 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36868.228473 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 143.137292 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 207.018752 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3683.589947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 7937.199418 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 31.598194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 49.489312 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 262.199860 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1950.255648 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 35.983983 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 62.743334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1641.772402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3638.516325 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 77.227279 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 111.401868 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2775.336167 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 5846.563924 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562565 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002184 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003159 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.121112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000755 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.029759 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000549 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.055519 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001178 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.001700 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.042348 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.089211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996739 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62258 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 551 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2814 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5213 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53546 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.949982 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 418516157 # Number of tag accesses -system.l2c.tags.data_accesses 418516157 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 157261 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 108108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 55934 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 41818 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 153552 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 59055 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 287259 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 109772 # number of ReadReq hits -system.l2c.ReadReq_hits::total 972759 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7483477 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7483477 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15738935 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15738935 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3877 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1492 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2643 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9361 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 3 # number of SCUpgradeReq hits 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latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 141497.641688 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 79885.981877 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 130586.978719 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 139175.386967 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 155662.198631 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 28279.203651 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137466.165414 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138175.304878 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 131892.820210 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131875.995486 # average overall miss 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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68004.641568 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 68003.715105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67990.197069 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 69500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121288.223696 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 121612.571462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 137568.095751 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129060.004806 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121664.598488 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 123642.090178 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 125940.353712 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124478.624673 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122955.597426 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124607.135558 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 131162.508707 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 127798.817228 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 121183.044567 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 129538.717077 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 144620.782657 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 135710.541280 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121664.598488 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121886.916007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 123642.090178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 122790.392616 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 125940.353712 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 134747.989890 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 127965.608487 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 124001.187648 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127451.704545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121664.598488 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121886.916007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 127022.511848 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 125734.090909 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 123642.090178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 122790.392616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 126981.020607 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 126742.338252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 125940.353712 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 134747.989890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 127965.608487 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184921.266116 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 184405.592390 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 178362.970711 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 182512.969397 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 192061.533656 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190659.928748 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 183355.306810 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 188566.722273 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 188357.244852 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 187420.225474 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 180808.885111 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 185445.898815 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76742 # Transaction distribution -system.membus.trans_dist::ReadResp 436146 # Transaction distribution -system.membus.trans_dist::WriteReq 33651 # Transaction distribution -system.membus.trans_dist::WriteResp 33651 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1056828 # Transaction distribution -system.membus.trans_dist::CleanEvict 193864 # Transaction distribution -system.membus.trans_dist::UpgradeReq 34231 # Transaction distribution +system.membus.trans_dist::ReadReq 76702 # Transaction distribution +system.membus.trans_dist::ReadResp 435346 # Transaction distribution +system.membus.trans_dist::WriteReq 33616 # Transaction distribution +system.membus.trans_dist::WriteResp 33616 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1053198 # Transaction distribution +system.membus.trans_dist::CleanEvict 195936 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34438 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 34233 # Transaction distribution -system.membus.trans_dist::ReadExReq 881810 # Transaction distribution -system.membus.trans_dist::ReadExResp 881810 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 359404 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution +system.membus.trans_dist::ReadExReq 877665 # Transaction distribution +system.membus.trans_dist::ReadExResp 877665 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 358644 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 56664 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122464 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3762035 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3891446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4234133 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155714 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3728417 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3857678 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 295106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 295106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4152784 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155640 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13532 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139863648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 140033090 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7303808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7303808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 147336898 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1567 # Total snoops (count) -system.membus.snoop_fanout::samples 2745655 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139314336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 139483644 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7302016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 146785660 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1643 # Total snoops (count) +system.membus.snoop_fanout::samples 2736894 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2745655 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2736894 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2745655 # Request fanout histogram -system.membus.reqLayer0.occupancy 68555500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2736894 # Request fanout histogram +system.membus.reqLayer0.occupancy 69642000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1764002 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1869502 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3043978655 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3024540179 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2811928746 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2745498213 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 111188737 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 28895247 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3180,61 +3170,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 51453109 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26058247 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2315 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2315 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 51377281 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26019251 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1998 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1998 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1484473 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23684852 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33651 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33651 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 7933708 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15738935 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2275989 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 42908 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 42913 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1970952 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1970952 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15741997 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6463623 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1272073 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1223993 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47309096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29178438 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 818931 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1715075 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79021540 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2014946836 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1018609902 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2956128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6054072 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3042566938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1651979 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 38031624 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016505 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127406 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1480293 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23646990 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33616 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33616 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 7917317 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15707105 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2286569 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 43130 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43132 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1967850 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1967850 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15707694 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6464392 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1273831 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1223831 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47208661 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29171496 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 814900 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1708889 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 78903946 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2010714388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1017569896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2939088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6022496 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3037245868 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1649773 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37956541 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016464 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127251 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37403925 98.35% 98.35% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 627699 1.65% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37331626 98.35% 98.35% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 624915 1.65% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 38031624 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 30654168986 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 37956541 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 30638283989 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 845171 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 663187 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15236717928 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15222114677 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7805405781 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7813255878 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 292394209 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 290580214 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 700943896 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 698608876 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index a910c6b4e..d04b59f4b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.289328 # Number of seconds simulated -sim_ticks 51289327844000 # Number of ticks simulated -final_tick 51289327844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.408461 # Number of seconds simulated +sim_ticks 51408461373000 # Number of ticks simulated +final_tick 51408461373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135228 # Simulator instruction rate (inst/s) -host_op_rate 158909 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7809061274 # Simulator tick rate (ticks/s) -host_mem_usage 694320 # Number of bytes of host memory used -host_seconds 6567.93 # Real time elapsed on the host -sim_insts 888164103 # Number of instructions simulated -sim_ops 1043699308 # Number of ops (including micro ops) simulated +host_inst_rate 195616 # Simulator instruction rate (inst/s) +host_op_rate 229875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11322692573 # Simulator tick rate (ticks/s) +host_mem_usage 696388 # Number of bytes of host memory used +host_seconds 4540.30 # Real time elapsed on the host +sim_insts 888155433 # Number of instructions simulated +sim_ops 1043703833 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 136512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3641344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 41468960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 150528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 137472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3597568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 42676392 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428864 # Number of bytes read from this memory -system.physmem.bytes_read::total 92364360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3641344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3597568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7238912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78441216 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 142656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 137152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3491584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 41406368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 143936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 139584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3767424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 42881448 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 438400 # Number of bytes read from this memory +system.physmem.bytes_read::total 92548552 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3491584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3767424 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7259008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78363136 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78461796 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2133 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1980 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 56896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 647961 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2352 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2148 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56212 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 666823 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6701 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1443206 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1225644 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78383716 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2229 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 54556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 646983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2181 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58866 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 670027 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6850 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1446084 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1224424 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1228217 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 70996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 808530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70143 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 832072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1800849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70143 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 141139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1529387 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1226997 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 67918 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 805439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2800 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 73284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 834132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1800259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 67918 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 73284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141203 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1524324 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1529788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1529387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 808530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70143 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 832473 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3330637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1443206 # Number of read requests accepted -system.physmem.writeReqs 1228217 # Number of write requests accepted -system.physmem.readBursts 1443206 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1228217 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 92312576 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 52608 # Total number of bytes read from write queue -system.physmem.bytesWritten 78461696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 92364360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78461796 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 822 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::cpu1.data 400 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1524724 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1524324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 67918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 805439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2800 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 73284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 834532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3324983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1446084 # Number of read requests accepted +system.physmem.writeReqs 1226997 # Number of write requests accepted +system.physmem.readBursts 1446084 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1226997 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 92503744 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 45632 # Total number of bytes read from write queue +system.physmem.bytesWritten 78384064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 92548552 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78383716 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 713 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 356478 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 87850 # Per bank write bursts -system.physmem.perBankRdBursts::1 89651 # Per bank write bursts -system.physmem.perBankRdBursts::2 87083 # Per bank write bursts -system.physmem.perBankRdBursts::3 86997 # Per bank write bursts -system.physmem.perBankRdBursts::4 87338 # Per bank write bursts -system.physmem.perBankRdBursts::5 97616 # Per bank write bursts -system.physmem.perBankRdBursts::6 89147 # Per bank write bursts -system.physmem.perBankRdBursts::7 87735 # Per bank write bursts -system.physmem.perBankRdBursts::8 84823 # Per bank write bursts -system.physmem.perBankRdBursts::9 114942 # Per bank write bursts -system.physmem.perBankRdBursts::10 92351 # Per bank write bursts -system.physmem.perBankRdBursts::11 95964 # Per bank write bursts -system.physmem.perBankRdBursts::12 83458 # Per bank write bursts -system.physmem.perBankRdBursts::13 87171 # Per bank write bursts -system.physmem.perBankRdBursts::14 84360 # Per bank write bursts -system.physmem.perBankRdBursts::15 85898 # Per bank write bursts -system.physmem.perBankWrBursts::0 74977 # Per bank write bursts -system.physmem.perBankWrBursts::1 75819 # Per bank write bursts -system.physmem.perBankWrBursts::2 74752 # Per bank write bursts -system.physmem.perBankWrBursts::3 76261 # Per bank write bursts -system.physmem.perBankWrBursts::4 75660 # Per bank write bursts -system.physmem.perBankWrBursts::5 82258 # Per bank write bursts -system.physmem.perBankWrBursts::6 76272 # Per bank write bursts -system.physmem.perBankWrBursts::7 77177 # Per bank write bursts -system.physmem.perBankWrBursts::8 74263 # Per bank write bursts -system.physmem.perBankWrBursts::9 81618 # Per bank write bursts -system.physmem.perBankWrBursts::10 78101 # Per bank write bursts -system.physmem.perBankWrBursts::11 81113 # Per bank write bursts -system.physmem.perBankWrBursts::12 72977 # Per bank write bursts -system.physmem.perBankWrBursts::13 75983 # Per bank write bursts -system.physmem.perBankWrBursts::14 73541 # Per bank write bursts -system.physmem.perBankWrBursts::15 75192 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 88572 # Per bank write bursts +system.physmem.perBankRdBursts::1 91936 # Per bank write bursts +system.physmem.perBankRdBursts::2 86142 # Per bank write bursts +system.physmem.perBankRdBursts::3 85794 # Per bank write bursts +system.physmem.perBankRdBursts::4 86883 # Per bank write bursts +system.physmem.perBankRdBursts::5 96343 # Per bank write bursts +system.physmem.perBankRdBursts::6 89494 # Per bank write bursts +system.physmem.perBankRdBursts::7 87879 # Per bank write bursts +system.physmem.perBankRdBursts::8 83471 # Per bank write bursts +system.physmem.perBankRdBursts::9 112607 # Per bank write bursts +system.physmem.perBankRdBursts::10 93875 # Per bank write bursts +system.physmem.perBankRdBursts::11 93808 # Per bank write bursts +system.physmem.perBankRdBursts::12 88268 # Per bank write bursts +system.physmem.perBankRdBursts::13 91281 # Per bank write bursts +system.physmem.perBankRdBursts::14 84984 # Per bank write bursts +system.physmem.perBankRdBursts::15 84034 # Per bank write bursts +system.physmem.perBankWrBursts::0 75348 # Per bank write bursts +system.physmem.perBankWrBursts::1 77371 # Per bank write bursts +system.physmem.perBankWrBursts::2 73838 # Per bank write bursts +system.physmem.perBankWrBursts::3 75932 # Per bank write bursts +system.physmem.perBankWrBursts::4 75756 # Per bank write bursts +system.physmem.perBankWrBursts::5 80933 # Per bank write bursts +system.physmem.perBankWrBursts::6 75453 # Per bank write bursts +system.physmem.perBankWrBursts::7 77252 # Per bank write bursts +system.physmem.perBankWrBursts::8 72443 # Per bank write bursts +system.physmem.perBankWrBursts::9 79503 # Per bank write bursts +system.physmem.perBankWrBursts::10 78639 # Per bank write bursts +system.physmem.perBankWrBursts::11 80056 # Per bank write bursts +system.physmem.perBankWrBursts::12 76299 # Per bank write bursts +system.physmem.perBankWrBursts::13 79068 # Per bank write bursts +system.physmem.perBankWrBursts::14 73755 # Per bank write bursts +system.physmem.perBankWrBursts::15 73105 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 51289326709500 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 51408460130000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1443191 # Read request sizes (log2) +system.physmem.readPktSize::6 1446069 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1225644 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 662564 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 216343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 159104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 787 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1224424 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 664932 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 398664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 216465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 159288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 882 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 572 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1228 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 757 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 385 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -165,180 +165,185 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 753 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 30025 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 43300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 73608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 74875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 75340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 78249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 77578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 77941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 84747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 79458 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 91879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 76400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 80241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 72208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1062 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 56 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 565463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.007183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.069104 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 331.382789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 226805 40.11% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 129321 22.87% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55220 9.77% 72.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26563 4.70% 77.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 23290 4.12% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13002 2.30% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13617 2.41% 86.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9017 1.59% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 68628 12.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 565463 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 70251 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.531565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 230.543084 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 70246 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::11 762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 31810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 43103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 72394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 72889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 73918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 75976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 75696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 81917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 79068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 92468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 101068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 77598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 81385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 73598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563019 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.519817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.962282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.070466 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 224938 39.95% 39.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 128250 22.78% 62.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55139 9.79% 72.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26598 4.72% 77.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23698 4.21% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13004 2.31% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13485 2.40% 86.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9030 1.60% 87.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 68877 12.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563019 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.665075 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 231.098088 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 69936 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 70251 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 70251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.451196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.927151 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.708530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 38 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 20 0.03% 0.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 12 0.02% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 64 0.09% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 66179 94.20% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1570 2.23% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 250 0.36% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 470 0.67% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 89 0.13% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 339 0.48% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 221 0.31% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.06% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 76 0.11% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 130 0.19% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 30 0.04% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 31 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 448 0.64% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.05% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 123 0.18% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 30 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 70251 # Writes before turning the bus around for reads -system.physmem.totQLat 41993928125 # Total ticks spent queuing -system.physmem.totMemAccLat 69038628125 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7211920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29114.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 69941 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69941 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.511202 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.923338 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 7.360496 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 37 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 29 0.04% 0.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 15 0.02% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 59 0.08% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 66137 94.56% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1542 2.20% 96.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 224 0.32% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 273 0.39% 97.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 66 0.09% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 90 0.13% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 208 0.30% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 42 0.06% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 345 0.49% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 68 0.10% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 33 0.05% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 68 0.10% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 312 0.45% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 25 0.04% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 24 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 113 0.16% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.24% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 25 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69941 # Writes before turning the bus around for reads +system.physmem.totQLat 42029385276 # Total ticks spent queuing +system.physmem.totMemAccLat 69130091526 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7226855000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29078.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47864.25 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 47828.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.53 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.56 # Average write queue length when enqueuing -system.physmem.readRowHits 1183273 # Number of row buffer hits during reads -system.physmem.writeRowHits 919611 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.01 # Row buffer hit rate for writes -system.physmem.avgGap 19199253.25 # Average gap between requests -system.physmem.pageHitRate 78.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2152490760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1174474125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5564652600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3973380480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3349969140960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1239658923690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29686172799750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34288665862365 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.534207 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49385348498815 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712663160000 # Time in different power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.08 # Average write queue length when enqueuing +system.physmem.readRowHits 1187061 # Number of row buffer hits during reads +system.physmem.writeRowHits 920040 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 19231912.59 # Average gap between requests +system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2145112200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1170448125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5561735400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3965001840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3357750617520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1242334329840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29755308399000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34368235643925 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.532696 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49500352455310 # Time in different power states +system.physmem_0.memoryStateTime::REF 1716641420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 191309868685 # Time in different power states +system.physmem_0.memoryStateTime::ACT 191465063440 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2122409520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1158060750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 5685895800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3970866240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3349969140960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1241047287225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29684954937000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34288908597495 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.538939 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49383290725827 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712663160000 # Time in different power states +system.physmem_1.actEnergy 2111311440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1152005250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 5712111600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3971384640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3357750617520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1241846921700 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29755735950000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34368280302150 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.533565 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49501052297586 # Time in different power states +system.physmem_1.memoryStateTime::REF 1716641420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 193373338673 # Time in different power states +system.physmem_1.memoryStateTime::ACT 190767036414 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -368,15 +373,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 128583219 # Number of BP lookups -system.cpu0.branchPred.condPredicted 87130706 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5608498 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 87627947 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 62974583 # Number of BTB hits +system.cpu0.branchPred.lookups 131317234 # Number of BP lookups +system.cpu0.branchPred.condPredicted 89033308 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5711784 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 89061890 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 64034993 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.865866 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 16935709 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187300 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.899432 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17159386 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 186222 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -407,87 +412,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 888652 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 888652 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16421 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 87809 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 549489 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 339163 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2672.191542 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 16085.449478 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 336454 99.20% 99.20% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1394 0.41% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 896 0.26% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 159 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 148 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 39 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 31 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 339163 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 409656 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22857.613461 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18421.045367 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19320.142266 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 401054 97.90% 97.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6459 1.58% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1486 0.36% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 99 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 354 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 127 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 51 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 409656 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 372489857920 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.125711 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.685370 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 371484178920 99.73% 99.73% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 543967500 0.15% 99.88% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 197972000 0.05% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 122397500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 45621000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 26772000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 27386500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 35231000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 5712500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 472000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 66500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 35000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 45500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 372489857920 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 87810 84.25% 84.25% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 16421 15.75% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 104231 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 888652 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 882165 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 882165 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16962 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90283 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 541135 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 341030 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2470.671202 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14842.312664 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 338635 99.30% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1231 0.36% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 836 0.25% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 125 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 123 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 27 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 341030 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 406695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23181.687751 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18594.894940 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 20266.186322 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 397583 97.76% 97.76% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6749 1.66% 99.42% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1620 0.40% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 348 0.09% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 158 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 81 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 17 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 406695 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 362445074540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.202763 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.718091 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 361444437540 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 559911000 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 188863000 0.05% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 117378000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 44663000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 25341500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26888500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 30794500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6481000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 299000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 3500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 362445074540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90283 84.18% 84.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16962 15.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107245 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 882165 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 888652 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104231 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 882165 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107245 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104231 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 992883 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 989410 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 102519767 # DTB read hits -system.cpu0.dtb.read_misses 608916 # DTB read misses -system.cpu0.dtb.write_hits 79730858 # DTB write hits -system.cpu0.dtb.write_misses 279736 # DTB write misses -system.cpu0.dtb.flush_tlb 1105 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 104764153 # DTB read hits +system.cpu0.dtb.read_misses 607812 # DTB read misses +system.cpu0.dtb.write_hits 82241693 # DTB write hits +system.cpu0.dtb.write_misses 274353 # DTB write misses +system.cpu0.dtb.flush_tlb 1109 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21393 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 535 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55242 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 209 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9412 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21084 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 563 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 55854 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 162 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9058 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56039 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 103128683 # DTB read accesses -system.cpu0.dtb.write_accesses 80010594 # DTB write accesses +system.cpu0.dtb.perms_faults 56832 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 105371965 # DTB read accesses +system.cpu0.dtb.write_accesses 82516046 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 182250625 # DTB hits -system.cpu0.dtb.misses 888652 # DTB misses -system.cpu0.dtb.accesses 183139277 # DTB accesses +system.cpu0.dtb.hits 187005846 # DTB hits +system.cpu0.dtb.misses 882165 # DTB misses +system.cpu0.dtb.accesses 187888011 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -517,824 +524,838 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 102152 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102152 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3042 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68901 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14128 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88024 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1905.912024 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 12139.697138 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-65535 87548 99.46% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-131071 189 0.21% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-196607 243 0.28% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-262143 22 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-327679 18 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88024 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86071 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 29335.746070 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24303.412638 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 23702.116672 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84000 97.59% 97.59% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 669 0.78% 98.37% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1177 1.37% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 63 0.07% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 107 0.12% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86071 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 290883014796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.826730 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -240403892944 -82.65% -82.65% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 531218150240 182.62% 99.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 61167000 0.02% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 6375000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 1069000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 146500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 290883014796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 68901 95.77% 95.77% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3042 4.23% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 71943 # Table walker page sizes translated +system.cpu0.itb.walker.walks 108290 # Table walker walks requested +system.cpu0.itb.walker.walksLong 108290 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3192 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 74908 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 14795 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 93495 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1790.395208 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11668.511629 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 92494 98.93% 98.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 513 0.55% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 98 0.10% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 116 0.12% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 207 0.22% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 24 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 93495 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 92895 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29889.315894 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24974.829894 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 23485.865012 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 49009 52.76% 52.76% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 41574 44.75% 97.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 612 0.66% 98.17% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 79 0.09% 98.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 1038 1.12% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 333 0.36% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 46 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 56 0.06% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 94 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 13 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 15 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 12 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 92895 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 289428770008 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.837978 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -242453514464 -83.77% -83.77% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 531809766472 183.74% 99.97% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 64887000 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6499500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 871000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 248000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 12500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 289428770008 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 74908 95.91% 95.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 3192 4.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 78100 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102152 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102152 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108290 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108290 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71943 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71943 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 174095 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 92233828 # ITB inst hits -system.cpu0.itb.inst_misses 102152 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 186390 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 94461785 # ITB inst hits +system.cpu0.itb.inst_misses 108290 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1105 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1109 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21393 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 535 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40730 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21084 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 563 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41856 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204444 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 202434 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 92335980 # ITB inst accesses -system.cpu0.itb.hits 92233828 # DTB hits -system.cpu0.itb.misses 102152 # DTB misses -system.cpu0.itb.accesses 92335980 # DTB accesses -system.cpu0.numCycles 692838439 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 94570075 # ITB inst accesses +system.cpu0.itb.hits 94461785 # DTB hits +system.cpu0.itb.misses 108290 # DTB misses +system.cpu0.itb.accesses 94570075 # DTB accesses +system.cpu0.numCycles 692991159 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 240908960 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 572231445 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 128583219 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 79910292 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 408388774 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 12834591 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2570044 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 24306 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 5220 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5457264 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 161454 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 3138 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 92012846 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3478486 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41135 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 663936181 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.010011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.263466 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 244811791 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 585398201 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 131317234 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81194379 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 404384012 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13047908 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2817091 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21621 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 5789 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5286158 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 175205 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 3136 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 94240840 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3527611 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 42921 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 664028482 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.032942 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.287290 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 522394328 78.68% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 17725810 2.67% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 17688411 2.66% 84.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13071873 1.97% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28203827 4.25% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8736087 1.32% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9493633 1.43% 92.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8170343 1.23% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 38451869 5.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 519576745 78.25% 78.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18052759 2.72% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18229592 2.75% 83.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13406945 2.02% 85.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28061689 4.23% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8964232 1.35% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9738895 1.47% 92.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8312010 1.25% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39685615 5.98% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 663936181 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.185589 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.825923 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 195480668 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 347525883 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 102363007 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13531611 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5032846 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19144374 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1404061 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 624972262 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4324699 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5032846 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 202972273 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 31908208 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 264942356 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 108280793 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 50797146 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 610471334 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 95561 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2181622 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1833281 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31100121 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3748 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 584763041 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 944825531 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 722111361 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 774403 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 494202829 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 90560207 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15441984 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13500490 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 76181815 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 97914623 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 83796282 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13494788 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14509188 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 578969956 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15549087 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 581387385 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 830768 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 76282364 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 48796155 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 362907 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 663936181 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.875668 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.614381 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 664028482 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189493 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.844741 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 199609312 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 340272761 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105735491 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13276963 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5131471 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19616175 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1412684 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 640319872 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4351333 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5131471 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 207083748 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 31652470 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 258696093 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111398501 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 50063478 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 625547022 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 86953 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2120320 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1651060 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 31054223 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 4011 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 597792979 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 961356441 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 739385367 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 793267 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 505102127 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 92690852 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14931756 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12960965 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 74096600 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 100382456 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86370742 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13395217 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14366752 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 594049171 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14966536 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 595443977 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 833379 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 77816816 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 49417916 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 356669 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 664028482 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.896715 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.636729 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 434128190 65.39% 65.39% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 98370789 14.82% 80.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 42377650 6.38% 86.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30067622 4.53% 91.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22403128 3.37% 94.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 15594972 2.35% 96.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10621983 1.60% 98.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6235616 0.94% 99.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4136231 0.62% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 431629347 65.00% 65.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 97195183 14.64% 79.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43390380 6.53% 86.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 30835149 4.64% 90.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23006785 3.46% 94.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16163925 2.43% 96.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 10905989 1.64% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6533904 0.98% 99.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4367820 0.66% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 663936181 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 664028482 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2959786 25.50% 25.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 23278 0.20% 25.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2380 0.02% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4810604 41.45% 67.18% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3809012 32.82% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3037620 25.70% 25.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 25191 0.21% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2899 0.02% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4781762 40.45% 66.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3973331 33.61% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 394568235 67.87% 67.87% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1380833 0.24% 68.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65255 0.01% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 66 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 59226 0.01% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 104545250 17.98% 86.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 80768506 13.89% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 44 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 403794947 67.81% 67.81% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1402722 0.24% 68.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 64715 0.01% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 26 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 70887 0.01% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 106816149 17.94% 86.01% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 83294486 13.99% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 581387385 # Type of FU issued -system.cpu0.iq.rate 0.839138 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11605060 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019961 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1838113951 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 670976650 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 559986003 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1032828 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 510697 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 459801 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 592439966 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 552468 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4598569 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 595443977 # Type of FU issued +system.cpu0.iq.rate 0.859237 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11820804 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019852 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1866487578 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 687019560 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 573922610 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1083041 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 536746 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 483014 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 606686496 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 578241 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4705214 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 15443537 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 19687 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 696908 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8570730 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 15648573 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20037 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 735656 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8693789 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3841968 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8263079 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3938518 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7949396 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5032846 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 16244018 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 13852341 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 594652790 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1703484 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 97914623 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 83796282 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13208370 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 224559 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13543277 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 696908 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2523457 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2209016 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4732473 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 575002762 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 102511874 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5508716 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5131471 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 16124670 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 13736061 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 609148290 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1755735 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 100382456 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86370742 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12679523 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 224965 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13426906 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 735656 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2579656 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2261003 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4840659 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 588863732 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 104752148 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5709737 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 133747 # number of nop insts executed -system.cpu0.iew.exec_refs 182243986 # number of memory reference insts executed -system.cpu0.iew.exec_branches 106498541 # Number of branches executed -system.cpu0.iew.exec_stores 79732112 # Number of stores executed -system.cpu0.iew.exec_rate 0.829923 # Inst execution rate -system.cpu0.iew.wb_sent 561628821 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 560445804 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 276455484 # num instructions producing a value -system.cpu0.iew.wb_consumers 480133798 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.808913 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575788 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 76323092 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15186180 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4223774 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 650882635 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.796206 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.791535 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 132583 # number of nop insts executed +system.cpu0.iew.exec_refs 186992207 # number of memory reference insts executed +system.cpu0.iew.exec_branches 108909859 # Number of branches executed +system.cpu0.iew.exec_stores 82240059 # Number of stores executed +system.cpu0.iew.exec_rate 0.849742 # Inst execution rate +system.cpu0.iew.wb_sent 575604648 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 574405624 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 283543762 # num instructions producing a value +system.cpu0.iew.wb_consumers 491943015 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.828879 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576375 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 77856968 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14609867 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4319026 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 650724527 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.816319 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.818422 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 459027992 70.52% 70.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 95977430 14.75% 85.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32265262 4.96% 90.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 14738583 2.26% 92.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10675615 1.64% 94.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6384145 0.98% 95.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 5905756 0.91% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3807566 0.58% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22100286 3.40% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 457095790 70.24% 70.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 94826206 14.57% 84.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 32956684 5.06% 89.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15335469 2.36% 92.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10858481 1.67% 93.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6641395 1.02% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6158141 0.95% 95.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3955723 0.61% 96.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22896638 3.52% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 650882635 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 440797694 # Number of instructions committed -system.cpu0.commit.committedOps 518236674 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 650724527 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 451838462 # Number of instructions committed +system.cpu0.commit.committedOps 531198891 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 157696637 # Number of memory references committed -system.cpu0.commit.loads 82471085 # Number of loads committed -system.cpu0.commit.membars 3674667 # Number of memory barriers committed -system.cpu0.commit.branches 98481561 # Number of branches committed -system.cpu0.commit.fp_insts 441323 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 475654398 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13113007 # Number of function calls committed. +system.cpu0.commit.refs 162410836 # Number of memory references committed +system.cpu0.commit.loads 84733883 # Number of loads committed +system.cpu0.commit.membars 3641724 # Number of memory barriers committed +system.cpu0.commit.branches 100706106 # Number of branches committed +system.cpu0.commit.fp_insts 463962 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 487973755 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13314640 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 359364507 69.34% 69.34% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1076711 0.21% 69.55% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48368 0.01% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 50451 0.01% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 82471085 15.91% 85.48% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 75225552 14.52% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 367585865 69.20% 69.20% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1092900 0.21% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48363 0.01% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 60927 0.01% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84733883 15.95% 85.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77676953 14.62% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 518236674 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22100286 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1219379931 # The number of ROB reads -system.cpu0.rob.rob_writes 1202193257 # The number of ROB writes -system.cpu0.timesIdled 4085117 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28902258 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 52406782764 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 440797694 # Number of Instructions Simulated -system.cpu0.committedOps 518236674 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.571783 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.571783 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.636220 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.636220 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 678374188 # number of integer regfile reads -system.cpu0.int_regfile_writes 399817042 # number of integer regfile writes -system.cpu0.fp_regfile_reads 838109 # number of floating regfile reads -system.cpu0.fp_regfile_writes 474946 # number of floating regfile writes -system.cpu0.cc_regfile_reads 123617139 # number of cc regfile reads -system.cpu0.cc_regfile_writes 124729221 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1203854145 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15290594 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10436084 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.972968 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 299959666 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10436596 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.741140 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 531198891 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22896638 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1233051269 # The number of ROB reads +system.cpu0.rob.rob_writes 1231435060 # The number of ROB writes +system.cpu0.timesIdled 4157054 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28962677 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 49016383217 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 451838462 # Number of Instructions Simulated +system.cpu0.committedOps 531198891 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.533714 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.533714 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.652012 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.652012 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 694247819 # number of integer regfile reads +system.cpu0.int_regfile_writes 410288637 # number of integer regfile writes +system.cpu0.fp_regfile_reads 858111 # number of floating regfile reads +system.cpu0.fp_regfile_writes 534016 # number of floating regfile writes +system.cpu0.cc_regfile_reads 125553876 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126720582 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1210004868 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14749855 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10444529 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.973029 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 299923189 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10445041 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.714410 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 279.244386 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 232.728582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.545399 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.454548 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 311.726470 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 200.246559 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.608841 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.391107 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1323106613 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1323106613 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77963580 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80269235 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 158232815 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 65859782 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67602913 # number of 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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18081.464497 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17789.136341 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43385.744365 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44347.595063 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43848.648663 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 71303.900116 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 76717.178017 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 74041.466406 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13477.623651 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14134.402297 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13808.317745 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33571.428571 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 41700 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 36958.333333 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30762.590162 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31092.612904 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 30924.202256 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29223.655986 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 29635.550847 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 29425.018590 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 88195384 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 113546 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3493866 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1091 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25.242921 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 104.075160 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.077629 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.080971 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.079268 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.081198 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.084603 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.082867 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17241.229516 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18286.375379 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17768.284819 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44850.241418 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42777.306616 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43818.871747 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 72149.321767 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 75560.284475 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 73908.492155 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13693.617559 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14010.475196 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13843.498505 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 33071.428571 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 47875 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 38454.545455 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31253.922197 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 30551.263373 # average overall miss latency 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number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8003169 # number of writebacks -system.cpu0.dcache.writebacks::total 8003169 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3436866 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3393684 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 6830550 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5461090 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5053042 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10514132 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3543 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3329 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 6872 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 197755 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 200626 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 398381 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 8897956 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 8446726 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 17344682 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 8897956 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 8446726 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 17344682 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2807485 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2807680 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5615165 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1100157 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1034244 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2134401 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660963 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 593397 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1254360 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 607866 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 622214 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 1230080 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123410 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 125079 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 248489 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 8006090 # number of writebacks +system.cpu0.dcache.writebacks::total 8006090 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3375063 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3454629 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6829692 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5283356 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5238971 # number of WriteReq MSHR hits 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number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 596274 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 635031 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1231305 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129459 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 117832 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 247291 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 3907642 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 3841924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 7749566 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4568605 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 4435321 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 9003926 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16017 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17661 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 14689 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 19007 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 30706 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 36668 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48229998000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49964907000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98194905000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 50851143254 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 48166542964 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 99017686218 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13581281500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11177477000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24758758500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 42782526766 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 47168374188 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 89950900954 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1714638000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1879552500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3594190500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 228000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 203500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 431500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99081141254 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 98131449964 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 197212591218 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112662422754 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 109308926964 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 221971349718 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2884316000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3346437000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6230753000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2757806500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3449966491 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6207772991 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5642122500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6796403491 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12438525991 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033340 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015191 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014035 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014608 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750831 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.742547 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746889 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.774491 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.800402 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787384 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059567 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060233 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3873914 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3883262 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7757176 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4506031 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4506299 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9012330 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15173 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 18510 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33683 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 14392 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 19307 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33699 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 29565 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 37817 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67382 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47767699000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 50570666500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98338365500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 51048745765 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 47967542154 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 99016287919 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12938219500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11970277000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24908496500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 42479134250 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 47413708556 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 89892842806 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1851393500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1735514500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3586908000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 224500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 187500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 98816444765 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 98538208654 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 197354653419 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111754664265 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110508485654 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 222263149919 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2756867500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3474155500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6231023000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2706893000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3501005491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6207898491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5463760500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6975160991 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12438921491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032930 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014385 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014880 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014626 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.744068 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749436 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746723 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.771883 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.803397 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787821 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062538 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057248 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059901 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024948 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023988 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024463 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029005 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027555 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028273 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17179.075935 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17795.798310 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17487.447831 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46221.714950 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46571.740290 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46391.323007 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20547.718254 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18836.423170 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19738.160098 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 70381.509685 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 75807.317399 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73126.057617 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13893.833563 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15026.922985 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14464.183525 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32571.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 40700 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 35958.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25355.736594 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25542.267355 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25448.211063 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24660.136465 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24645.099411 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24652.729234 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180078.416682 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 189481.739426 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185009.590831 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187746.374838 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181510.311517 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184228.780597 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 183746.580473 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185349.718856 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184619.081411 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023996 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025001 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024489 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027766 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028858 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028301 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17080.614946 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17908.550556 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17496.587984 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47385.337906 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45276.574241 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46339.777521 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20468.077112 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19212.786721 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19844.972410 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 71240.963466 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 74663.612573 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 73006.154288 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14301.002634 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14728.719703 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.806079 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 32071.428571 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 46875 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 37454.545455 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25508.166873 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25375.112123 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25441.559328 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24801.130810 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24523.114346 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24662.118444 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181695.610624 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187690.734738 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184990.143396 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 188083.171206 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181333.479619 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184216.104068 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184805.022831 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 184445.117037 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184603.031833 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 15974128 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.921242 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 168806839 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15974640 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.567176 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 16002915 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.921323 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 168727471 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16003427 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.543209 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 23708267500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 281.088545 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 230.832697 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.549001 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.450845 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 280.765706 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 231.155617 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.548371 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.451476 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 201986364 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 201986364 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 83405429 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 85401410 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 168806839 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 83405429 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 85401410 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 168806839 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 83405429 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 85401410 # number of overall hits -system.cpu0.icache.overall_hits::total 168806839 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8594272 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8610485 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17204757 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8594272 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8610485 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17204757 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8594272 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8610485 # number of overall misses -system.cpu0.icache.overall_misses::total 17204757 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115674670362 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116624708317 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 232299378679 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 115674670362 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 116624708317 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 232299378679 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 115674670362 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 116624708317 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 232299378679 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91999701 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 94011895 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 186011596 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91999701 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 94011895 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 186011596 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91999701 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 94011895 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 186011596 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.093416 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091589 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092493 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.093416 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091589 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092493 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.093416 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091589 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092493 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13459.507724 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13544.499330 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13502.043573 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13459.507724 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13544.499330 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13502.043573 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13459.507724 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13544.499330 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13502.043573 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 130388 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 201964404 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 201964404 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 85532749 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 83194722 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 168727471 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 85532749 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 83194722 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 168727471 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 85532749 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 83194722 # number of overall hits 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of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 232789634196 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 116564920862 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 116224713334 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 232789634196 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 116564920862 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 116224713334 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 232789634196 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 94227691 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 91733140 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 185960831 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 94227691 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 91733140 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 185960831 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 94227691 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 91733140 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 185960831 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.093079 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.092672 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092276 # miss rate for demand accesses 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# average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13406.060772 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13611.972772 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13508.081662 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 124982 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8896 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 8393 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.656924 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.891219 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 15974128 # number of writebacks -system.cpu0.icache.writebacks::total 15974128 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 611973 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 618016 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1229989 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 611973 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 618016 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1229989 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 611973 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 618016 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1229989 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 7982299 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7992469 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 15974768 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 7982299 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 7992469 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 15974768 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 7982299 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 7992469 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 15974768 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 16002915 # number of writebacks +system.cpu0.icache.writebacks::total 16002915 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 618920 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 610867 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1229787 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 618920 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 610867 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1229787 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 618920 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 610867 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1229787 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8076022 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7927551 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16003573 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8076022 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 7927551 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16003573 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8076022 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 7927551 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16003573 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102168974407 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102903128872 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 205072103279 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102168974407 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102903128872 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 205072103279 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102168974407 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102903128872 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 205072103279 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 102996587403 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 102473648883 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 205470236286 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 102996587403 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 102473648883 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 205470236286 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 102996587403 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 102473648883 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 205470236286 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960890000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636383000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960890000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636383000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086764 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085016 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085880 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086764 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085016 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085880 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086764 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085016 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085880 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12799.442167 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12875.011323 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12837.250799 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12799.442167 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12875.011323 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12837.250799 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12799.442167 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12875.011323 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12837.250799 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086059 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086059 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085708 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.086420 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086059 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12839.022654 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12839.022654 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12753.381232 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12926.268009 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12839.022654 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency @@ -1342,15 +1363,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 130968102 # Number of BP lookups -system.cpu1.branchPred.condPredicted 88970124 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5750252 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 89023495 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 63858591 # Number of BTB hits +system.cpu1.branchPred.lookups 128216560 # Number of BP lookups +system.cpu1.branchPred.condPredicted 87052179 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5647036 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87531901 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 62765206 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.732289 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16978119 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 186369 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 71.705521 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16746465 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188086 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1380,94 +1401,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 886500 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 886500 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16614 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90854 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 546971 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 339529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2635.682077 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15582.194898 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 331369 97.60% 97.60% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 5485 1.62% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 837 0.25% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 574 0.17% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 696 0.20% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 183 0.05% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 92 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 51 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 111 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 21 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 9 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 6 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 19 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-491519 24 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::491520-524287 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 339529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 415382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23662.319263 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 19025.805885 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20147.084285 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 405553 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7307 1.76% 99.39% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1720 0.41% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 155 0.04% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 425 0.10% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 150 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 57 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 415382 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 346321236644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.073903 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.674380 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 345291497644 99.70% 99.70% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 564895000 0.16% 99.87% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 201129000 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 122101500 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 48136500 0.01% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 26097000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 27118000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 32649000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 7117000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 414500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 28000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 21500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 2000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 346321236644 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 90854 84.54% 84.54% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 16614 15.46% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 107468 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886500 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 886664 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 886664 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16465 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89324 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 548056 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 338608 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2680.249728 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15884.122714 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 335881 99.19% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1416 0.42% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 912 0.27% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 152 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 149 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 41 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 27 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 24 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 338608 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 414311 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23113.131199 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 18566.304673 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 20214.309005 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 405108 97.78% 97.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6775 1.64% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1700 0.41% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 115 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 357 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 138 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 86 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 414311 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 341299530060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.159336 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.721695 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 340284229060 99.70% 99.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 551479000 0.16% 99.86% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 203508500 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 121654000 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 47328500 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 25233500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 25945000 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 34128500 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5458500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 539500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 14000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 341299530060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 89325 84.44% 84.44% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 16465 15.56% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 105790 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886664 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886500 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 107468 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886664 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105790 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 107468 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 993968 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105790 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 992454 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 104053210 # DTB read hits -system.cpu1.dtb.read_misses 608792 # DTB read misses -system.cpu1.dtb.write_hits 81022913 # DTB write hits -system.cpu1.dtb.write_misses 277708 # DTB write misses -system.cpu1.dtb.flush_tlb 1101 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 101829672 # DTB read hits +system.cpu1.dtb.read_misses 610637 # DTB read misses +system.cpu1.dtb.write_hits 78493819 # DTB write hits +system.cpu1.dtb.write_misses 276027 # DTB write misses +system.cpu1.dtb.flush_tlb 1099 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21005 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55258 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 175 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8900 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 494 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 53264 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 214 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9173 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55921 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 104662002 # DTB read accesses -system.cpu1.dtb.write_accesses 81300621 # DTB write accesses +system.cpu1.dtb.perms_faults 54344 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 102440309 # DTB read accesses +system.cpu1.dtb.write_accesses 78769846 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 185076123 # DTB hits -system.cpu1.dtb.misses 886500 # DTB misses -system.cpu1.dtb.accesses 185962623 # DTB accesses +system.cpu1.dtb.hits 180323491 # DTB hits +system.cpu1.dtb.misses 886664 # DTB misses +system.cpu1.dtb.accesses 181210155 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1497,391 +1514,379 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 108383 # Table walker walks requested -system.cpu1.itb.walker.walksLong 108383 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3055 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 74203 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 15086 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 93297 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1942.152481 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12371.477981 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 92174 98.80% 98.80% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 584 0.63% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 102 0.11% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 130 0.14% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 211 0.23% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 45 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 16 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 93297 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 92344 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 29998.852118 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25024.825336 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 23447.205445 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47315 51.24% 51.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 42742 46.29% 97.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 660 0.71% 98.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 85 0.09% 98.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 956 1.04% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 338 0.37% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 49 0.05% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 41 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 83 0.09% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 32 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 14 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 20 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 92344 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 303371540184 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.809423 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -245466797852 -80.91% -80.91% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 548762837036 180.89% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 65136000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 8157000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 1504000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 507000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 155000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 42000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 303371540184 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 74203 96.05% 96.05% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3055 3.95% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 77258 # Table walker page sizes translated +system.cpu1.itb.walker.walks 102782 # Table walker walks requested +system.cpu1.itb.walker.walksLong 102782 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2883 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68745 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14394 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 88388 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1935.822736 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 12537.694172 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 87864 99.41% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 223 0.25% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 254 0.29% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 88388 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29627.804515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24484.599023 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24553.065811 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 83801 97.42% 97.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 633 0.74% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1356 1.58% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.07% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 124 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 13 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 285462324712 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.863931 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -246539938456 -86.37% -86.37% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 531932332168 186.34% 99.98% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 61889000 0.02% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 6735500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 960500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 221000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 125000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 285462324712 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 68745 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2883 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71628 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 108383 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 108383 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 102782 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 102782 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 77258 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 77258 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 185641 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 94245746 # ITB inst hits -system.cpu1.itb.inst_misses 108383 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71628 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71628 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174410 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 91967963 # ITB inst hits +system.cpu1.itb.inst_misses 102782 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1101 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1099 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21005 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 522 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 41537 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21345 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 494 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 39701 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 202136 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 205263 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 94354129 # ITB inst accesses -system.cpu1.itb.hits 94245746 # DTB hits -system.cpu1.itb.misses 108383 # DTB misses -system.cpu1.itb.accesses 94354129 # DTB accesses -system.cpu1.numCycles 688244310 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 92070745 # ITB inst accesses +system.cpu1.itb.hits 91967963 # DTB hits +system.cpu1.itb.misses 102782 # DTB misses +system.cpu1.itb.accesses 92070745 # DTB accesses +system.cpu1.numCycles 688789566 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 242823548 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 582789507 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 130968102 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80836710 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 401946219 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13110617 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2820679 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23345 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 5607 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5329468 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 177594 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 4339 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 94019463 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3524085 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 43192 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 659685833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.033819 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.287421 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 239433402 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 569353182 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 128216560 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 79511671 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 405943168 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 12894098 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2616962 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25257 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 5725 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5490519 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 162267 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 4008 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 91740705 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3476633 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41341 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 660128083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.009568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.262441 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 515917584 78.21% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18016869 2.73% 80.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18269669 2.77% 83.71% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13353344 2.02% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 27714525 4.20% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8994456 1.36% 91.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9703502 1.47% 92.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8398741 1.27% 94.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39317143 5.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 519338149 78.67% 78.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 17657421 2.67% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 17720975 2.68% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13023211 1.97% 86.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 27851950 4.22% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 8753673 1.33% 91.55% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9450814 1.43% 92.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8261049 1.25% 94.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 38070841 5.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 659685833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.190293 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.846777 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 197914756 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 338110902 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105437320 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13046087 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5174542 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19519920 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1400536 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 636170059 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4304353 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5174542 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 205322358 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31076264 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 254971917 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 110916625 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 52221607 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 621253009 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 123804 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2084188 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1933644 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 33372173 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3863 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 594055023 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 953160447 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 734477449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 779699 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 499665654 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 94389369 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 14450095 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 12489155 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 72603024 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 100339444 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85180632 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13386925 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14275413 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 590006738 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 14504084 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 589818158 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 830847 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 79048188 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 50610611 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352346 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 659685833 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.894089 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.635498 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 660128083 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.186148 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.826600 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 194262443 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 345472686 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 102025852 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13293227 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5071579 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19043746 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1394530 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 620472933 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4297557 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5071579 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 201685746 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31240093 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 261429717 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 107754222 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 52944105 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 605820743 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 130951 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2142931 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 2140614 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 33385135 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3753 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 580698698 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 936110112 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 716711881 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 767618 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 488837378 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 91861315 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14967870 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13038182 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 74719709 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 97839319 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 82555667 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13435403 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14269542 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 574617477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15094560 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 575613551 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 822312 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 77207090 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 49700091 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 361677 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 660128083 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.871973 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.612023 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 430142670 65.20% 65.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 95209085 14.43% 79.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43103455 6.53% 86.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30774369 4.67% 90.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22787863 3.45% 94.29% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16081687 2.44% 96.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10870686 1.65% 98.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6433091 0.98% 99.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4282927 0.65% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 433148093 65.62% 65.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 96441838 14.61% 80.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 42095455 6.38% 86.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 30017553 4.55% 91.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 22180461 3.36% 94.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15486932 2.35% 96.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10578992 1.60% 98.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6132384 0.93% 99.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4046375 0.61% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 659685833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 660128083 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2991282 25.77% 25.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24682 0.21% 25.98% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3126 0.03% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.01% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4685148 40.36% 66.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3902762 33.62% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2899692 25.45% 25.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23212 0.20% 25.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2493 0.02% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4727772 41.50% 67.18% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3739545 32.82% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 399989408 67.82% 67.82% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1473233 0.25% 68.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67059 0.01% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 153 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 4 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 70210 0.01% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 106137364 17.99% 86.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82080680 13.92% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 87 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 390631647 67.86% 67.86% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1449252 0.25% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 67728 0.01% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 81 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 18 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 4 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 58665 0.01% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 103885376 18.05% 86.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 79520645 13.81% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 589818158 # Type of FU issued -system.cpu1.iq.rate 0.856990 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11607000 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019679 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1850695958 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 683728270 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 568714201 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1064038 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 529691 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 473676 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 600857355 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 567803 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4685307 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 575613551 # Type of FU issued +system.cpu1.iq.rate 0.835689 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11392715 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019792 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1822546817 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 667071123 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 554642407 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1023395 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 508279 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 454369 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 586459289 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 546890 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4569014 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 15994035 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20483 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 710355 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8709901 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 15724428 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20010 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 670978 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8558712 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3868542 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7450104 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3761249 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7804669 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5174542 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16661499 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 12204142 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 604643269 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1738208 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 100339444 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85180632 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12202242 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 236266 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 11879435 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 710355 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2616920 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2284300 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4901220 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 583187166 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 104040866 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5756605 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5071579 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 16680640 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 12329901 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 589846063 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1702837 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 97839319 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 82555667 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12741950 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 233925 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 12007104 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 670978 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2558274 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2229598 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4787872 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 569204299 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 101821264 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5535672 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 132447 # number of nop insts executed -system.cpu1.iew.exec_refs 185065127 # number of memory reference insts executed -system.cpu1.iew.exec_branches 108200674 # Number of branches executed -system.cpu1.iew.exec_stores 81024261 # Number of stores executed -system.cpu1.iew.exec_rate 0.847355 # Inst execution rate -system.cpu1.iew.wb_sent 570418733 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 569187877 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281309683 # num instructions producing a value -system.cpu1.iew.wb_consumers 488305636 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.827014 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.576093 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 79095788 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14151738 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4369211 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 646199938 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.813158 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.817106 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 134026 # number of nop insts executed +system.cpu1.iew.exec_refs 180319145 # number of memory reference insts executed +system.cpu1.iew.exec_branches 105773243 # Number of branches executed +system.cpu1.iew.exec_stores 78497881 # Number of stores executed +system.cpu1.iew.exec_rate 0.826383 # Inst execution rate +system.cpu1.iew.wb_sent 556304876 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 555096776 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 274163162 # num instructions producing a value +system.cpu1.iew.wb_consumers 476408431 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.805902 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575479 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 77255744 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14732883 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4271292 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 646929445 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.792211 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.788945 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 455330275 70.46% 70.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 92773758 14.36% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32833911 5.08% 89.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15287498 2.37% 92.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10781023 1.67% 93.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6487132 1.00% 94.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6078607 0.94% 95.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3894706 0.60% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22733028 3.52% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 457763793 70.76% 70.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 93973346 14.53% 85.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 32152826 4.97% 90.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 14713797 2.27% 92.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10604817 1.64% 94.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6244010 0.97% 95.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5818154 0.90% 96.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3733305 0.58% 96.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 21925397 3.39% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 646199938 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 447366409 # Number of instructions committed -system.cpu1.commit.committedOps 525462634 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 646929445 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 436316971 # Number of instructions committed +system.cpu1.commit.committedOps 512504942 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160816140 # Number of memory references committed -system.cpu1.commit.loads 84345409 # Number of loads committed -system.cpu1.commit.membars 3627931 # Number of memory barriers committed -system.cpu1.commit.branches 99847042 # Number of branches committed -system.cpu1.commit.fp_insts 454333 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 482598910 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13134163 # Number of function calls committed. +system.cpu1.commit.refs 156111845 # Number of memory references committed +system.cpu1.commit.loads 82114890 # Number of loads committed +system.cpu1.commit.membars 3660763 # Number of memory barriers committed +system.cpu1.commit.branches 97634182 # Number of branches committed +system.cpu1.commit.fp_insts 435169 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 470255893 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12926033 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 363400914 69.16% 69.16% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1135062 0.22% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50467 0.01% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 60009 0.01% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.40% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84345409 16.05% 85.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76470731 14.55% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 355174724 69.30% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1118155 0.22% 69.52% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50641 0.01% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 49535 0.01% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 82114890 16.02% 85.56% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 73996955 14.44% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 525462634 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22733028 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1224126418 # The number of ROB reads -system.cpu1.rob.rob_writes 1222625233 # The number of ROB writes -system.cpu1.timesIdled 4106530 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 28558477 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 48790405544 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 447366409 # Number of Instructions Simulated -system.cpu1.committedOps 525462634 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.538435 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.538435 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.650011 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.650011 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 687757037 # number of integer regfile reads -system.cpu1.int_regfile_writes 406838676 # number of integer regfile writes -system.cpu1.fp_regfile_reads 842941 # number of floating regfile reads -system.cpu1.fp_regfile_writes 528902 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124631004 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125817612 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1199807572 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14264439 # number of misc regfile writes +system.cpu1.commit.op_class_0::total 512504942 # Class of committed instruction +system.cpu1.commit.bw_lim_events 21925397 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1210740079 # The number of ROB reads +system.cpu1.rob.rob_writes 1192741700 # The number of ROB writes +system.cpu1.timesIdled 4053845 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 28661483 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 52418384154 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 436316971 # Number of Instructions Simulated +system.cpu1.committedOps 512504942 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.578645 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.578645 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.633455 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.633455 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 671693836 # number of integer regfile reads +system.cpu1.int_regfile_writes 396256302 # number of integer regfile writes +system.cpu1.fp_regfile_reads 829382 # number of floating regfile reads +system.cpu1.fp_regfile_writes 475398 # number of floating regfile writes +system.cpu1.cc_regfile_reads 122695419 # number of cc regfile reads +system.cpu1.cc_regfile_writes 123792123 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1193620211 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14812328 # number of misc regfile writes system.iobus.trans_dist::ReadReq 40298 # Transaction distribution system.iobus.trans_dist::ReadResp 40298 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution @@ -1924,7 +1929,7 @@ system.iobus.pkt_size_system.realview.ide.dma::total 7334248 system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 7492168 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47828500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 47816000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1946,11 +1951,11 @@ system.iobus.reqLayer16.occupancy 14500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25445500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25477500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40141500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40153500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565650665 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 567153724 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1959,16 +1964,16 @@ system.iobus.respLayer3.utilization 0.0 # La system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115458 # number of replacements -system.iocache.tags.tagsinuse 10.418706 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.431703 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13100979262000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 5.907316 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 4.511389 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.369207 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.281962 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651169 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13100979259000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.538083 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.893621 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221130 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430851 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651981 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1988,18 +1993,18 @@ system.iocache.overall_misses::realview.ethernet 40 system.iocache.overall_misses::realview.ide 8813 # number of overall misses system.iocache.overall_misses::total 8853 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1684461016 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1689547016 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1703214286 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1708300286 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13867464649 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13867464649 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13410969438 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13410969438 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1684461016 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1689898016 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1703214286 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1708651286 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1684461016 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1689898016 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1703214286 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1708651286 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::realview.ide 8813 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 8850 # number of ReadReq accesses(hits+misses) @@ -2027,23 +2032,23 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 191133.667990 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 190909.267345 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 193261.577896 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 193028.280904 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130010.731353 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130010.731353 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125730.981756 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125730.981756 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 191133.667990 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 190884.221846 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 193261.577896 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 193002.517339 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 191133.667990 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 190884.221846 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 36071 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 193261.577896 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 193002.517339 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 35415 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3608 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3508 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.997506 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.095496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2063,18 +2068,18 @@ system.iocache.overall_mshr_misses::realview.ethernet 40 system.iocache.overall_mshr_misses::realview.ide 8813 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 8853 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1243811016 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1247047016 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1262564286 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1265800286 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8534264649 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8534264649 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072705642 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8072705642 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1243811016 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1247248016 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1262564286 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1266001286 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1243811016 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1247248016 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1262564286 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1266001286 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2089,311 +2094,311 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141133.667990 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 140909.267345 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143261.577896 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 143028.280904 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80010.731353 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80010.731353 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75683.507481 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75683.507481 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 141133.667990 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 140884.221846 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 143261.577896 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 143002.517339 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 141133.667990 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 140884.221846 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 143261.577896 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 143002.517339 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1326476 # number of replacements -system.l2c.tags.tagsinuse 65296.669801 # Cycle average of tags in use -system.l2c.tags.total_refs 49454623 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1388892 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 35.607249 # Average number of references to valid blocks. +system.l2c.tags.replacements 1326374 # number of replacements +system.l2c.tags.tagsinuse 65265.362084 # Cycle average of tags in use +system.l2c.tags.total_refs 49524083 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1389631 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 35.638298 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 22398666000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35546.103483 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 178.339981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 269.475913 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3715.302647 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10815.708045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 174.213795 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 257.428239 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3587.286900 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10752.810798 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.542390 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002721 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056691 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.165035 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002658 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003928 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054738 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.164075 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996348 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 319 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62097 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 35423.869586 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 183.395025 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 263.757590 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3339.523943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11653.727077 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 182.196722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 269.878356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3963.200555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9985.813228 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.540525 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002798 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004025 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.177822 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002780 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.004118 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.060474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.152371 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995870 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 308 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62949 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2767 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5122 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53561 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004868 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.947525 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 439122291 # Number of tag accesses -system.l2c.tags.data_accesses 439122291 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 514243 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 181851 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 527161 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 198547 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1421802 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8003169 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8003169 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15970717 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15970717 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5001 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4885 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9886 # number of UpgradeReq hits +system.l2c.tags.age_task_id_blocks_1023::4 307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 578 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2748 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5097 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54406 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.960526 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 439713882 # Number of tag accesses +system.l2c.tags.data_accesses 439713882 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 520227 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 197797 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 519049 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 183181 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1420254 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8006090 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8006090 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 15999481 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 15999481 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 4949 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4988 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9937 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 822179 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 770643 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1592822 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 7938357 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7943580 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15881937 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3437833 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3369062 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6806895 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 367734 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 352789 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 720523 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 514243 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 181851 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7938357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4260012 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 527161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 198547 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7943580 # number of demand (read+write) hits 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number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2181 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8690 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18258 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17747 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36005 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 795643 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 798642 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1594285 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 8034471 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 7876086 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 15910557 # number of ReadCleanReq hits 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overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004266 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010717 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011764 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006159 # mshr miss rate for ReadReq accesses system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.784986 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784155 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.784576 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785432 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781295 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783375 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.240450 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.242800 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.241589 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005488 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006094 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005791 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041395 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.042882 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042132 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.395041 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.433008 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.414246 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004131 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005488 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.087546 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004442 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010701 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006094 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.087721 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034117 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004131 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005488 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.087546 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004442 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010701 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006094 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.087721 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034117 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 127829.676071 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70763.281849 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70751.310081 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70757.380919 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71125 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139392.773852 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139774.479890 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 139578.674506 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125469.445522 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125584.780871 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125530.164611 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131080.893745 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130493.219474 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130784.609938 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145245.877268 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145055.017575 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145144.961780 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125469.445522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136373.840007 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125584.780871 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136254.946515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 135135.772667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126903.891233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128757.828283 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125469.445522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136373.840007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127055.272109 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128741.387337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125584.780871 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136254.946515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 135135.772667 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.363636 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.249238 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.234077 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.241719 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005135 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006478 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005800 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.040698 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.044075 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.042388 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.400718 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.425034 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.413259 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005135 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.088613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011764 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006478 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.087132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034199 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005135 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.088613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011764 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006478 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.087132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034199 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 129000.227448 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67991.057629 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67991.105000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67991.081119 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 69250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139439.219057 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139575.693355 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 139504.762779 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125238.213543 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125643.181140 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130826.925373 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130488.236882 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130650.692885 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145334.302216 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145079.841747 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145199.328106 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125238.213543 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136392.628753 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136020.568810 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135062.582465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130015.926424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127358.376108 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125238.213543 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136392.628753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129415.741218 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129146.950940 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125970.169055 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136020.568810 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135062.582465 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167572.516701 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169190.865353 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176976.360342 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149581.013880 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176241.949758 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169926.263903 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172679.442604 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175186.169638 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149571.674391 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176579.940245 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169749.909256 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172666.844654 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 171719.761610 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 172787.806528 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173321.915512 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 158423.602545 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 172410.754370 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 158412.999228 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54324 # Transaction distribution -system.membus.trans_dist::ReadResp 463697 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1225644 # Transaction distribution -system.membus.trans_dist::CleanEvict 212879 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36939 # Transaction distribution +system.membus.trans_dist::ReadReq 54329 # Transaction distribution +system.membus.trans_dist::ReadResp 466235 # Transaction distribution +system.membus.trans_dist::WriteReq 33699 # Transaction distribution +system.membus.trans_dist::WriteResp 33699 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1224424 # Transaction distribution +system.membus.trans_dist::CleanEvict 216307 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36790 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36943 # Transaction distribution -system.membus.trans_dist::ReadExReq 1016012 # Transaction distribution -system.membus.trans_dist::ReadExResp 1016012 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 409373 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 1016209 # Transaction distribution +system.membus.trans_dist::ReadExResp 1016209 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 411906 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4278076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4407714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 342018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4749732 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6874 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4246337 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4375991 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237825 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4613816 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163572972 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 163744670 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7253184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7253184 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 170997854 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2815 # Total snoops (count) -system.membus.snoop_fanout::samples 3097878 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13748 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163669548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 163841278 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7262720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 171103998 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2667 # Total snoops (count) +system.membus.snoop_fanout::samples 3100373 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3097878 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3100373 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3097878 # Request fanout histogram -system.membus.reqLayer0.occupancy 113853500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3100373 # Request fanout histogram +system.membus.reqLayer0.occupancy 113885000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5460502 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5470002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8296545910 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8294790249 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7735775396 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7676329675 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227455723 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44628309 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2710,11 +2711,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2747,64 +2748,64 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 53686542 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27275171 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4479 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2151 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2151 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 53748943 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 27300315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2137 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2137 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2028951 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25110801 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9228831 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15970717 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2648270 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45894 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45906 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2100210 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2100210 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15974768 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7115167 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1336742 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1230078 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47961225 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31535681 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 914731 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2490388 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 82902025 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2045811904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1101659806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3076664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8367272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3158915646 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2102692 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30077408 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.027456 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.163407 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2032183 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25147760 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33699 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33699 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9230552 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16002915 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2655847 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45875 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2102499 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2102499 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16003573 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7120105 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1337967 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1231303 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48051162 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31561925 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 916568 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2490426 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 83020081 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049724352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1102308286 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3082904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8350216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3163465758 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2107044 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30117798 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.027021 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.162144 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 29251611 97.25% 97.25% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 825797 2.75% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29303991 97.30% 97.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 813807 2.70% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30077408 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 51459246454 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30117798 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 51529807954 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1450396 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1428891 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24008829328 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24051879645 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14504682071 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14516066687 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 530598551 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 531626613 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1447405469 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1449630863 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16329 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16333 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index 61bf9a286..d09bb714e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.771755 # Number of seconds simulated -sim_ticks 51771755296500 # Number of ticks simulated -final_tick 51771755296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.771727 # Number of seconds simulated +sim_ticks 51771726701500 # Number of ticks simulated +final_tick 51771726701500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 629134 # Simulator instruction rate (inst/s) -host_op_rate 739361 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39432920775 # Simulator tick rate (ticks/s) -host_mem_usage 676920 # Number of bytes of host memory used -host_seconds 1312.91 # Real time elapsed on the host -sim_insts 825994487 # Number of instructions simulated -sim_ops 970712321 # Number of ops (including micro ops) simulated +host_inst_rate 821234 # Simulator instruction rate (inst/s) +host_op_rate 965096 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51452236494 # Simulator tick rate (ticks/s) +host_mem_usage 677452 # Number of bytes of host memory used +host_seconds 1006.21 # Real time elapsed on the host +sim_insts 826333887 # Number of instructions simulated +sim_ops 971088679 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 69120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 72384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2314776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 32049840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 60480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 66688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2364572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 32106392 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 391424 # Number of bytes read from this memory -system.physmem.bytes_read::total 69495676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2314776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2364572 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4679348 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 60509440 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 69952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 75072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2290776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 31969648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 59200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 65024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2387996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 32286808 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 387264 # Number of bytes read from this memory +system.physmem.bytes_read::total 69591740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2290776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2387996 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4678772 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 60611648 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory -system.physmem.bytes_written::total 60530020 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1080 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 56829 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 500782 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 501672 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1126290 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 945460 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 60632228 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1093 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1173 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 56454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 499529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 925 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 504491 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6051 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1127791 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 947057 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 948033 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 44711 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 619060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 620153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1342347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 44711 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 90384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1168773 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 949630 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 44248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 617512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 46125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 623638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1344204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 44248 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 46125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 90373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1170748 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1169171 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1168773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 44711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 619367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 620244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7561 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2511518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1126290 # Number of read requests accepted -system.physmem.writeReqs 948033 # Number of write requests accepted -system.physmem.readBursts 1126290 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 948033 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72036608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 45952 # Total number of bytes read from write queue -system.physmem.bytesWritten 60529408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 69495676 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 60530020 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 718 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 294002 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72701 # Per bank write bursts -system.physmem.perBankRdBursts::1 69688 # Per bank write bursts -system.physmem.perBankRdBursts::2 71671 # Per bank write bursts -system.physmem.perBankRdBursts::3 65333 # Per bank write bursts -system.physmem.perBankRdBursts::4 67150 # Per bank write bursts -system.physmem.perBankRdBursts::5 75432 # Per bank write bursts -system.physmem.perBankRdBursts::6 63718 # Per bank write bursts -system.physmem.perBankRdBursts::7 62281 # Per bank write bursts -system.physmem.perBankRdBursts::8 61723 # Per bank write bursts -system.physmem.perBankRdBursts::9 108434 # Per bank write bursts -system.physmem.perBankRdBursts::10 66581 # Per bank write bursts -system.physmem.perBankRdBursts::11 66036 # Per bank write bursts -system.physmem.perBankRdBursts::12 64933 # Per bank write bursts -system.physmem.perBankRdBursts::13 72823 # Per bank write bursts -system.physmem.perBankRdBursts::14 65732 # Per bank write bursts -system.physmem.perBankRdBursts::15 71336 # Per bank write bursts -system.physmem.perBankWrBursts::0 59678 # Per bank write bursts -system.physmem.perBankWrBursts::1 59397 # Per bank write bursts -system.physmem.perBankWrBursts::2 61038 # Per bank write bursts -system.physmem.perBankWrBursts::3 58102 # Per bank write bursts -system.physmem.perBankWrBursts::4 58442 # Per bank write bursts -system.physmem.perBankWrBursts::5 63800 # Per bank write bursts -system.physmem.perBankWrBursts::6 56091 # Per bank write bursts -system.physmem.perBankWrBursts::7 56307 # Per bank write bursts -system.physmem.perBankWrBursts::8 55145 # Per bank write bursts -system.physmem.perBankWrBursts::9 60224 # Per bank write bursts -system.physmem.perBankWrBursts::10 58756 # Per bank write bursts -system.physmem.perBankWrBursts::11 59336 # Per bank write bursts -system.physmem.perBankWrBursts::12 57263 # Per bank write bursts -system.physmem.perBankWrBursts::13 62824 # Per bank write bursts -system.physmem.perBankWrBursts::14 57899 # Per bank write bursts -system.physmem.perBankWrBursts::15 61470 # Per bank write bursts +system.physmem.bw_write::total 1171146 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1170748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 44248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 617818 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 46125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 623729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2515349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1127791 # Number of read requests accepted +system.physmem.writeReqs 949630 # Number of write requests accepted +system.physmem.readBursts 1127791 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 949630 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72133184 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 45440 # Total number of bytes read from write queue +system.physmem.bytesWritten 60631936 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 69591740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 60632228 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 710 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 72704 # Per bank write bursts +system.physmem.perBankRdBursts::1 73689 # Per bank write bursts +system.physmem.perBankRdBursts::2 70161 # Per bank write bursts +system.physmem.perBankRdBursts::3 65996 # Per bank write bursts +system.physmem.perBankRdBursts::4 66834 # Per bank write bursts +system.physmem.perBankRdBursts::5 71242 # Per bank write bursts +system.physmem.perBankRdBursts::6 65196 # Per bank write bursts +system.physmem.perBankRdBursts::7 62079 # Per bank write bursts +system.physmem.perBankRdBursts::8 64428 # Per bank write bursts +system.physmem.perBankRdBursts::9 108710 # Per bank write bursts +system.physmem.perBankRdBursts::10 67339 # Per bank write bursts +system.physmem.perBankRdBursts::11 66743 # Per bank write bursts +system.physmem.perBankRdBursts::12 64268 # Per bank write bursts +system.physmem.perBankRdBursts::13 71345 # Per bank write bursts +system.physmem.perBankRdBursts::14 65944 # Per bank write bursts +system.physmem.perBankRdBursts::15 70403 # Per bank write bursts +system.physmem.perBankWrBursts::0 59852 # Per bank write bursts +system.physmem.perBankWrBursts::1 61594 # Per bank write bursts +system.physmem.perBankWrBursts::2 59825 # Per bank write bursts +system.physmem.perBankWrBursts::3 58084 # Per bank write bursts +system.physmem.perBankWrBursts::4 58217 # Per bank write bursts +system.physmem.perBankWrBursts::5 60425 # Per bank write bursts +system.physmem.perBankWrBursts::6 57000 # Per bank write bursts +system.physmem.perBankWrBursts::7 56382 # Per bank write bursts +system.physmem.perBankWrBursts::8 57853 # Per bank write bursts +system.physmem.perBankWrBursts::9 59874 # Per bank write bursts +system.physmem.perBankWrBursts::10 59285 # Per bank write bursts +system.physmem.perBankWrBursts::11 60081 # Per bank write bursts +system.physmem.perBankWrBursts::12 57131 # Per bank write bursts +system.physmem.perBankWrBursts::13 62251 # Per bank write bursts +system.physmem.perBankWrBursts::14 58136 # Per bank write bursts +system.physmem.perBankWrBursts::15 61384 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 51771752359500 # Total gap between requests +system.physmem.numWrRetry 47 # Number of times write queue was full causing retry +system.physmem.totGap 51771723764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1083174 # Read request sizes (log2) +system.physmem.readPktSize::6 1084675 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 945460 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1099993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 20089 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 632 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see +system.physmem.writePktSize::6 947057 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1101525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 20079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 506 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1087 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 265 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 323 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -165,137 +165,144 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 52857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 55240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 56007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 57237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 56745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 56988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 56201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 54839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 55500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 53521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 52708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 51972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 442229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 299.767080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.615293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.948153 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 176550 39.92% 39.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 107641 24.34% 64.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38242 8.65% 72.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22044 4.98% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15615 3.53% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11547 2.61% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10103 2.28% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8633 1.95% 88.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51854 11.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 442229 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52882 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.284426 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 294.979543 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 52875 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 18027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 55508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 54068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 53991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 55232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 54714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 55832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 58265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 55672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 55559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 58031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 54737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 53792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 53604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 143 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 442864 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 299.787276 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 172.663870 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.837689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 176801 39.92% 39.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 107708 24.32% 64.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38340 8.66% 72.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22096 4.99% 77.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15589 3.52% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11707 2.64% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10190 2.30% 86.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8599 1.94% 88.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51834 11.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 442864 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52780 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.354225 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 295.252681 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 52773 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52882 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.884573 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.137705 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.800600 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 115 0.22% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 64 0.12% 0.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 68 0.13% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 119 0.23% 0.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49331 93.29% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 541 1.02% 95.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 348 0.66% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 615 1.16% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 130 0.25% 97.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 329 0.62% 97.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 199 0.38% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 29 0.05% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 82 0.16% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 151 0.29% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 24 0.05% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 42 0.08% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 468 0.88% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 24 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 19 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 123 0.23% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 52780 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.949488 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.151899 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.362849 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 96 0.18% 0.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 68 0.13% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 65 0.12% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 113 0.21% 0.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49413 93.62% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 604 1.14% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 382 0.72% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 366 0.69% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 106 0.20% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 120 0.23% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 251 0.48% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.05% 97.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 347 0.66% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 80 0.15% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 21 0.04% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 55 0.10% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 264 0.50% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 29 0.05% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 122 0.23% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 176 0.33% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.01% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52882 # Writes before turning the bus around for reads -system.physmem.totQLat 13860867186 # Total ticks spent queuing -system.physmem.totMemAccLat 34965342186 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5627860000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12314.51 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52780 # Writes before turning the bus around for reads +system.physmem.totQLat 13931485499 # Total ticks spent queuing +system.physmem.totMemAccLat 35064254249 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5635405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12360.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31064.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31110.68 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.34 # Average system read bandwidth in MiByte/s @@ -305,40 +312,40 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.22 # Average write queue length when enqueuing -system.physmem.readRowHits 909331 # Number of row buffer hits during reads -system.physmem.writeRowHits 719783 # Number of row buffer hits during writes +system.physmem.avgWrQLen 9.40 # Average write queue length when enqueuing +system.physmem.readRowHits 910554 # Number of row buffer hits during reads +system.physmem.writeRowHits 721036 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.79 # Row buffer hit rate for reads system.physmem.writeRowHitRate 76.11 # Row buffer hit rate for writes -system.physmem.avgGap 24958385.15 # Average gap between requests +system.physmem.avgGap 24921151.64 # Average gap between requests system.physmem.pageHitRate 78.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1706473440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 931111500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4274158200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3064100400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3381479010000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1298516894550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29923999959000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34613971707090 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.588021 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49780674651877 # Time in different power states -system.physmem_0.memoryStateTime::REF 1728772500000 # Time in different power states +system.physmem_0.actEnergy 1716089760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 936358500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4273627800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3054535920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3381477484320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1299156215670 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29923425135750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34614039447720 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.589631 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49779697907279 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728771720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 262307488123 # Time in different power states +system.physmem_0.memoryStateTime::ACT 263256805221 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1636777800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 893083125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4505264400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3064502160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3381479010000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1291239562905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29930383583250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34613201783640 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.573149 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49791285234291 # Time in different power states -system.physmem_1.memoryStateTime::REF 1728772500000 # Time in different power states +system.physmem_1.actEnergy 1631962080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 890455500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4517588400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3084447600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3381477484320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1291204023120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29930400751500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34613206712520 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.573546 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49791314720420 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728771720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 251692056959 # Time in different power states +system.physmem_1.memoryStateTime::ACT 251640005830 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -392,69 +399,69 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 115460 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 115460 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17717 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83741 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 10 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 115450 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.259853 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 63.668442 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 115448 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 115485 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 115485 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17906 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83637 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 115474 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.346398 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 89.645919 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 115472 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 115450 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 101468 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25057.924666 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21784.198284 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16152.265883 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 100874 99.41% 99.41% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.42% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 517 0.51% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 5 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 13 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 101468 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -3983763676 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.449006 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 115474 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 101554 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25029.885578 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 21753.655577 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15864.720522 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100973 99.43% 99.43% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8 0.01% 99.44% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 501 0.49% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 8 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 30 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 101554 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -3996350676 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.438404 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1788733704 -44.90% -44.90% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -5772497380 144.90% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -3983763676 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 83741 82.54% 82.54% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17717 17.46% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 101458 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115460 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::0 1752015204 -43.84% -43.84% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -5748365880 143.84% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -3996350676 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 83637 82.37% 82.37% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17906 17.63% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101543 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 115485 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115460 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101458 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 115485 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101543 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101458 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 216918 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101543 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 217028 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 77974126 # DTB read hits -system.cpu0.dtb.read_misses 88549 # DTB read misses -system.cpu0.dtb.write_hits 70569009 # DTB write hits -system.cpu0.dtb.write_misses 26911 # DTB write misses +system.cpu0.dtb.read_hits 77968786 # DTB read hits +system.cpu0.dtb.read_misses 88587 # DTB read misses +system.cpu0.dtb.write_hits 70658355 # DTB write hits +system.cpu0.dtb.write_misses 26898 # DTB write misses system.cpu0.dtb.flush_tlb 51778 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 18628 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 500 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 67577 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 18574 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 67879 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3961 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4111 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9183 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78062675 # DTB read accesses -system.cpu0.dtb.write_accesses 70595920 # DTB write accesses +system.cpu0.dtb.perms_faults 9218 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78057373 # DTB read accesses +system.cpu0.dtb.write_accesses 70685253 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 148543135 # DTB hits -system.cpu0.dtb.misses 115460 # DTB misses -system.cpu0.dtb.accesses 148658595 # DTB accesses +system.cpu0.dtb.hits 148627141 # DTB hits +system.cpu0.dtb.misses 115485 # DTB misses +system.cpu0.dtb.accesses 148742626 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,278 +491,281 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 74491 # Table walker walks requested -system.cpu0.itb.walker.walksLong 74491 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4184 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 65168 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 74491 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 74491 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 74491 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 69352 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28600.025955 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25396.938168 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18997.799631 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 68658 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 606 0.87% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 12 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 31 0.04% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 74042 # Table walker walks requested +system.cpu0.itb.walker.walksLong 74042 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4198 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64736 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 74042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 74042 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 74042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 68934 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28581.273392 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25349.599489 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 19061.356835 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 68231 98.98% 98.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 610 0.88% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 10 0.01% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 35 0.05% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 69352 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 68934 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 65168 93.97% 93.97% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4184 6.03% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 69352 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 64736 93.91% 93.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4198 6.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 68934 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74491 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 74042 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 74042 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 69352 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 69352 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 143843 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 413472692 # ITB inst hits -system.cpu0.itb.inst_misses 74491 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 68934 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 68934 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 142976 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 413989239 # ITB inst hits +system.cpu0.itb.inst_misses 74042 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51778 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 18628 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 500 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 50115 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 18574 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 509 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 49997 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 413547183 # ITB inst accesses -system.cpu0.itb.hits 413472692 # DTB hits -system.cpu0.itb.misses 74491 # DTB misses -system.cpu0.itb.accesses 413547183 # DTB accesses -system.cpu0.numCycles 51772397578 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 414063281 # ITB inst accesses +system.cpu0.itb.hits 413989239 # DTB hits +system.cpu0.itb.misses 74042 # DTB misses +system.cpu0.itb.accesses 414063281 # DTB accesses +system.cpu0.numCycles 51772399583 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 15961 # number of quiesce instructions executed -system.cpu0.committedInsts 413219664 # Number of instructions committed -system.cpu0.committedOps 485565994 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 446433803 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 442229 # Number of float alu accesses -system.cpu0.num_func_calls 24786010 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 62671041 # number of instructions that are conditional controls -system.cpu0.num_int_insts 446433803 # number of integer instructions -system.cpu0.num_fp_insts 442229 # number of float instructions -system.cpu0.num_int_register_reads 644929511 # number of times the integer registers were read -system.cpu0.num_int_register_writes 353812607 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 719009 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 362960 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 107066643 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 106758859 # number of times the CC registers were written -system.cpu0.num_mem_refs 148533323 # number of memory refs -system.cpu0.num_load_insts 77969520 # Number of load instructions -system.cpu0.num_store_insts 70563803 # Number of store instructions -system.cpu0.num_idle_cycles 50229359275.953438 # Number of idle cycles -system.cpu0.num_busy_cycles 1543038302.046558 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029804 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970196 # Percentage of idle cycles -system.cpu0.Branches 92169862 # Number of branches fetched +system.cpu0.kern.inst.quiesce 15959 # number of quiesce instructions executed +system.cpu0.committedInsts 413737178 # Number of instructions committed +system.cpu0.committedOps 486128458 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 446921205 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 447031 # Number of float alu accesses +system.cpu0.num_func_calls 24805806 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 62762528 # number of instructions that are conditional controls +system.cpu0.num_int_insts 446921205 # number of integer instructions +system.cpu0.num_fp_insts 447031 # number of float instructions +system.cpu0.num_int_register_reads 646154735 # number of times the integer registers were read +system.cpu0.num_int_register_writes 354190798 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 724381 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 372700 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 107222136 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 106914913 # number of times the CC registers were written +system.cpu0.num_mem_refs 148617421 # number of memory refs +system.cpu0.num_load_insts 77964333 # Number of load instructions +system.cpu0.num_store_insts 70653088 # Number of store instructions +system.cpu0.num_idle_cycles 50228896973.724121 # Number of idle cycles +system.cpu0.num_busy_cycles 1543502609.275879 # Number of busy cycles +system.cpu0.not_idle_fraction 0.029813 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.970187 # Percentage of idle cycles +system.cpu0.Branches 92293251 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 336128174 69.18% 69.18% # Class of executed instruction -system.cpu0.op_class::IntMult 1076007 0.22% 69.41% # Class of executed instruction -system.cpu0.op_class::IntDiv 49967 0.01% 69.42% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.42% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 53572 0.01% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu0.op_class::MemRead 77969520 16.05% 85.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 70563803 14.52% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 336607156 69.20% 69.20% # Class of executed instruction +system.cpu0.op_class::IntMult 1073484 0.22% 69.42% # Class of executed instruction +system.cpu0.op_class::IntDiv 49277 0.01% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 20 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55202 0.01% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu0.op_class::MemRead 77964333 16.03% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 70653088 14.53% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 485841084 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9212621 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.942746 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 287301900 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9213133 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.183952 # Average number of references to valid blocks. +system.cpu0.op_class::total 486402581 # Class of executed instruction +system.cpu0.dcache.tags.replacements 9229396 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.942744 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 287404842 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9229908 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.138430 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 301.496360 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 210.446385 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.588860 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.411028 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 300.933674 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 211.009070 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.587761 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.412127 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1195722346 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1195722346 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73035245 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 72652643 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 145687888 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67007378 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67030482 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134037860 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184933 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 187057 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 371990 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165113 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 167764 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 332877 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1642151 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1632221 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3274372 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1781285 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1774075 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3555360 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 140042623 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 139683125 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 279725748 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 140227556 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 139870182 # number of overall hits -system.cpu0.dcache.overall_hits::total 280097738 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2403483 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2400966 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4804449 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 980962 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 977666 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1958628 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 551880 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 550634 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1102514 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 610138 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 608619 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1218757 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 139928 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 142675 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 282603 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1196218197 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1196218197 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73007967 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 72737993 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 145745960 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67086341 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 66998346 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134084687 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 184406 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 186200 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 370606 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 162812 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 166437 # number of WriteLineReq hits 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# number of overall hits +system.cpu0.dcache.overall_hits::total 280201253 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2418380 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2397518 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 4815898 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 985807 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 975481 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1961288 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 555377 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 547969 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1103346 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 614035 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 608349 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1222384 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141557 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 139184 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 280741 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3384445 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3378632 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6763077 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3936325 # number of overall misses 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73013883500 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2143987500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2178071000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4322058500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3404187 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 3372999 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 6777186 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3959564 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 3920968 # number of overall misses +system.cpu0.dcache.overall_misses::total 7880532 # number of overall misses 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overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 147985726500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75438728 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 75053609 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 150492337 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 67988340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 68008148 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 135996488 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 736813 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 737691 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1474504 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 775251 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 776383 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1551634 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1782079 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1774896 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3556975 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1781285 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1774076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3555361 # number of StoreCondReq accesses(hits+misses) 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0.014376 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.014402 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.749010 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.746429 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.747719 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.787020 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.783916 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.785467 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078520 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.080385 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079450 # miss rate for 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for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.790419 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.785183 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.787805 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079252 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078570 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078912 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.023597 # miss rate for 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number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1470813500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1497747500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2968561000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33216 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 34191 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67407 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38272403000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 38035124000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 76307527000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 31289337500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31445195500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 62734533000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10450714000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10117444000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20568158000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 35764874000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 36263707500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 72028581500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1482346000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1473647000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2955993000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 79000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 81000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69666340500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69302452000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 138968792500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80072421500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 79431687000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 159504108500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3017045500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3182297000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199342500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3020495500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3197083500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217579000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6037541000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6379380500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12416921500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031702 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031850 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031776 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014259 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014233 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014246 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.747720 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745285 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.746502 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.787020 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.783916 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785467 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059893 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061439 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060664 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 69561740500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69480319500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 139042060000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80012454500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 79597763500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 159610218000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3013571000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3185791500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199362500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2991819500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3225760000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6217579500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6005390500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6411551500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12416942000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031904 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031769 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031837 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014312 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014208 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014260 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.749445 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745230 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747346 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.790419 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.785183 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787805 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060501 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059798 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060151 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023434 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023475 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023454 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027136 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027178 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027157 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15940.680085 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15902.920255 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15921.804675 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32536.278660 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32323.375357 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32429.910360 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18888.209028 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18423.825461 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18656.257722 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58224.653275 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59594.020233 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58908.483397 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13780.177825 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13734.880373 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13757.286323 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023559 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023428 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023494 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027282 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027112 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027197 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15904.442617 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15934.299038 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15919.310409 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32115.607859 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32559.916812 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32336.788080 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18849.576229 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18492.015536 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18671.980987 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 58245.660264 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 59610.038810 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 58924.676288 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13717.297157 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13911.385713 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13813.374144 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 79000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20727.546384 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20635.599229 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20681.590992 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20468.509816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20324.454356 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20396.517068 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182685.165002 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185189.536778 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183962.209561 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178854.541686 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 190087.609251 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.578129 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180748.465707 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187612.284210 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184210.923360 # average overall mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20576.323947 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20723.314158 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20649.514438 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20333.037491 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20410.279557 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20371.484963 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182662.807613 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185198.901291 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.344214 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 178957.979423 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 189873.447525 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184459.592963 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 180798.124398 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 187521.613875 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184208.494667 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13370435 # number of replacements +system.cpu0.icache.tags.replacements 13374068 # number of replacements system.cpu0.icache.tags.tagsinuse 511.782255 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 813133937 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13370947 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 60.813489 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 813470115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13374580 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 60.822105 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 61705740500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 285.320721 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 226.461534 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.557267 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.442308 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 283.742263 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 228.039992 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.554184 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.445391 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12676.533398 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12660.404379 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency @@ -1068,65 +1082,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 118174 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 118174 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17820 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86207 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 117928 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 117928 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 18037 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85683 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 118168 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 118168 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 118168 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 104033 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25040.588083 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21749.548904 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15700.304805 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 103488 99.48% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 470 0.45% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 4 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 22 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 104033 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1363590484 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 2.149961 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1568075704 -115.00% -115.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -2931666188 215.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1363590484 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86208 82.87% 82.87% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17820 17.13% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 104028 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 118174 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 117922 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 117922 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 117922 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 103726 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24721.569327 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 21421.072660 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15374.016898 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 68517 66.06% 66.06% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 34673 33.43% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 1 0.00% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 7 0.01% 99.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 395 0.38% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 59 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 7 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 7 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 18 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 103726 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 7196110108 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.793869 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.404526 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1483343204 20.61% 20.61% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 5712766904 79.39% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 7196110108 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85684 82.61% 82.61% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18037 17.39% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 103721 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 117928 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 118174 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 104028 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 117928 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103721 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 104028 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 222202 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103721 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 221649 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 77583369 # DTB read hits -system.cpu1.dtb.read_misses 91391 # DTB read misses -system.cpu1.dtb.write_hits 70584225 # DTB write hits -system.cpu1.dtb.write_misses 26783 # DTB write misses +system.cpu1.dtb.read_hits 77658339 # DTB read hits +system.cpu1.dtb.read_misses 91087 # DTB read misses +system.cpu1.dtb.write_hits 70545022 # DTB write hits +system.cpu1.dtb.write_misses 26841 # DTB write misses system.cpu1.dtb.flush_tlb 51774 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 19034 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 497 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 67777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 19088 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 488 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 67576 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3786 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4039 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9337 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 77674760 # DTB read accesses -system.cpu1.dtb.write_accesses 70611008 # DTB write accesses +system.cpu1.dtb.perms_faults 9302 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 77749426 # DTB read accesses +system.cpu1.dtb.write_accesses 70571863 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 148167594 # DTB hits -system.cpu1.dtb.misses 118174 # DTB misses -system.cpu1.dtb.accesses 148285768 # DTB accesses +system.cpu1.dtb.hits 148203361 # DTB hits +system.cpu1.dtb.misses 117928 # DTB misses +system.cpu1.dtb.accesses 148321289 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1156,125 +1175,126 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 75448 # Table walker walks requested -system.cpu1.itb.walker.walksLong 75448 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4153 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66142 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 75448 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 75448 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75448 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 70295 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28625.784195 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25406.753839 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18792.899470 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 69604 99.02% 99.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1 0.00% 99.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 599 0.85% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 17 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 70295 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 75461 # Table walker walks requested +system.cpu1.itb.walker.walksLong 75461 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4165 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66112 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 75461 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 75461 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75461 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 70277 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28243.080951 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25107.153761 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18108.319299 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 69604 99.04% 99.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.00% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 599 0.85% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 10 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 30 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 11 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 70277 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 66142 94.09% 94.09% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4153 5.91% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 70295 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 66112 94.07% 94.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4165 5.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 70277 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75448 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75448 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 75461 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 75461 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70295 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70295 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 145743 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 413032197 # ITB inst hits -system.cpu1.itb.inst_misses 75448 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 70277 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 70277 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 145738 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 412855461 # ITB inst hits +system.cpu1.itb.inst_misses 75461 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51774 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 19034 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 497 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 50656 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 19088 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 488 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 50522 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 413107645 # ITB inst accesses -system.cpu1.itb.hits 413032197 # DTB hits -system.cpu1.itb.misses 75448 # DTB misses -system.cpu1.itb.accesses 413107645 # DTB accesses -system.cpu1.numCycles 51771113015 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 412930922 # ITB inst accesses +system.cpu1.itb.hits 412855461 # DTB hits +system.cpu1.itb.misses 75461 # DTB misses +system.cpu1.itb.accesses 412930922 # DTB accesses +system.cpu1.numCycles 51771053820 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 412774823 # Number of instructions committed -system.cpu1.committedOps 485146327 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 446024475 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 456863 # Number of float alu accesses -system.cpu1.num_func_calls 24836924 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 62537039 # number of instructions that are conditional controls -system.cpu1.num_int_insts 446024475 # number of integer instructions -system.cpu1.num_fp_insts 456863 # number of float instructions -system.cpu1.num_int_register_reads 646025772 # number of times the integer registers were read -system.cpu1.num_int_register_writes 353451520 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 733263 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 394304 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 106699743 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 106398156 # number of times the CC registers were written -system.cpu1.num_mem_refs 148156265 # number of memory refs -system.cpu1.num_load_insts 77578568 # Number of load instructions -system.cpu1.num_store_insts 70577697 # Number of store instructions -system.cpu1.num_idle_cycles 50233500723.542557 # Number of idle cycles -system.cpu1.num_busy_cycles 1537612291.457444 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029700 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970300 # Percentage of idle cycles -system.cpu1.Branches 92112103 # Number of branches fetched +system.cpu1.committedInsts 412596709 # Number of instructions committed +system.cpu1.committedOps 484960221 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 445873459 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 452061 # Number of float alu accesses +system.cpu1.num_func_calls 24841157 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 62479389 # number of instructions that are conditional controls +system.cpu1.num_int_insts 445873459 # number of integer instructions +system.cpu1.num_fp_insts 452061 # number of float instructions +system.cpu1.num_int_register_reads 645239510 # number of times the integer registers were read +system.cpu1.num_int_register_writes 353339457 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 727891 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 384564 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 106622832 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 106320597 # number of times the CC registers were written +system.cpu1.num_mem_refs 148192340 # number of memory refs +system.cpu1.num_load_insts 77653796 # Number of load instructions +system.cpu1.num_store_insts 70538544 # Number of store instructions +system.cpu1.num_idle_cycles 50233192566.855270 # Number of idle cycles +system.cpu1.num_busy_cycles 1537861253.144726 # Number of busy cycles +system.cpu1.not_idle_fraction 0.029705 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.970295 # Percentage of idle cycles +system.cpu1.Branches 92059897 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 336122870 69.24% 69.24% # Class of executed instruction -system.cpu1.op_class::IntMult 1039751 0.21% 69.46% # Class of executed instruction -system.cpu1.op_class::IntDiv 47048 0.01% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 58827 0.01% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::MemRead 77578568 15.98% 85.46% # Class of executed instruction -system.cpu1.op_class::MemWrite 70577697 14.54% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 335900158 69.22% 69.22% # Class of executed instruction +system.cpu1.op_class::IntMult 1042632 0.21% 69.44% # Class of executed instruction +system.cpu1.op_class::IntDiv 47706 0.01% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 1 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.45% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 57197 0.01% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::MemRead 77653796 16.00% 85.46% # Class of executed instruction +system.cpu1.op_class::MemWrite 70538544 14.54% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 485424763 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40321 # Transaction distribution -system.iobus.trans_dist::ReadResp 40321 # Transaction distribution +system.cpu1.op_class::total 485240035 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40316 # Transaction distribution +system.iobus.trans_dist::ReadResp 40316 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1291,11 +1311,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230990 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353784 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353774 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1310,12 +1330,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334432 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492352 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1337,73 +1357,73 @@ system.iobus.reqLayer16.occupancy 16500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25707000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25708000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38602000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565399896 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566763189 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147760000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147750000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 115482 # number of replacements -system.iocache.tags.tagsinuse 10.442874 # Cycle average of tags in use +system.iocache.tags.tagsinuse 10.442873 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183784929000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.514153 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.928721 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219635 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433045 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183784926000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.854402 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.588472 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.365900 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.286779 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652680 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039857 # Number of tag accesses -system.iocache.tags.data_accesses 1039857 # Number of data accesses +system.iocache.tags.tag_accesses 1039812 # Number of tag accesses +system.iocache.tags.data_accesses 1039812 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8836 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8873 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8831 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8868 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8836 # number of demand (read+write) misses -system.iocache.demand_misses::total 8876 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8831 # number of demand (read+write) misses +system.iocache.demand_misses::total 8871 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8836 # number of overall misses -system.iocache.overall_misses::total 8876 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5087000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1609197370 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1614284370 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8831 # number of overall misses +system.iocache.overall_misses::total 8871 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1624550168 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1629620168 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13863548526 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13863548526 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5438000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1609197370 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1614635370 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5438000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1609197370 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1614635370 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13409547021 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13409547021 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1624550168 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1629971168 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1624550168 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1629971168 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8836 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8873 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8831 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8868 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8836 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8831 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8871 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8836 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8831 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8871 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1417,55 +1437,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137486.486486 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182118.308058 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 181932.195424 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183959.932963 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183764.114569 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129974.016782 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129974.016782 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135950 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 182118.308058 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 181910.248986 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135950 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 182118.308058 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 181910.248986 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32984 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125717.646263 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125717.646263 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183959.932963 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183741.536242 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183959.932963 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183741.536242 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32143 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3440 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3321 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.588372 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.678711 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8836 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8873 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8831 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8868 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8836 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8876 # number of demand (read+write) MSHR misses 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ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1183000168 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1186220168 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8530348526 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8530348526 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3438000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1167397370 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1170835370 # number of demand (read+write) MSHR miss cycles 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132118.308058 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 131932.195424 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133959.932963 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133764.114569 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79974.016782 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79974.016782 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85950 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 132118.308058 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131910.248986 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85950 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 132118.308058 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131910.248986 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75669.543117 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75669.543117 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133959.932963 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133741.536242 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133959.932963 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133741.536242 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 987985 # number of replacements -system.l2c.tags.tagsinuse 65209.498770 # Cycle average of tags in use -system.l2c.tags.total_refs 41654495 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1049725 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 39.681340 # Average number of references to valid blocks. +system.l2c.tags.replacements 989396 # number of replacements +system.l2c.tags.tagsinuse 65299.098652 # Cycle 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blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4437.462816 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8704.472068 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.574516 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001678 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002345 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.148550 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001413 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002268 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.067710 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.132820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995018 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 271 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 61469 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 270 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2443 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5529 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53059 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004135 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.937943 # Percentage of cache occupancy per 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number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 209151 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 158768 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6613945 # number of overall hits -system.l2c.overall_hits::cpu1.data 3735894 # number of overall hits -system.l2c.overall_hits::total 21497474 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1080 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1131 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 945 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1042 # number of ReadReq misses -system.l2c.ReadReq_misses::total 4198 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 16117 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16535 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 32652 # number of UpgradeReq misses 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percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.002456 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.060680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146787 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001483 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002234 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.070248 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.134705 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996385 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 252 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62099 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2415 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5492 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53743 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.947556 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 372018005 # Number of tag accesses +system.l2c.tags.data_accesses 372018005 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 204641 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 155167 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 205544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 156704 # number of ReadReq hits +system.l2c.ReadReq_hits::total 722056 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 7232763 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 7232763 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 13372479 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 13372479 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 4450 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4428 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 8878 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 799766 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 788996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1588762 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6672024 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 6632136 # number of ReadCleanReq hits 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0.004498 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006520 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005358 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.065133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.027182 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 127259.766556 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70685.332258 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70682.310251 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70683.801911 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.161398 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.165008 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.163195 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005134 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005398 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005266 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.035506 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035229 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.035368 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.386388 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.397882 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.392108 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005313 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.007503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005134 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.065353 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004480 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.006442 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005398 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.066002 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.027163 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005313 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.007503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.065353 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004480 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.006442 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005398 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.066002 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.027163 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 125929.094236 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127850.809889 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 126141.621622 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 126723.425197 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 126703.470406 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67940.490950 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67931.037632 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67935.722185 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120524.496157 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120652.920493 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 120588.213860 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122217.575566 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122121.681168 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122169.066076 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122600.651960 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122782.359685 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122690.203624 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120219.548432 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120186.409444 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120202.755444 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122217.575566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121380.034993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122121.681168 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121523.580194 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 121575.846667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 126506.018519 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122217.575566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121380.034993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127378.306878 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127853.646833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122121.681168 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121523.580194 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 121575.846667 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120593.702087 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120588.203415 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 120590.935057 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 122179.136774 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122174.352706 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 122176.691516 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122936.276534 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122895.720702 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122916.173748 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 120186.958391 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 120158.745471 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 120172.710810 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125929.094236 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127850.809889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 122179.136774 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121564.666568 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 126141.621622 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126723.425197 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122174.352706 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121527.800696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 121656.292566 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125929.094236 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127850.809889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122179.136774 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121564.666568 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 126141.621622 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126723.425197 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122174.352706 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121527.800696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 121656.292566 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170162.700575 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170140.289732 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172666.084730 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138954.857857 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167354.216011 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178587.311969 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172675.851645 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138953.224862 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 167457.710252 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178373.064924 # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172959.266621 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168742.777595 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 168790.116209 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175594.918095 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 149324.678145 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 175506.712293 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149323.449318 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 76824 # Transaction distribution -system.membus.trans_dist::ReadResp 376266 # Transaction distribution +system.membus.trans_dist::ReadReq 76825 # Transaction distribution +system.membus.trans_dist::ReadResp 376385 # Transaction distribution system.membus.trans_dist::WriteReq 33707 # Transaction distribution system.membus.trans_dist::WriteResp 33707 # Transaction distribution -system.membus.trans_dist::WritebackDirty 945460 # Transaction distribution -system.membus.trans_dist::CleanEvict 154121 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33223 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33224 # Transaction distribution -system.membus.trans_dist::ReadExReq 787142 # Transaction distribution -system.membus.trans_dist::ReadExResp 787142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 299442 # Transaction distribution +system.membus.trans_dist::WritebackDirty 947057 # Transaction distribution +system.membus.trans_dist::CleanEvict 156816 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33121 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 788585 # Transaction distribution +system.membus.trans_dist::ReadExResp 788585 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 299560 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3299562 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3429246 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 340924 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3770170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3270790 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3400476 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3637544 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13844 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 122809888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 122979698 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7215808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7215808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 130195506 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3417 # Total snoops (count) -system.membus.snoop_fanout::samples 2439476 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 123012320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 123182134 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7211648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7211648 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 130393782 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3477 # Total snoops (count) +system.membus.snoop_fanout::samples 2442384 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2439476 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2442384 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2439476 # Request fanout histogram -system.membus.reqLayer0.occupancy 106887500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2442384 # Request fanout histogram +system.membus.reqLayer0.occupancy 106884000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5646000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5641500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6220729239 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6231197843 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5972547051 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5914461286 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227475321 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44673503 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2093,61 +2124,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 45741552 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 23157457 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2207 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 45780480 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 23175972 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1745 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2220 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2220 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1182207 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 20652494 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 1179802 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 20664144 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8165321 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13368850 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2150617 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 41555 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 41556 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1895867 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1895867 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13370952 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6107399 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1325421 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1218757 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40197004 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27857487 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 758584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1079607 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 69892682 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1711519828 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 973953566 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2539040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3323424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2691335858 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1592408 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 25060590 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021420 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144781 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 8179867 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13374068 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2154454 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 41435 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 41437 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1898604 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1898604 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13374585 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6117809 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1329048 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1222384 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40209488 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27907755 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 753930 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1075310 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 69946483 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1712086292 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 975622370 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2512480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3297624 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2693518766 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1597993 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 25079917 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021333 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144493 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 24523786 97.86% 97.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 536804 2.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 24544878 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 535039 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 25060590 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 43819448000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 25079917 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 43855145000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1523382 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1530888 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20099553000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20105002500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12672308976 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 12693791976 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 441204000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 439870000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 664179000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 663107000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 0e907e72d..7ec12ef0d 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,133 +1,133 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144275 # Number of seconds simulated -sim_ticks 5144274809000 # Number of ticks simulated -final_tick 5144274809000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.144266 # Number of seconds simulated +sim_ticks 5144266112000 # Number of ticks simulated +final_tick 5144266112000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 169693 # Simulator instruction rate (inst/s) -host_op_rate 335427 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145113000 # Simulator tick rate (ticks/s) -host_mem_usage 770200 # Number of bytes of host memory used -host_seconds 2398.14 # Real time elapsed on the host -sim_insts 406947274 # Number of instructions simulated -sim_ops 804399711 # Number of ops (including micro ops) simulated +host_inst_rate 171088 # Simulator instruction rate (inst/s) +host_op_rate 338186 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2162643270 # Simulator tick rate (ticks/s) +host_mem_usage 817576 # Number of bytes of host memory used +host_seconds 2378.69 # Real time elapsed on the host +sim_insts 406967147 # Number of instructions simulated +sim_ops 804441344 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1034048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10709312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1037760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10694784 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11775872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1034048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1034048 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9547776 # Number of bytes written to this memory -system.physmem.bytes_written::total 9547776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 60 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16157 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 167333 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11765248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1037760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1037760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9531136 # Number of bytes written to this memory +system.physmem.bytes_written::total 9531136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16215 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 167106 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 183998 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149184 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149184 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 201009 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2081792 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 183832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 148924 # Number of write requests responded to by this memory +system.physmem.num_writes::total 148924 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2078972 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5511 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2289122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 201009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 201009 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1856000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1856000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1856000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 201009 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2081792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 2287061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852769 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1852769 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2078972 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4145122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 183998 # Number of read requests accepted -system.physmem.writeReqs 149184 # Number of write requests accepted -system.physmem.readBursts 183998 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149184 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11761088 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 14784 # Total number of bytes read from write queue -system.physmem.bytesWritten 9546240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11775872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9547776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 231 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 4139829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 183832 # Number of read requests accepted +system.physmem.writeReqs 148924 # Number of write requests accepted +system.physmem.readBursts 183832 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 148924 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11753920 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11328 # Total number of bytes read from write queue +system.physmem.bytesWritten 9529408 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11765248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9531136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 177 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 58239 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11315 # Per bank write bursts -system.physmem.perBankRdBursts::1 10581 # Per bank write bursts -system.physmem.perBankRdBursts::2 12129 # Per bank write bursts -system.physmem.perBankRdBursts::3 11752 # Per bank write bursts -system.physmem.perBankRdBursts::4 11319 # Per bank write bursts -system.physmem.perBankRdBursts::5 10663 # Per bank write bursts -system.physmem.perBankRdBursts::6 10930 # Per bank write bursts -system.physmem.perBankRdBursts::7 11239 # Per bank write bursts -system.physmem.perBankRdBursts::8 10920 # Per bank write bursts -system.physmem.perBankRdBursts::9 11403 # Per bank write bursts -system.physmem.perBankRdBursts::10 11471 # Per bank write bursts -system.physmem.perBankRdBursts::11 11421 # Per bank write bursts -system.physmem.perBankRdBursts::12 12415 # Per bank write bursts -system.physmem.perBankRdBursts::13 12512 # Per bank write bursts -system.physmem.perBankRdBursts::14 11823 # Per bank write bursts -system.physmem.perBankRdBursts::15 11874 # Per bank write bursts -system.physmem.perBankWrBursts::0 9756 # Per bank write bursts -system.physmem.perBankWrBursts::1 9158 # Per bank write bursts -system.physmem.perBankWrBursts::2 9767 # Per bank write bursts -system.physmem.perBankWrBursts::3 9469 # Per bank write bursts -system.physmem.perBankWrBursts::4 9300 # Per bank write bursts -system.physmem.perBankWrBursts::5 9148 # Per bank write bursts -system.physmem.perBankWrBursts::6 8815 # Per bank write bursts -system.physmem.perBankWrBursts::7 8963 # Per bank write bursts -system.physmem.perBankWrBursts::8 8876 # Per bank write bursts -system.physmem.perBankWrBursts::9 9249 # Per bank write bursts -system.physmem.perBankWrBursts::10 9141 # Per bank write bursts -system.physmem.perBankWrBursts::11 9048 # Per bank write bursts -system.physmem.perBankWrBursts::12 9841 # Per bank write bursts -system.physmem.perBankWrBursts::13 9699 # Per bank write bursts -system.physmem.perBankWrBursts::14 9635 # Per bank write bursts -system.physmem.perBankWrBursts::15 9295 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11604 # Per bank write bursts +system.physmem.perBankRdBursts::1 10712 # Per bank write bursts +system.physmem.perBankRdBursts::2 11807 # Per bank write bursts +system.physmem.perBankRdBursts::3 11944 # Per bank write bursts +system.physmem.perBankRdBursts::4 11505 # Per bank write bursts +system.physmem.perBankRdBursts::5 10649 # Per bank write bursts +system.physmem.perBankRdBursts::6 11472 # Per bank write bursts +system.physmem.perBankRdBursts::7 11273 # Per bank write bursts +system.physmem.perBankRdBursts::8 10779 # Per bank write bursts +system.physmem.perBankRdBursts::9 10837 # Per bank write bursts +system.physmem.perBankRdBursts::10 10616 # Per bank write bursts +system.physmem.perBankRdBursts::11 10970 # Per bank write bursts +system.physmem.perBankRdBursts::12 12334 # Per bank write bursts +system.physmem.perBankRdBursts::13 12596 # Per bank write bursts +system.physmem.perBankRdBursts::14 12433 # Per bank write bursts +system.physmem.perBankRdBursts::15 12124 # Per bank write bursts +system.physmem.perBankWrBursts::0 10095 # Per bank write bursts +system.physmem.perBankWrBursts::1 9143 # Per bank write bursts +system.physmem.perBankWrBursts::2 9309 # Per bank write bursts +system.physmem.perBankWrBursts::3 9560 # Per bank write bursts +system.physmem.perBankWrBursts::4 9320 # Per bank write bursts +system.physmem.perBankWrBursts::5 8650 # Per bank write bursts +system.physmem.perBankWrBursts::6 9309 # Per bank write bursts +system.physmem.perBankWrBursts::7 8633 # Per bank write bursts +system.physmem.perBankWrBursts::8 9264 # Per bank write bursts +system.physmem.perBankWrBursts::9 9181 # Per bank write bursts +system.physmem.perBankWrBursts::10 8947 # Per bank write bursts +system.physmem.perBankWrBursts::11 9087 # Per bank write bursts +system.physmem.perBankWrBursts::12 9676 # Per bank write bursts +system.physmem.perBankWrBursts::13 9763 # Per bank write bursts +system.physmem.perBankWrBursts::14 9717 # Per bank write bursts +system.physmem.perBankWrBursts::15 9243 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 5144274759500 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 5144265940500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 183998 # Read request sizes (log2) +system.physmem.readPktSize::6 183832 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149184 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 169620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11412 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148924 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 169282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11661 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -156,300 +156,300 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 9443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 292.108413 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.353373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.792232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28114 38.54% 38.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17711 24.28% 62.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7670 10.52% 73.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4213 5.78% 79.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2951 4.05% 83.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2449 3.36% 86.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1349 1.85% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1138 1.56% 89.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7348 10.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72943 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.251615 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 563.083563 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7276 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 8552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 8532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 72695 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 292.774799 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.092405 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 313.788617 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27722 38.13% 38.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17851 24.56% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7685 10.57% 73.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4254 5.85% 79.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2907 4.00% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2448 3.37% 86.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1364 1.88% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1142 1.57% 89.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7322 10.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72695 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.828551 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.649701 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7109 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7277 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7277 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.497458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.666266 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.148532 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6223 85.52% 85.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 179 2.46% 87.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 37 0.51% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 2.49% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 17 0.23% 91.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 151 2.08% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 102 1.40% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 5 0.07% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 29 0.40% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 31 0.43% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.12% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 222 3.05% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.08% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.55% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.23% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7277 # Writes before turning the bus around for reads -system.physmem.totQLat 2097648589 # Total ticks spent queuing -system.physmem.totMemAccLat 5543279839 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 918835000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11414.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7110 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.941913 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.730767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.006357 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6192 87.09% 87.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 167 2.35% 89.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 37 0.52% 89.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 45 0.63% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 23 0.32% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.30% 91.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 97 1.36% 92.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.13% 92.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 166 2.33% 95.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 18 0.25% 95.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.10% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.23% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 121 1.70% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 8 0.11% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 38 0.53% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 106 1.49% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.07% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7110 # Writes before turning the bus around for reads +system.physmem.totQLat 2119857534 # Total ticks spent queuing +system.physmem.totMemAccLat 5563388784 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 918275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11542.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30164.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30292.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.86 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.26 # Average write queue length when enqueuing -system.physmem.readRowHits 150147 # Number of row buffer hits during reads -system.physmem.writeRowHits 109836 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.62 # Row buffer hit rate for writes -system.physmem.avgGap 15439833.96 # Average gap between requests -system.physmem.pageHitRate 78.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 269030160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 146792250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 701430600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 481956480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 132992885070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2969904214500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3440495289780 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.800889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4940616567724 # Time in different power states -system.physmem_0.memoryStateTime::REF 171778620000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 149881 # Number of row buffer hits during reads +system.physmem.writeRowHits 109975 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.85 # Row buffer hit rate for writes +system.physmem.avgGap 15459573.80 # Average gap between requests +system.physmem.pageHitRate 78.13 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 270058320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 147353250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 709527000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 479643120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 132965716590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2969918703000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3440488964880 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.801684 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4940650410974 # Time in different power states +system.physmem_0.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31879461276 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31837441026 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 282418920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 154097625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 731944200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 484600320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 335998980720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 133085381535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2969823077250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3440560500570 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.813565 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4940481114488 # Time in different power states -system.physmem_1.memoryStateTime::REF 171778620000 # Time in different power states +system.physmem_1.actEnergy 279515880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 152513625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 722974200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 485209440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 335997963600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 132979028940 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2969907025500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3440524231185 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.808539 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4940617535740 # Time in different power states +system.physmem_1.memoryStateTime::REF 171778100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32014679262 # Time in different power states +system.physmem_1.memoryStateTime::ACT 31863205510 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86341843 # Number of BP lookups -system.cpu.branchPred.condPredicted 86341843 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 843606 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 79482226 # Number of BTB lookups -system.cpu.branchPred.BTBHits 77803537 # Number of BTB hits +system.cpu.branchPred.lookups 86364991 # Number of BP lookups +system.cpu.branchPred.condPredicted 86364991 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844127 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79785258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 77812669 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.887969 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1532975 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 177711 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.527627 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1536742 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177773 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 465489033 # number of cpu cycles simulated +system.cpu.numCycles 465360105 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27349012 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 426558725 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86341843 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79336512 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 433328456 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1773234 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 140367 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 61411 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 195746 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 62 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 949 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 8924695 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 425342 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4681 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 461962620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.822369 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.015343 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27264808 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 426684669 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86364991 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79349411 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 433306610 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1772802 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 134530 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 64125 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 192382 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 61 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 876 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 8941256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 423617 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4382 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 461849793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.823288 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.015889 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 297385469 64.37% 64.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2141918 0.46% 64.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72009169 15.59% 80.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1542851 0.33% 80.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2093373 0.45% 81.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2277762 0.49% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1468275 0.32% 82.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1844826 0.40% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81198977 17.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 297255411 64.36% 64.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2121995 0.46% 64.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72014573 15.59% 80.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1541910 0.33% 80.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2093291 0.45% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2283864 0.49% 81.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1472775 0.32% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1848688 0.40% 82.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81217286 17.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 461962620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.185486 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.916367 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23051751 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 281963390 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 147749616 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 8311246 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 886617 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 834090099 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 886617 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 26334343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 229948938 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14545958 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 152100341 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 38146423 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 830806639 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 454355 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12555277 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 214921 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22219847 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 992487524 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1803840100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1108929979 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 295 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 961885153 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 30602369 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 460175 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 463946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42648824 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17020536 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10013615 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1265948 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1065839 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 825617137 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1152647 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 820744592 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 214843 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 22370068 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33775079 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 142908 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 461962620 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.776647 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.400230 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 461849793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185587 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.916891 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 22977374 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 281921600 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 147739670 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 8324748 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 886401 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 834278152 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 886401 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 26267496 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 229970737 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14504506 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 152095213 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 38125440 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 830978624 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 455578 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12565136 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 219239 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 22179017 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 992691182 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1804301856 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1109183623 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 961933159 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 30758021 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 459775 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 462810 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42714636 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17039027 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10018616 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1305141 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1111349 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 825753425 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1154163 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 820868911 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 214819 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22466239 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33875924 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 142660 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 461849793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.777350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.400586 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 278779319 60.35% 60.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13677385 2.96% 63.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 9694463 2.10% 65.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7479161 1.62% 67.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 73155086 15.84% 82.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4780135 1.03% 83.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72637826 15.72% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1181137 0.26% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 578108 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 278664222 60.34% 60.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13660041 2.96% 63.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9686600 2.10% 65.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7488458 1.62% 67.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 73146885 15.84% 82.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4790867 1.04% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72643551 15.73% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1186237 0.26% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 582932 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 461962620 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 461849793 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2412123 76.39% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 586072 18.56% 94.95% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159607 5.05% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2421761 76.44% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 586525 18.51% 94.95% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160044 5.05% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 284241 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 792878234 96.60% 96.64% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 149840 0.02% 96.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 126459 0.02% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 284830 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 792980272 96.60% 96.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 149980 0.02% 96.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 126454 0.02% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 91 0.00% 96.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 89 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.67% # Type of FU issued @@ -473,96 +473,96 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.67% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.67% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18033989 2.20% 98.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9271738 1.13% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18050334 2.20% 98.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9276952 1.13% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 820744592 # Type of FU issued -system.cpu.iq.rate 1.763188 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3157802 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003847 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2106824012 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 849151947 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 816471101 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 436 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 156 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 823617942 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 211 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1861954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 820868911 # Type of FU issued +system.cpu.iq.rate 1.763943 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3168330 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003860 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2106970311 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 849385719 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 816582122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 452 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 530 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 823752187 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 224 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1863434 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3065804 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14153 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14111 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1593948 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3081685 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14588 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13991 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1596193 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2095806 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 68873 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2095838 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68033 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 886617 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 206103955 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15659492 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 826769784 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 162986 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17020536 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10013615 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 683525 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 383471 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 14451239 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14111 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 476576 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 506351 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 982927 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 819239221 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 17663851 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1381012 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 886401 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 206156511 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15627383 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 826907588 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 167586 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17039027 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10018616 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 684984 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 384487 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 14418162 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13991 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 476529 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 505758 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 982287 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 819355250 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 17680454 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1388114 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 26724913 # number of memory reference insts executed -system.cpu.iew.exec_branches 82983667 # Number of branches executed -system.cpu.iew.exec_stores 9061062 # Number of stores executed -system.cpu.iew.exec_rate 1.759954 # Inst execution rate -system.cpu.iew.wb_sent 818769187 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 816471257 # cumulative count of insts written-back -system.cpu.iew.wb_producers 638649867 # num instructions producing a value -system.cpu.iew.wb_consumers 1046653125 # num instructions consuming a value -system.cpu.iew.wb_rate 1.754008 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610183 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 22245724 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1009739 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 854697 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 458607756 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.754004 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.647518 # Number of insts commited each cycle +system.cpu.iew.exec_refs 26746540 # number of memory reference insts executed +system.cpu.iew.exec_branches 82995794 # Number of branches executed +system.cpu.iew.exec_stores 9066086 # Number of stores executed +system.cpu.iew.exec_rate 1.760691 # Inst execution rate +system.cpu.iew.wb_sent 818880550 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 816582286 # cumulative count of insts written-back +system.cpu.iew.wb_producers 638742122 # num instructions producing a value +system.cpu.iew.wb_consumers 1046798890 # num instructions consuming a value +system.cpu.iew.wb_rate 1.754732 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610186 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 22341740 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1011503 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 854574 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 458481638 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.754577 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.647842 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 288145143 62.83% 62.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11087272 2.42% 65.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3640468 0.79% 66.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74478879 16.24% 82.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2430107 0.53% 82.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1625402 0.35% 83.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1001040 0.22% 83.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 70854372 15.45% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5345073 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 288021226 62.82% 62.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11081670 2.42% 65.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3642063 0.79% 66.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74473498 16.24% 82.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2428435 0.53% 82.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1625237 0.35% 83.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1003852 0.22% 83.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 70853239 15.45% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5352418 1.17% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 458607756 # Number of insts commited each cycle -system.cpu.commit.committedInsts 406947274 # Number of instructions committed -system.cpu.commit.committedOps 804399711 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 458481638 # Number of insts commited each cycle +system.cpu.commit.committedInsts 406967147 # Number of instructions committed +system.cpu.commit.committedOps 804441344 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22374398 # Number of memory references committed -system.cpu.commit.loads 13954731 # Number of loads committed -system.cpu.commit.membars 448033 # Number of memory barriers committed -system.cpu.commit.branches 81999646 # Number of branches committed +system.cpu.commit.refs 22379764 # Number of memory references committed +system.cpu.commit.loads 13957341 # Number of loads committed +system.cpu.commit.membars 448127 # Number of memory barriers committed +system.cpu.commit.branches 82004213 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 733379682 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155571 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171831 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 781589650 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144528 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121874 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 733419549 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155856 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171897 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 781625831 97.16% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144579 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121842 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -589,231 +589,231 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13952145 1.73% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8419667 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13954756 1.73% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8422423 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 804399711 # Class of committed instruction -system.cpu.commit.bw_lim_events 5345073 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1279829790 # The number of ROB reads -system.cpu.rob.rob_writes 1656663443 # The number of ROB writes -system.cpu.timesIdled 287506 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3526413 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9823058000 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 406947274 # Number of Instructions Simulated -system.cpu.committedOps 804399711 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.143856 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.143856 # CPI: Total CPI of All Threads -system.cpu.ipc 0.874236 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.874236 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1088022059 # number of integer regfile reads -system.cpu.int_regfile_writes 653481018 # number of integer regfile writes -system.cpu.fp_regfile_reads 156 # number of floating regfile reads -system.cpu.cc_regfile_reads 414844045 # number of cc regfile reads -system.cpu.cc_regfile_writes 320950754 # number of cc regfile writes -system.cpu.misc_regfile_reads 264261421 # number of misc regfile reads -system.cpu.misc_regfile_writes 400173 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1656014 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995636 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18946459 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1656526 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.437466 # Average number of references to valid blocks. +system.cpu.commit.op_class_0::total 804441344 # Class of committed instruction +system.cpu.commit.bw_lim_events 5352418 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1279833930 # The number of ROB reads +system.cpu.rob.rob_writes 1656952294 # The number of ROB writes +system.cpu.timesIdled 286358 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3510312 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9823169535 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 406967147 # Number of Instructions Simulated +system.cpu.committedOps 804441344 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.143483 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.143483 # CPI: Total CPI of All Threads +system.cpu.ipc 0.874521 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.874521 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1088188706 # number of integer regfile reads +system.cpu.int_regfile_writes 653573677 # number of integer regfile writes +system.cpu.fp_regfile_reads 164 # number of floating regfile reads +system.cpu.cc_regfile_reads 414911991 # number of cc regfile reads +system.cpu.cc_regfile_writes 320992687 # number of cc regfile writes +system.cpu.misc_regfile_reads 264310319 # number of misc regfile reads +system.cpu.misc_regfile_writes 400396 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1655678 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.993569 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18965333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1656190 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.451182 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 65644500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995636 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993569 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 87599396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 87599396 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10805755 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10805755 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8075007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8075007 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62855 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62855 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 18880762 # number of demand (read+write) hits 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-system.cpu.dcache.WriteReq_avg_miss_latency::total 62956.753286 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23986.573519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23986.573519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20151.832916 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20151.832916 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 556428 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 87673930 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87673930 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10821466 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10821466 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077929 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077929 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63073 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63073 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 18899395 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18899395 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18962468 # number of overall hits +system.cpu.dcache.overall_hits::total 18962468 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1800836 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1800836 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334794 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334794 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406327 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406327 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 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21504425 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.142671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.142671 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039796 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039796 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.865631 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.865631 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101527 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101527 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.118206 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.118206 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16700.626265 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16700.626265 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62910.075243 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62910.075243 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23944.693009 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23944.693009 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20117.179296 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20117.179296 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 547266 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 52454 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 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+system.cpu.dcache.overall_mshr_miss_latency::total 40221791734 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 98116957000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 98116957000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2783856500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2783856500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100900813500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100900813500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034457 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034457 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.858200 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.858200 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059692 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059692 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077122 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077122 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14800.602949 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14800.602949 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65948.044109 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65948.044109 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16908.231328 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.231328 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26608.552467 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26608.552467 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24252.362712 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24252.362712 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171091.653356 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171091.653356 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 199831.778049 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 199831.778049 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 171773.256873 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 171773.256873 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 76780 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.821773 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 101894 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 76796 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.326814 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 199830391500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821773 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988861 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988861 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 437119 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 437119 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 101894 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 101894 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 101894 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 101894 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 101894 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 101894 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77777 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 77777 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77777 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 77777 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77777 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 77777 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 965958500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 965958500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 965958500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 965958500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 965958500 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 965958500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 179671 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 179671 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 179671 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 179671 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 179671 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 179671 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.432886 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.432886 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.432886 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.432886 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.432886 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.432886 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12419.590624 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12419.590624 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12419.590624 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12419.590624 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12419.590624 # average overall miss latency +system.cpu.dtb_walker_cache.tags.replacements 70584 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.821836 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 110496 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 70598 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.565143 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 199830439500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.821836 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988865 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988865 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 435866 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 435866 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 110530 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 110530 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 110530 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 110530 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 110530 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 110530 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 71602 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 71602 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 71602 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 71602 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 71602 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 71602 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914983500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914983500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914983500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 914983500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914983500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 914983500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 182132 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 182132 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 182132 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 182132 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 182132 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 182132 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.393132 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.393132 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.393132 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.393132 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.393132 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.393132 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12778.742214 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12778.742214 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12778.742214 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12778.742214 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,182 +822,182 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 21553 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 21553 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77777 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77777 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77777 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 77777 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77777 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 77777 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 888181500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 888181500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 888181500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 888181500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 888181500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 888181500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.432886 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.432886 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.432886 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.432886 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11419.590624 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11419.590624 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11419.590624 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20861 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20861 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 71602 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 71602 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 71602 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 71602 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 71602 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 71602 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 843381500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 843381500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 843381500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 843381500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 843381500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 843381500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.393132 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.393132 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.393132 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.393132 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11778.742214 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11778.742214 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 11778.742214 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 981325 # number of replacements -system.cpu.icache.tags.tagsinuse 508.752321 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7876209 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981837 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.021911 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 975620 # number of replacements +system.cpu.icache.tags.tagsinuse 509.114510 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7899697 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 976132 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.092857 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 150355632500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.752321 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.993657 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.993657 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 509.114510 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994364 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994364 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9906588 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9906588 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7876209 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7876209 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7876209 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7876209 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7876209 # number of overall hits -system.cpu.icache.overall_hits::total 7876209 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1048476 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1048476 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1048476 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1048476 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1048476 # number of overall misses -system.cpu.icache.overall_misses::total 1048476 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15750091989 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15750091989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15750091989 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15750091989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15750091989 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15750091989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 8924685 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8924685 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 8924685 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8924685 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 8924685 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8924685 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.117480 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.117480 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.117480 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.117480 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.117480 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.117480 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15021.890810 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15021.890810 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15021.890810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15021.890810 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15021.890810 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 14497 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 291 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 495 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 9917449 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9917449 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7899697 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7899697 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7899697 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7899697 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7899697 # number of overall hits +system.cpu.icache.overall_hits::total 7899697 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1041547 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1041547 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1041547 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1041547 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1041547 # number of overall misses +system.cpu.icache.overall_misses::total 1041547 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15667212986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15667212986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15667212986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15667212986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15667212986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15667212986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 8941244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8941244 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 8941244 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 8941244 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 8941244 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 8941244 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116488 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116488 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116488 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116488 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116488 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116488 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15042.252521 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15042.252521 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15042.252521 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15042.252521 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15042.252521 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15042.252521 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 12938 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 311 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 471 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.286869 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 72.750000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 27.469214 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 77.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 981325 # number of writebacks -system.cpu.icache.writebacks::total 981325 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66573 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66573 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66573 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66573 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66573 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66573 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981903 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981903 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981903 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981903 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981903 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981903 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13872010992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13872010992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13872010992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13872010992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13872010992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13872010992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.110021 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.110021 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.110021 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.110021 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14127.679610 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14127.679610 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14127.679610 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14127.679610 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 975620 # number of writebacks +system.cpu.icache.writebacks::total 975620 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65342 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65342 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65342 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65342 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65342 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65342 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 976205 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 976205 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 976205 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 976205 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 976205 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 976205 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13808957489 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13808957489 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13808957489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13808957489 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13808957489 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13808957489 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109180 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109180 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109180 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109180 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14145.550872 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14145.550872 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14145.550872 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14145.550872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14145.550872 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14145.550872 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 13612 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.021123 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25352 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 13625 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.860697 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5116302133500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.021123 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376320 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376320 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 94236 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 94236 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25363 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25363 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 12936 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.024979 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 24186 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 12951 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.867501 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5115444997000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.024979 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376561 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.376561 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 89804 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 89804 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 24185 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 24185 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25365 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25365 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25365 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25365 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14502 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 14502 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14502 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 14502 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14502 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 14502 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 176957500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 176957500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 176957500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 176957500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 176957500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 176957500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39865 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 39865 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 24187 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 24187 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 24187 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 24187 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 13810 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 13810 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 13810 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 13810 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 13810 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 13810 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 163118000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 163118000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 163118000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 163118000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 163118000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 163118000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 37995 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 37995 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39867 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 39867 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39867 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 39867 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363778 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363778 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363760 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.363760 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363760 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.363760 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12202.282444 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 12202.282444 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 12202.282444 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12202.282444 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 12202.282444 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 37997 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 37997 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 37997 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 37997 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363469 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363450 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.363450 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363450 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.363450 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11811.585807 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11811.585807 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11811.585807 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11811.585807 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1006,187 +1006,187 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2767 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2767 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14502 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14502 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14502 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 14502 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14502 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 14502 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 162455500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 162455500 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 162455500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 162455500 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 162455500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 162455500 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363778 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363778 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363760 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363760 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363760 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 11202.282444 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 11202.282444 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 11202.282444 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 2462 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 2462 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 13810 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 13810 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 13810 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 13810 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 13810 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 13810 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149308000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 149308000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 149308000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 149308000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 149308000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 149308000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363469 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363450 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363450 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363450 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363450 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10811.585807 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10811.585807 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10811.585807 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112087 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64799.238973 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4898447 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176177 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 27.804123 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 111812 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64798.412308 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4876376 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176112 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 27.689062 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50590.672109 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.620858 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.139554 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3112.121923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11083.684529 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.771952 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50635.420946 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.805219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143023 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3115.012545 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11033.030575 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.772635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047487 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.169124 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.988758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64090 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3231 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6108 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53982 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977936 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 43579518 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 43579518 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1582394 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1582394 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 980190 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 980190 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 342 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 342 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 155444 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 155444 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 965615 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 965615 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 66816 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 12095 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1332257 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1411168 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 66816 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12095 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 965615 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1487701 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2532227 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 66816 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12095 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 965615 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1487701 # number of overall hits -system.cpu.l2cache.overall_hits::total 2532227 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1438 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1438 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 132521 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 132521 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 16160 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 16160 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 60 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 35761 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 35826 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 60 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 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2166148500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21761700000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23937106500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 8579000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 679000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2166148500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21761700000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23937106500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1582394 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1582394 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 980190 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 980190 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1780 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1780 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287965 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287965 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 981775 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 981775 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 66876 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 12100 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number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2623573000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 93572030000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 93572030000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807865 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807865 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460198 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016457 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026140 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024758 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067914 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000897 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000413 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016457 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101620 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067914 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71470.792072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71470.792072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117804.480045 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117804.480045 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124054.372718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124054.372718 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125800 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124952.642617 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124966.210747 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 132983.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 125800 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124054.372718 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119323.476804 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119742.380883 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.740488 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.740488 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188413.986618 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188413.986618 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159297.440747 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159297.440747 # average overall mshr uncacheable latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823594 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823594 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459919 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016613 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026094 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.024783 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101497 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.068097 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000966 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000548 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016613 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101497 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.068097 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68715.194110 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68715.194110 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117815.636570 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117815.636570 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124044.989639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124044.989639 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 135870.967742 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 125416.666667 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 125505.771474 # average ReadSharedReq mshr miss latency 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mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 119449.087781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 119859.101022 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 158591.566168 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158591.566168 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188326.250808 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188326.250808 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 159296.756763 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 159296.756763 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5460741 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2718937 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 72407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1221 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1221 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5434918 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2706203 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 65803 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 573460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3016607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13899 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1731587 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 980190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 117679 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 981903 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1461779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::MessageReq 1645 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 573476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3003914 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1730558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 975620 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 168030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2247 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287779 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 976205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1454773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::MessageReq 1647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2943868 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146532 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31429 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 174582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 9296411 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 125565760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207412623 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 951488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5659456 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 339589327 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 223808 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3529303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.165576 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2927884 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6146809 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 37703 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 206355 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 9318751 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 124907456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207405643 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 858816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5441920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 338613835 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 220482 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3516168 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.160049 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3464951 98.18% 98.18% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 53009 1.50% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 11343 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3458199 98.35% 98.35% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 46816 1.33% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 11153 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3529303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5594725985 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3516168 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5575385475 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 671790 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 661286 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474740212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1466090916 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3066745270 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3066273273 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 21763478 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20730469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 116728873 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 107476352 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 212016 # Transaction distribution -system.iobus.trans_dist::ReadResp 212016 # Transaction distribution -system.iobus.trans_dist::WriteReq 57726 # Transaction distribution -system.iobus.trans_dist::WriteResp 57726 # Transaction distribution -system.iobus.trans_dist::MessageReq 1645 # Transaction distribution -system.iobus.trans_dist::MessageResp 1645 # Transaction distribution +system.iobus.trans_dist::ReadReq 212032 # Transaction distribution +system.iobus.trans_dist::ReadResp 212032 # Transaction distribution +system.iobus.trans_dist::WriteReq 57756 # Transaction distribution +system.iobus.trans_dist::WriteResp 57756 # Transaction distribution +system.iobus.trans_dist::MessageReq 1647 # Transaction distribution +system.iobus.trans_dist::MessageResp 1647 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) @@ -1391,15 +1391,15 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 444236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 444328 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 542774 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 542870 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) @@ -1414,37 +1414,37 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 228398 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 228450 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3262754 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3980596 # Layer occupancy (ticks) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3262814 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3982096 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10514500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10538500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1031500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1023500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 92500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 59000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 59500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 300003000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1175500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1174500 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 212500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 24561500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 24563000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1452,27 +1452,27 @@ system.iobus.reqLayer15.occupancy 10000 # La system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 241121329 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 242078063 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1231500 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1233000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 433230000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 433292000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50160000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1647000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.116025 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.116006 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4999365177000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116025 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007252 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007252 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4999354367000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.116006 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007250 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007250 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1486,14 +1486,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 904 system.iocache.demand_misses::total 904 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 145501183 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 145501183 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6077027146 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6077027146 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 145501183 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 145501183 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 145501183 # number of overall miss cycles -system.iocache.overall_miss_latency::total 145501183 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149927198 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 149927198 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867794865 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5867794865 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 149927198 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 149927198 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 149927198 # number of overall miss cycles +system.iocache.overall_miss_latency::total 149927198 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1510,19 +1510,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 160952.636062 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 130073.355009 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130073.355009 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 160952.636062 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 160952.636062 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 160952.636062 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1232 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 165848.670354 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125594.924336 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125594.924336 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 165848.670354 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 165848.670354 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 165848.670354 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 254 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 114 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.807018 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.043478 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1536,14 +1536,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 904 system.iocache.demand_mshr_misses::total 904 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 904 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 904 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100301183 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3741027146 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3741027146 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100301183 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100301183 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100301183 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104727198 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3529874733 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3529874733 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104727198 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104727198 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104727198 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1552,81 +1552,80 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110952.636062 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80073.355009 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80073.355009 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110952.636062 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110952.636062 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115848.670354 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75553.825621 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75553.825621 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115848.670354 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115848.670354 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 573460 # Transaction distribution -system.membus.trans_dist::ReadResp 626337 # Transaction distribution -system.membus.trans_dist::WriteReq 13899 # Transaction distribution -system.membus.trans_dist::WriteResp 13899 # Transaction distribution -system.membus.trans_dist::WritebackDirty 149184 # Transaction distribution -system.membus.trans_dist::CleanEvict 9829 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2188 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1709 # Transaction distribution -system.membus.trans_dist::ReadExReq 132252 # Transaction distribution -system.membus.trans_dist::ReadExResp 132250 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 52886 # Transaction distribution -system.membus.trans_dist::MessageReq 1645 # Transaction distribution -system.membus.trans_dist::MessageResp 1645 # Transaction distribution -system.membus.trans_dist::BadAddressError 9 # Transaction distribution +system.membus.trans_dist::ReadReq 573476 # Transaction distribution +system.membus.trans_dist::ReadResp 626351 # Transaction distribution +system.membus.trans_dist::WriteReq 13931 # Transaction distribution +system.membus.trans_dist::WriteResp 13931 # Transaction distribution +system.membus.trans_dist::WritebackDirty 148924 # Transaction distribution +system.membus.trans_dist::CleanEvict 10358 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2192 # Transaction distribution +system.membus.trans_dist::UpgradeResp 19 # Transaction distribution +system.membus.trans_dist::ReadExReq 132088 # Transaction distribution +system.membus.trans_dist::ReadExResp 132085 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 52881 # Transaction distribution +system.membus.trans_dist::MessageReq 1647 # Transaction distribution +system.membus.trans_dist::MessageResp 1647 # Transaction distribution +system.membus.trans_dist::BadAddressError 6 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444236 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 483648 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1658384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1803484 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228398 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460961 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18308608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19997967 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3294 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 444328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 730486 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 481353 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1656179 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95636 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1755109 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6588 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 228450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1460969 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18281344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19970763 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23019587 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1629 # Total snoops (count) -system.membus.snoop_fanout::samples 982619 # Request fanout histogram -system.membus.snoop_fanout::mean 1.001674 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.040881 # Request fanout histogram +system.membus.pkt_size::total 22992391 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1583 # Total snoops (count) +system.membus.snoop_fanout::samples 982226 # Request fanout histogram +system.membus.snoop_fanout::mean 1.001677 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.040914 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 980974 99.83% 99.83% # Request fanout histogram -system.membus.snoop_fanout::2 1645 0.17% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 980579 99.83% 99.83% # Request fanout histogram +system.membus.snoop_fanout::2 1647 0.17% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 982619 # Request fanout histogram -system.membus.reqLayer0.occupancy 339006500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 982226 # Request fanout histogram +system.membus.reqLayer0.occupancy 339026000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 369115500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 369109500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3980404 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3981904 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1013900787 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1012407982 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 12000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 2335404 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2334904 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2139201818 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2135091502 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85763851 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 4662400 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index fd3501a6f..c56d79e86 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.221334 # Nu sim_ticks 5221333868500 # Number of ticks simulated final_tick 5221333868500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155160 # Simulator instruction rate (inst/s) -host_op_rate 301283 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5363173075 # Simulator tick rate (ticks/s) -host_mem_usage 777200 # Number of bytes of host memory used -host_seconds 973.55 # Real time elapsed on the host +host_inst_rate 231127 # Simulator instruction rate (inst/s) +host_op_rate 448792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7989012150 # Simulator tick rate (ticks/s) +host_mem_usage 840496 # Number of bytes of host memory used +host_seconds 653.56 # Real time elapsed on the host sim_insts 151056351 # Number of instructions simulated sim_ops 293314763 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -568,37 +568,37 @@ system.ruby.delayHist::mean 0.431734 # de system.ruby.delayHist::stdev 1.809496 # delay histogram for all message system.ruby.delayHist | 10578004 94.61% 94.61% | 2065 0.02% 94.63% | 600258 5.37% 99.99% | 191 0.00% 100.00% | 301 0.00% 100.00% | 12 0.00% 100.00% | 64 0.00% 100.00% | 2 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message system.ruby.delayHist::total 11180898 # delay histogram for all message -system.ruby.outstanding_req_hist::bucket_size 1 -system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 197955008 -system.ruby.outstanding_req_hist::mean 1.000129 -system.ruby.outstanding_req_hist::gmean 1.000089 -system.ruby.outstanding_req_hist::stdev 0.011356 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 197955008 -system.ruby.latency_hist::bucket_size 128 -system.ruby.latency_hist::max_bucket 1279 -system.ruby.latency_hist::samples 197955007 -system.ruby.latency_hist::mean 1.340882 -system.ruby.latency_hist::gmean 1.042158 -system.ruby.latency_hist::stdev 5.088799 -system.ruby.latency_hist | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00% -system.ruby.latency_hist::total 197955007 -system.ruby.hit_latency_hist::bucket_size 1 -system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 195243038 -system.ruby.hit_latency_hist::mean 1 -system.ruby.hit_latency_hist::gmean 1 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 195243038 -system.ruby.miss_latency_hist::bucket_size 128 -system.ruby.miss_latency_hist::max_bucket 1279 -system.ruby.miss_latency_hist::samples 2711969 -system.ruby.miss_latency_hist::mean 25.882013 -system.ruby.miss_latency_hist::gmean 20.371762 -system.ruby.miss_latency_hist::stdev 35.771321 -system.ruby.miss_latency_hist | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00% -system.ruby.miss_latency_hist::total 2711969 +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 197955008 +system.ruby.outstanding_req_hist_seqr::mean 1.000129 +system.ruby.outstanding_req_hist_seqr::gmean 1.000089 +system.ruby.outstanding_req_hist_seqr::stdev 0.011356 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 197929478 99.99% 99.99% | 25530 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 197955008 +system.ruby.latency_hist_seqr::bucket_size 128 +system.ruby.latency_hist_seqr::max_bucket 1279 +system.ruby.latency_hist_seqr::samples 197955007 +system.ruby.latency_hist_seqr::mean 1.340882 +system.ruby.latency_hist_seqr::gmean 1.042158 +system.ruby.latency_hist_seqr::stdev 5.088799 +system.ruby.latency_hist_seqr | 197919440 99.98% 99.98% | 26716 0.01% 100.00% | 2921 0.00% 100.00% | 3323 0.00% 100.00% | 1640 0.00% 100.00% | 892 0.00% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00% +system.ruby.latency_hist_seqr::total 197955007 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 195243038 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 195243038 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 195243038 +system.ruby.miss_latency_hist_seqr::bucket_size 128 +system.ruby.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.miss_latency_hist_seqr::samples 2711969 +system.ruby.miss_latency_hist_seqr::mean 25.882013 +system.ruby.miss_latency_hist_seqr::gmean 20.371762 +system.ruby.miss_latency_hist_seqr::stdev 35.771321 +system.ruby.miss_latency_hist_seqr | 2676402 98.69% 98.69% | 26716 0.99% 99.67% | 2921 0.11% 99.78% | 3323 0.12% 99.90% | 1640 0.06% 99.96% | 892 0.03% 100.00% | 7 0.00% 100.00% | 33 0.00% 100.00% | 26 0.00% 100.00% | 9 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 2711969 system.ruby.l1_cntrl0.L1Dcache.demand_hits 16386626 # Number of cache demand hits system.ruby.l1_cntrl0.L1Dcache.demand_misses 1208734 # Number of cache demand misses system.ruby.l1_cntrl0.L1Dcache.demand_accesses 17595360 # Number of cache demand accesses @@ -895,135 +895,135 @@ system.ruby.delayVCHist.vnet_2::mean 0.000069 # de system.ruby.delayVCHist.vnet_2::stdev 0.011745 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 86983 100.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 86986 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 128 -system.ruby.LD.latency_hist::max_bucket 1279 -system.ruby.LD.latency_hist::samples 15432045 -system.ruby.LD.latency_hist::mean 2.853347 -system.ruby.LD.latency_hist::gmean 1.313273 -system.ruby.LD.latency_hist::stdev 9.004183 -system.ruby.LD.latency_hist | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.latency_hist::total 15432045 -system.ruby.LD.hit_latency_hist::bucket_size 1 -system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13998259 -system.ruby.LD.hit_latency_hist::mean 1 -system.ruby.LD.hit_latency_hist::gmean 1 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 13998259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13998259 -system.ruby.LD.miss_latency_hist::bucket_size 128 -system.ruby.LD.miss_latency_hist::max_bucket 1279 -system.ruby.LD.miss_latency_hist::samples 1433786 -system.ruby.LD.miss_latency_hist::mean 20.947839 -system.ruby.LD.miss_latency_hist::gmean 18.787632 -system.ruby.LD.miss_latency_hist::stdev 22.620333 -system.ruby.LD.miss_latency_hist | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1433786 -system.ruby.ST.latency_hist::bucket_size 128 -system.ruby.ST.latency_hist::max_bucket 1279 -system.ruby.ST.latency_hist::samples 9612989 -system.ruby.ST.latency_hist::mean 3.237898 -system.ruby.ST.latency_hist::gmean 1.143931 -system.ruby.ST.latency_hist::stdev 17.979843 -system.ruby.ST.latency_hist | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00% -system.ruby.ST.latency_hist::total 9612989 -system.ruby.ST.hit_latency_hist::bucket_size 1 -system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9259401 -system.ruby.ST.hit_latency_hist::mean 1 -system.ruby.ST.hit_latency_hist::gmean 1 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9259401 -system.ruby.ST.miss_latency_hist::bucket_size 128 -system.ruby.ST.miss_latency_hist::max_bucket 1279 -system.ruby.ST.miss_latency_hist::samples 353588 -system.ruby.ST.miss_latency_hist::mean 61.841694 -system.ruby.ST.miss_latency_hist::gmean 38.700068 -system.ruby.ST.miss_latency_hist::stdev 72.272561 -system.ruby.ST.miss_latency_hist | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 353588 -system.ruby.IFETCH.latency_hist::bucket_size 128 -system.ruby.IFETCH.latency_hist::max_bucket 1279 -system.ruby.IFETCH.latency_hist::samples 171728771 -system.ruby.IFETCH.latency_hist::mean 1.087728 -system.ruby.IFETCH.latency_hist::gmean 1.013814 -system.ruby.IFETCH.latency_hist::stdev 1.877484 -system.ruby.IFETCH.latency_hist | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 171728771 -system.ruby.IFETCH.hit_latency_hist::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 170908500 -system.ruby.IFETCH.hit_latency_hist::mean 1 -system.ruby.IFETCH.hit_latency_hist::gmean 1 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 170908500 -system.ruby.IFETCH.miss_latency_hist::bucket_size 128 -system.ruby.IFETCH.miss_latency_hist::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist::samples 820271 -system.ruby.IFETCH.miss_latency_hist::mean 19.366341 -system.ruby.IFETCH.miss_latency_hist::gmean 17.675078 -system.ruby.IFETCH.miss_latency_hist::stdev 20.056386 -system.ruby.IFETCH.miss_latency_hist | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 820271 -system.ruby.RMW_Read.latency_hist::bucket_size 128 -system.ruby.RMW_Read.latency_hist::max_bucket 1279 -system.ruby.RMW_Read.latency_hist::samples 500824 -system.ruby.RMW_Read.latency_hist::mean 4.015135 -system.ruby.RMW_Read.latency_hist::gmean 1.504010 -system.ruby.RMW_Read.latency_hist::stdev 10.229460 -system.ruby.RMW_Read.latency_hist | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 500824 -system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 -system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 434822 -system.ruby.RMW_Read.hit_latency_hist::mean 1 -system.ruby.RMW_Read.hit_latency_hist::gmean 1 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 434822 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 434822 -system.ruby.RMW_Read.miss_latency_hist::bucket_size 128 -system.ruby.RMW_Read.miss_latency_hist::max_bucket 1279 -system.ruby.RMW_Read.miss_latency_hist::samples 66002 -system.ruby.RMW_Read.miss_latency_hist::mean 23.878882 -system.ruby.RMW_Read.miss_latency_hist::gmean 22.130008 -system.ruby.RMW_Read.miss_latency_hist::stdev 18.427339 -system.ruby.RMW_Read.miss_latency_hist | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 66002 -system.ruby.Locked_RMW_Read.latency_hist::bucket_size 64 -system.ruby.Locked_RMW_Read.latency_hist::max_bucket 639 -system.ruby.Locked_RMW_Read.latency_hist::samples 340189 -system.ruby.Locked_RMW_Read.latency_hist::mean 3.322221 -system.ruby.Locked_RMW_Read.latency_hist::gmean 1.405053 -system.ruby.Locked_RMW_Read.latency_hist::stdev 8.368395 -system.ruby.Locked_RMW_Read.latency_hist | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 340189 -system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301867 -system.ruby.Locked_RMW_Read.hit_latency_hist::mean 1 -system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 1 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 301867 -system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 64 -system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 639 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38322 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 21.614634 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 20.468455 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 15.638998 -system.ruby.Locked_RMW_Read.miss_latency_hist | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38322 -system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 340189 -system.ruby.Locked_RMW_Write.latency_hist::mean 1 -system.ruby.Locked_RMW_Write.latency_hist::gmean 1 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 340189 -system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 -system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 340189 -system.ruby.Locked_RMW_Write.hit_latency_hist::mean 1 -system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 1 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 340189 +system.ruby.LD.latency_hist_seqr::bucket_size 128 +system.ruby.LD.latency_hist_seqr::max_bucket 1279 +system.ruby.LD.latency_hist_seqr::samples 15432045 +system.ruby.LD.latency_hist_seqr::mean 2.853347 +system.ruby.LD.latency_hist_seqr::gmean 1.313273 +system.ruby.LD.latency_hist_seqr::stdev 9.004183 +system.ruby.LD.latency_hist_seqr | 15417229 99.90% 99.90% | 12840 0.08% 99.99% | 810 0.01% 99.99% | 753 0.00% 100.00% | 313 0.00% 100.00% | 86 0.00% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 15432045 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 13998259 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 13998259 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 13998259 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.LD.miss_latency_hist_seqr::samples 1433786 +system.ruby.LD.miss_latency_hist_seqr::mean 20.947839 +system.ruby.LD.miss_latency_hist_seqr::gmean 18.787632 +system.ruby.LD.miss_latency_hist_seqr::stdev 22.620333 +system.ruby.LD.miss_latency_hist_seqr | 1418970 98.97% 98.97% | 12840 0.90% 99.86% | 810 0.06% 99.92% | 753 0.05% 99.97% | 313 0.02% 99.99% | 86 0.01% 100.00% | 3 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 1433786 +system.ruby.ST.latency_hist_seqr::bucket_size 128 +system.ruby.ST.latency_hist_seqr::max_bucket 1279 +system.ruby.ST.latency_hist_seqr::samples 9612989 +system.ruby.ST.latency_hist_seqr::mean 3.237898 +system.ruby.ST.latency_hist_seqr::gmean 1.143931 +system.ruby.ST.latency_hist_seqr::stdev 17.979843 +system.ruby.ST.latency_hist_seqr | 9598427 99.85% 99.85% | 8665 0.09% 99.94% | 1602 0.02% 99.96% | 2295 0.02% 99.98% | 1192 0.01% 99.99% | 757 0.01% 100.00% | 4 0.00% 100.00% | 23 0.00% 100.00% | 18 0.00% 100.00% | 6 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 9612989 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 9259401 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9259401 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 9259401 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.ST.miss_latency_hist_seqr::samples 353588 +system.ruby.ST.miss_latency_hist_seqr::mean 61.841694 +system.ruby.ST.miss_latency_hist_seqr::gmean 38.700068 +system.ruby.ST.miss_latency_hist_seqr::stdev 72.272561 +system.ruby.ST.miss_latency_hist_seqr | 339026 95.88% 95.88% | 8665 2.45% 98.33% | 1602 0.45% 98.79% | 2295 0.65% 99.43% | 1192 0.34% 99.77% | 757 0.21% 99.99% | 4 0.00% 99.99% | 23 0.01% 99.99% | 18 0.01% 100.00% | 6 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 353588 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 128 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279 +system.ruby.IFETCH.latency_hist_seqr::samples 171728771 +system.ruby.IFETCH.latency_hist_seqr::mean 1.087728 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.013814 +system.ruby.IFETCH.latency_hist_seqr::stdev 1.877484 +system.ruby.IFETCH.latency_hist_seqr | 171723029 100.00% 100.00% | 4832 0.00% 100.00% | 479 0.00% 100.00% | 259 0.00% 100.00% | 120 0.00% 100.00% | 42 0.00% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 171728771 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 170908500 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 170908500 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 170908500 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 820271 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 19.366341 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 17.675078 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 20.056386 +system.ruby.IFETCH.miss_latency_hist_seqr | 814529 99.30% 99.30% | 4832 0.59% 99.89% | 479 0.06% 99.95% | 259 0.03% 99.98% | 120 0.01% 99.99% | 42 0.01% 100.00% | 0 0.00% 100.00% | 6 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 820271 +system.ruby.RMW_Read.latency_hist_seqr::bucket_size 128 +system.ruby.RMW_Read.latency_hist_seqr::max_bucket 1279 +system.ruby.RMW_Read.latency_hist_seqr::samples 500824 +system.ruby.RMW_Read.latency_hist_seqr::mean 4.015135 +system.ruby.RMW_Read.latency_hist_seqr::gmean 1.504010 +system.ruby.RMW_Read.latency_hist_seqr::stdev 10.229460 +system.ruby.RMW_Read.latency_hist_seqr | 500636 99.96% 99.96% | 143 0.03% 99.99% | 19 0.00% 99.99% | 10 0.00% 100.00% | 9 0.00% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist_seqr::total 500824 +system.ruby.RMW_Read.hit_latency_hist_seqr::bucket_size 1 +system.ruby.RMW_Read.hit_latency_hist_seqr::max_bucket 9 +system.ruby.RMW_Read.hit_latency_hist_seqr::samples 434822 +system.ruby.RMW_Read.hit_latency_hist_seqr::mean 1 +system.ruby.RMW_Read.hit_latency_hist_seqr::gmean 1 +system.ruby.RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 434822 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist_seqr::total 434822 +system.ruby.RMW_Read.miss_latency_hist_seqr::bucket_size 128 +system.ruby.RMW_Read.miss_latency_hist_seqr::max_bucket 1279 +system.ruby.RMW_Read.miss_latency_hist_seqr::samples 66002 +system.ruby.RMW_Read.miss_latency_hist_seqr::mean 23.878882 +system.ruby.RMW_Read.miss_latency_hist_seqr::gmean 22.130008 +system.ruby.RMW_Read.miss_latency_hist_seqr::stdev 18.427339 +system.ruby.RMW_Read.miss_latency_hist_seqr | 65814 99.72% 99.72% | 143 0.22% 99.93% | 19 0.03% 99.96% | 10 0.02% 99.98% | 9 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist_seqr::total 66002 +system.ruby.Locked_RMW_Read.latency_hist_seqr::bucket_size 64 +system.ruby.Locked_RMW_Read.latency_hist_seqr::max_bucket 639 +system.ruby.Locked_RMW_Read.latency_hist_seqr::samples 340189 +system.ruby.Locked_RMW_Read.latency_hist_seqr::mean 3.322221 +system.ruby.Locked_RMW_Read.latency_hist_seqr::gmean 1.405053 +system.ruby.Locked_RMW_Read.latency_hist_seqr::stdev 8.368395 +system.ruby.Locked_RMW_Read.latency_hist_seqr | 339841 99.90% 99.90% | 89 0.03% 99.92% | 235 0.07% 99.99% | 1 0.00% 99.99% | 3 0.00% 99.99% | 8 0.00% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 5 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist_seqr::total 340189 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::samples 301867 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::mean 1 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::gmean 1 +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr | 0 0.00% 0.00% | 301867 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist_seqr::total 301867 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::bucket_size 64 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::max_bucket 639 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::samples 38322 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::mean 21.614634 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::gmean 20.468455 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::stdev 15.638998 +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr | 37974 99.09% 99.09% | 89 0.23% 99.32% | 235 0.61% 99.94% | 1 0.00% 99.94% | 3 0.01% 99.95% | 8 0.02% 99.97% | 5 0.01% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.99% | 5 0.01% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist_seqr::total 38322 +system.ruby.Locked_RMW_Write.latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Write.latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Write.latency_hist_seqr::samples 340189 +system.ruby.Locked_RMW_Write.latency_hist_seqr::mean 1 +system.ruby.Locked_RMW_Write.latency_hist_seqr::gmean 1 +system.ruby.Locked_RMW_Write.latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist_seqr::total 340189 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::samples 340189 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::mean 1 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::gmean 1 +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr | 0 0.00% 0.00% | 340189 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist_seqr::total 340189 system.ruby.Directory_Controller.Fetch 181234 0.00% 0.00% system.ruby.Directory_Controller.Data 103288 0.00% 0.00% system.ruby.Directory_Controller.Memory_Data 181708 0.00% 0.00% diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index df59304a0..e92014927 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.142345 # Number of seconds simulated -sim_ticks 5142345332000 # Number of ticks simulated -final_tick 5142345332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.145152 # Number of seconds simulated +sim_ticks 5145151650500 # Number of ticks simulated +final_tick 5145151650500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 328643 # Simulator instruction rate (inst/s) -host_op_rate 653294 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6944434004 # Simulator tick rate (ticks/s) -host_mem_usage 993680 # Number of bytes of host memory used -host_seconds 740.50 # Real time elapsed on the host -sim_insts 243359937 # Number of instructions simulated -sim_ops 483763631 # Number of ops (including micro ops) simulated +host_inst_rate 272385 # Simulator instruction rate (inst/s) +host_op_rate 541465 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5759353840 # Simulator tick rate (ticks/s) +host_mem_usage 1031560 # Number of bytes of host memory used +host_seconds 893.36 # Real time elapsed on the host +sim_insts 243336751 # Number of instructions simulated +sim_ops 483720414 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 463872 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5043712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 148160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2254656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 338432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 3039936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 460480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5461312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 120640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2033024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 372928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2832128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11319616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 463872 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 148160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 338432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 950464 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9139904 # Number of bytes written to this memory -system.physmem.bytes_written::total 9139904 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7248 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78808 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35229 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 34 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5288 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 47499 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11311232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 460480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 120640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 372928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 954048 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9134592 # Number of bytes written to this memory +system.physmem.bytes_written::total 9134592 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7195 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 85333 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 31766 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5827 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 44252 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176869 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 142811 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142811 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 980819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 438449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 65813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 591157 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2201256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 65813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 184831 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1777380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1777380 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1777380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 980819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 438449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 65813 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 591157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3978636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 90808 # Number of read requests accepted -system.physmem.writeReqs 80864 # Number of write requests accepted -system.physmem.readBursts 90808 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 80864 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5799936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11776 # Total number of bytes read from write queue -system.physmem.bytesWritten 5173504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5811712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5175296 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 184 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 176738 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 142728 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142728 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 89498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1061448 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 23447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 395134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 72481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 550446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5510 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2198425 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 89498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 72481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 185427 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1775379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1775379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1775379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 89498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1061448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 23447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 395134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 72481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 550446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3973804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 84206 # Number of read requests accepted +system.physmem.writeReqs 79488 # Number of write requests accepted +system.physmem.readBursts 84206 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 79488 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5382080 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue +system.physmem.bytesWritten 5087168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5389184 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5087232 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 28946 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5471 # Per bank write bursts -system.physmem.perBankRdBursts::1 4964 # Per bank write bursts -system.physmem.perBankRdBursts::2 5622 # Per bank write bursts -system.physmem.perBankRdBursts::3 5619 # Per bank write bursts -system.physmem.perBankRdBursts::4 5375 # Per bank write bursts -system.physmem.perBankRdBursts::5 4811 # Per bank write bursts -system.physmem.perBankRdBursts::6 5429 # Per bank write bursts -system.physmem.perBankRdBursts::7 5659 # Per bank write bursts -system.physmem.perBankRdBursts::8 5571 # Per bank write bursts -system.physmem.perBankRdBursts::9 5234 # Per bank write bursts -system.physmem.perBankRdBursts::10 5583 # Per bank write bursts -system.physmem.perBankRdBursts::11 5583 # Per bank write bursts -system.physmem.perBankRdBursts::12 6015 # Per bank write bursts -system.physmem.perBankRdBursts::13 6427 # Per bank write bursts -system.physmem.perBankRdBursts::14 6843 # Per bank write bursts -system.physmem.perBankRdBursts::15 6418 # Per bank write bursts -system.physmem.perBankWrBursts::0 5328 # Per bank write bursts -system.physmem.perBankWrBursts::1 5179 # Per bank write bursts -system.physmem.perBankWrBursts::2 4756 # Per bank write bursts -system.physmem.perBankWrBursts::3 4771 # Per bank write bursts -system.physmem.perBankWrBursts::4 5274 # Per bank write bursts -system.physmem.perBankWrBursts::5 4797 # Per bank write bursts -system.physmem.perBankWrBursts::6 4981 # Per bank write bursts -system.physmem.perBankWrBursts::7 4962 # Per bank write bursts -system.physmem.perBankWrBursts::8 4826 # Per bank write bursts -system.physmem.perBankWrBursts::9 4673 # Per bank write bursts -system.physmem.perBankWrBursts::10 4967 # Per bank write bursts -system.physmem.perBankWrBursts::11 4883 # Per bank write bursts -system.physmem.perBankWrBursts::12 5134 # Per bank write bursts -system.physmem.perBankWrBursts::13 5204 # Per bank write bursts -system.physmem.perBankWrBursts::14 5383 # Per bank write bursts -system.physmem.perBankWrBursts::15 5718 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5096 # Per bank write bursts +system.physmem.perBankRdBursts::1 4624 # Per bank write bursts +system.physmem.perBankRdBursts::2 5310 # Per bank write bursts +system.physmem.perBankRdBursts::3 5338 # Per bank write bursts +system.physmem.perBankRdBursts::4 5132 # Per bank write bursts +system.physmem.perBankRdBursts::5 4140 # Per bank write bursts +system.physmem.perBankRdBursts::6 4924 # Per bank write bursts +system.physmem.perBankRdBursts::7 5068 # Per bank write bursts +system.physmem.perBankRdBursts::8 5142 # Per bank write bursts +system.physmem.perBankRdBursts::9 4820 # Per bank write bursts +system.physmem.perBankRdBursts::10 5253 # Per bank write bursts +system.physmem.perBankRdBursts::11 5392 # Per bank write bursts +system.physmem.perBankRdBursts::12 5342 # Per bank write bursts +system.physmem.perBankRdBursts::13 6011 # Per bank write bursts +system.physmem.perBankRdBursts::14 6494 # Per bank write bursts +system.physmem.perBankRdBursts::15 6009 # Per bank write bursts +system.physmem.perBankWrBursts::0 5355 # Per bank write bursts +system.physmem.perBankWrBursts::1 5372 # Per bank write bursts +system.physmem.perBankWrBursts::2 5018 # Per bank write bursts +system.physmem.perBankWrBursts::3 4968 # Per bank write bursts +system.physmem.perBankWrBursts::4 5041 # Per bank write bursts +system.physmem.perBankWrBursts::5 4268 # Per bank write bursts +system.physmem.perBankWrBursts::6 4490 # Per bank write bursts +system.physmem.perBankWrBursts::7 4780 # Per bank write bursts +system.physmem.perBankWrBursts::8 5008 # Per bank write bursts +system.physmem.perBankWrBursts::9 4638 # Per bank write bursts +system.physmem.perBankWrBursts::10 4962 # Per bank write bursts +system.physmem.perBankWrBursts::11 5159 # Per bank write bursts +system.physmem.perBankWrBursts::12 4729 # Per bank write bursts +system.physmem.perBankWrBursts::13 5005 # Per bank write bursts +system.physmem.perBankWrBursts::14 5381 # Per bank write bursts +system.physmem.perBankWrBursts::15 5313 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5141345197000 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 5144151504000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 90808 # Read request sizes (log2) +system.physmem.readPktSize::6 84206 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 80864 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 85390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 178 # What read queue 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(log2) +system.physmem.rdQLenPdf::0 79978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 412 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 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read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 273.144621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.560811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.725081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16113 40.11% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9912 24.67% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4303 10.71% 75.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2413 6.01% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1642 4.09% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1065 2.65% 88.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 735 1.83% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 648 1.61% 91.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3343 8.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40174 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.121094 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 231.669266 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4094 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4096 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.735352 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.630791 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.122766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 68 1.66% 1.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 3 0.07% 1.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.02% 1.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.12% 1.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3465 84.59% 86.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 91 2.22% 88.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 32 0.78% 89.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 114 2.78% 92.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 13 0.32% 92.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 74 1.81% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 48 1.17% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.07% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.32% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.24% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.17% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.05% 96.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 111 2.71% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.10% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 16 0.39% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.07% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.15% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4096 # Writes before turning the bus around for reads -system.physmem.totQLat 1084591495 # Total ticks spent queuing -system.physmem.totMemAccLat 2783791495 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 453120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11968.04 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 17 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 271.729236 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.741988 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.469956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15728 40.82% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9476 24.60% 65.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4018 10.43% 75.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2235 5.80% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1484 3.85% 85.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1040 2.70% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 621 1.61% 89.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 586 1.52% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3340 8.67% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38528 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.323865 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 241.560167 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3765 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-14847 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3767 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.100876 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.013157 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 16.139837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 73 1.94% 1.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 5 0.13% 2.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.05% 2.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 10 0.27% 2.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3150 83.62% 86.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 90 2.39% 88.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 37 0.98% 89.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 29 0.77% 90.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 11 0.29% 90.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.40% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 49 1.30% 92.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 5 0.13% 92.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 97 2.57% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.13% 94.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.13% 95.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.16% 95.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 56 1.49% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.05% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.11% 96.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.69% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 71 1.88% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.24% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.11% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3767 # Writes before turning the bus around for reads +system.physmem.totQLat 976693078 # Total ticks spent queuing +system.physmem.totMemAccLat 2553474328 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 420475000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11614.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30718.04 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.01 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.13 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.01 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30364.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.99 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.79 # Average write queue length when enqueuing -system.physmem.readRowHits 72353 # Number of row buffer hits during reads -system.physmem.writeRowHits 58932 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.88 # Row buffer hit rate for writes -system.physmem.avgGap 29948653.23 # Average gap between requests -system.physmem.pageHitRate 76.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 144214560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 78573000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 335010000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 259511040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96378538635 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2237986517250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2585666472645 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.978665 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3687486057488 # Time in different power states -system.physmem_0.memoryStateTime::REF 128059360000 # Time in different power states +system.physmem.avgWrQLen 6.49 # Average write queue length when enqueuing +system.physmem.readRowHits 66583 # Number of row buffer hits during reads +system.physmem.writeRowHits 58470 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes +system.physmem.avgGap 31425412.68 # Average gap between requests +system.physmem.pageHitRate 76.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 137463480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 74835750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 309129600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254612160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250601076960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 95881334760 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2241313470000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2588571922710 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.897936 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3690036314984 # Time in different power states +system.physmem_0.memoryStateTime::REF 128119160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 19884905262 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19076389516 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 159500880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86876625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 371841600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 264306240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250484108160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 97163933940 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2232534954750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581065522195 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.160201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3686335779224 # Time in different power states -system.physmem_1.memoryStateTime::REF 128059360000 # Time in different power states +system.physmem_1.actEnergy 153808200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83729250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 346803600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 260463600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250601076960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96592845240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2234121702750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2582160429600 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.130643 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3689011276980 # Time in different power states +system.physmem_1.memoryStateTime::REF 128119160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21009267026 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20078331770 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1088115959 # number of cpu cycles simulated +system.cpu0.numCycles 1088692410 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.committedInsts 71651877 # Number of instructions committed -system.cpu0.committedOps 146177129 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134125177 # Number of integer alu accesses +system.cpu0.committedInsts 72035509 # Number of instructions committed +system.cpu0.committedOps 146805199 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 134737053 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 958449 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14231951 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134125177 # number of integer instructions +system.cpu0.num_func_calls 969730 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14267962 # number of instructions that are conditional controls +system.cpu0.num_int_insts 134737053 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 245781224 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115362346 # number of times the integer registers were written +system.cpu0.num_int_register_reads 247210570 # number of times the integer registers were read +system.cpu0.num_int_register_writes 115779061 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83627387 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55829285 # number of times the CC registers were written -system.cpu0.num_mem_refs 13623500 # number of memory refs -system.cpu0.num_load_insts 10168797 # Number of load instructions -system.cpu0.num_store_insts 3454703 # Number of store instructions -system.cpu0.num_idle_cycles 1031530406.657702 # Number of idle cycles -system.cpu0.num_busy_cycles 56585552.342298 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052003 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947997 # Percentage of idle cycles -system.cpu0.Branches 15545637 # Number of branches fetched -system.cpu0.op_class::No_OpClass 91075 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132356346 90.54% 90.61% # Class of executed instruction -system.cpu0.op_class::IntMult 58823 0.04% 90.65% # Class of executed instruction -system.cpu0.op_class::IntDiv 49650 0.03% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.68% # Class of executed instruction -system.cpu0.op_class::MemRead 10166974 6.96% 97.64% # Class of executed instruction -system.cpu0.op_class::MemWrite 3454703 2.36% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83908421 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55985088 # number of times the CC registers were written +system.cpu0.num_mem_refs 13846193 # number of memory refs +system.cpu0.num_load_insts 10242461 # Number of load instructions +system.cpu0.num_store_insts 3603732 # Number of store instructions +system.cpu0.num_idle_cycles 1032281888.672235 # Number of idle cycles +system.cpu0.num_busy_cycles 56410521.327765 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051815 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948185 # Percentage of idle cycles +system.cpu0.Branches 15596726 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94997 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132756064 90.43% 90.49% # Class of executed instruction +system.cpu0.op_class::IntMult 60391 0.04% 90.54% # Class of executed instruction +system.cpu0.op_class::IntDiv 49910 0.03% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.57% # Class of executed instruction +system.cpu0.op_class::MemRead 10240627 6.98% 97.55% # Class of executed instruction +system.cpu0.op_class::MemWrite 3603732 2.45% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146177571 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1639042 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999458 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19611882 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639554 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.961718 # Average number of references to valid blocks. +system.cpu0.op_class::total 146805721 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1638200 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999475 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19659628 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638712 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 11.997000 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 186.987910 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.755532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 116.256017 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365211 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407726 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.227063 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 187.218245 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.811458 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 115.969772 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.365661 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.226503 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 215 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id 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number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9785 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 28212 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59535 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8261761 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4256710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7032021 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19550492 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8283299 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4266495 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7060233 # number of overall hits -system.cpu0.dcache.overall_hits::total 19610027 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 366824 # number of ReadReq misses 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uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 639710000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 711714500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1351424500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31278342000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33745348000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65023690000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059966 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087419 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045438 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034238 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.033163 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019789 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.859324 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.856344 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.532877 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.049443 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066080 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.035255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.061827 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087372 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.045964 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13624.045020 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14133.220985 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13993.926362 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 69744.656029 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 53347.457340 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 59528.860818 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17302.477500 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15798.619991 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16160.737951 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 29518.398866 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21873.285455 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24140.923273 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26922.310374 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20269.198481 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22149.941031 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173931.934171 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170384.488619 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172073.252169 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 194145.675266 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206174.536501 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200300.059286 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174303.096162 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 171010.586381 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172578.713669 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 1548224 # number of writebacks +system.cpu0.dcache.writebacks::total 1548224 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 71 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 347686 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 347757 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1725 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 33527 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 35252 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1796 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 381213 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 383009 # number of demand (read+write) MSHR hits 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+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7208014495 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 13807580903 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21015595398 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30625317500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33009151000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63634468500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 615059500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 691101000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1306160500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31240377000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33700252000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64940629000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059272 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088133 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045089 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034923 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031128 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018634 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.860396 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.855326 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.529416 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.049415 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066110 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034599 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.062387 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087424 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045231 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13664.782647 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13755.283656 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13730.323904 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61827.519393 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 56622.426973 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 58740.936040 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17214.228009 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15209.951675 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15722.883458 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27443.980394 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 21553.114453 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.860098 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25187.347978 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19877.061513 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21426.447529 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173932.378632 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 170361.018786 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172061.315015 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 195318.990156 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 206916.467066 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 201288.411157 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174308.143395 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170980.476915 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172565.280011 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 863213 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.772348 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129563028 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 863725 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 150.004953 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149035233500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 148.852314 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 120.504208 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 241.415826 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.290727 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.235360 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.471515 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997602 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 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(read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5288988973 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7533033473 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2244044500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5288988973 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7533033473 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004163 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004163 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004258 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.112313 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004163 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13824.083625 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13824.083625 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13357.646267 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 14031.977197 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13824.083625 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608019031 # number of cpu cycles simulated +system.cpu1.numCycles 2608700985 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 35872545 # Number of instructions committed -system.cpu1.committedOps 69699402 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64677814 # Number of integer alu accesses +system.cpu1.committedInsts 35853190 # Number of instructions committed +system.cpu1.committedOps 69637325 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64624192 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 478121 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6602854 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64677814 # number of integer instructions +system.cpu1.num_func_calls 480821 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6584072 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64624192 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119785728 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55703367 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119734930 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55665261 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36592003 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27221835 # number of times the CC registers were written -system.cpu1.num_mem_refs 4725252 # number of memory refs -system.cpu1.num_load_insts 2891470 # Number of load instructions -system.cpu1.num_store_insts 1833782 # Number of store instructions -system.cpu1.num_idle_cycles 2475574417.457654 # Number of idle cycles -system.cpu1.num_busy_cycles 132444613.542345 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050784 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949216 # Percentage of idle cycles -system.cpu1.Branches 7256649 # Number of branches fetched -system.cpu1.op_class::No_OpClass 36799 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64882747 93.09% 93.14% # Class of executed instruction -system.cpu1.op_class::IntMult 30615 0.04% 93.19% # Class of executed instruction -system.cpu1.op_class::IntDiv 25662 0.04% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.22% # Class of executed instruction -system.cpu1.op_class::MemRead 2890134 4.15% 97.37% # Class of executed instruction -system.cpu1.op_class::MemWrite 1833782 2.63% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36441615 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27163948 # number of times the CC registers were written +system.cpu1.num_mem_refs 4762653 # number of memory refs +system.cpu1.num_load_insts 2934148 # Number of load instructions +system.cpu1.num_store_insts 1828505 # Number of store instructions +system.cpu1.num_idle_cycles 2477829433.289960 # Number of idle cycles +system.cpu1.num_busy_cycles 130871551.710040 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050167 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949833 # Percentage of idle cycles +system.cpu1.Branches 7242423 # Number of branches fetched +system.cpu1.op_class::No_OpClass 33618 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64788264 93.04% 93.08% # Class of executed instruction +system.cpu1.op_class::IntMult 30568 0.04% 93.13% # Class of executed instruction +system.cpu1.op_class::IntDiv 23981 0.03% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.16% # Class of executed instruction +system.cpu1.op_class::MemRead 2932794 4.21% 97.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 1828505 2.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69699739 # Class of executed instruction -system.cpu2.branchPred.lookups 28904699 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28904699 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 301799 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26182960 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25618019 # Number of BTB hits +system.cpu1.op_class::total 69637730 # Class of executed instruction +system.cpu2.branchPred.lookups 28889322 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28889322 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 295969 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26161863 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25623496 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.842333 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 577766 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 65377 # Number of incorrect RAS predictions. -system.cpu2.numCycles 157028917 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.942169 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 568311 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63642 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155802495 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10756065 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 142934226 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 28904699 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26195785 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 144559167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 634442 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 102497 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 11445 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 9293 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 61170 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 12 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 1572 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3392030 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 159049 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2822 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 155817791 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.805701 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.007704 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10515897 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142640150 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28889322 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26191807 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143559452 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 620364 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 87827 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9842 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 11126 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 54390 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 17 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 1387 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3356023 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 154184 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2703 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154549468 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.817375 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.013614 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 100969926 64.80% 64.80% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 864181 0.55% 65.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23515186 15.09% 80.45% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 574321 0.37% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 784323 0.50% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 832797 0.53% 81.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 526849 0.34% 82.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 721182 0.46% 82.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27029026 17.35% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 99785668 64.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 851405 0.55% 65.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23501964 15.21% 80.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 570178 0.37% 80.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 787471 0.51% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 829399 0.54% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 530756 0.34% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 713885 0.46% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 26978742 17.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155817791 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.184072 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.910241 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9372643 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95636804 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 20963245 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4000269 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 317872 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 278646605 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 317872 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10991831 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 77276692 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 5181011 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 23079329 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13444163 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 277492076 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 194116 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5314185 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 68849 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 6513408 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 331462631 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 605120715 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 371802312 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 234 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320362920 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11099709 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 163935 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 165202 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 19836823 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6505105 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3734190 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 446981 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 391369 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 275686580 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 411981 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 273842853 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 94839 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8211456 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12322633 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64605 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155817791 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.757456 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.386043 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154549468 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.185423 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.915519 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9161947 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94660451 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22362416 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3983614 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 310834 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278186393 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 310834 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10773754 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76930615 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4967111 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24468455 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13028558 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277047338 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 190678 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5336222 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 56223 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 6096944 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331227284 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 604004541 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 370955338 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 211 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 319831441 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11395843 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 155918 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 157041 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 19693984 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6408841 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3580904 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 429275 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 378401 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275247067 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 403961 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273265487 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 91844 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8373138 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12782922 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 62096 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154549468 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.768143 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.389638 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 93841974 60.23% 60.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5140662 3.30% 63.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3701702 2.38% 65.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3241767 2.08% 67.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 23231728 14.91% 82.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2206356 1.42% 84.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23779364 15.26% 99.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 455294 0.29% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 218944 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 92779587 60.03% 60.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5028830 3.25% 63.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3690380 2.39% 65.67% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3236781 2.09% 67.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 23211705 15.02% 82.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2188888 1.42% 84.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23752986 15.37% 99.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 446110 0.29% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 214201 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155817791 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154549468 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1209883 81.76% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 81.76% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 208644 14.10% 95.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 61248 4.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1203384 82.42% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 82.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 197980 13.56% 95.97% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 58776 4.03% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 74059 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 263387979 96.18% 96.21% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 56208 0.02% 96.23% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 48343 0.02% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 104 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.25% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6817856 2.49% 98.74% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3458304 1.26% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 71495 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263081199 96.27% 96.30% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54839 0.02% 96.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49922 0.02% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 90 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.34% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6697042 2.45% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3310900 1.21% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 273842853 # Type of FU issued -system.cpu2.iq.rate 1.743901 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1479775 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.005404 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 705077754 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 284314372 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272343231 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 356 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 332 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 144 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 275248392 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 717023 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273265487 # Type of FU issued +system.cpu2.iq.rate 1.753922 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1460140 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.005343 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 702632101 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284028018 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 271786365 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 325 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 130 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 274653974 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 158 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 690819 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1119882 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 5658 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5248 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 603569 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1132838 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5529 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4669 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 589748 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 712184 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 25029 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 711826 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 19138 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 317872 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 69999671 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 4334406 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276098561 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 36227 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6505105 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3734190 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 245180 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 161697 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 3862519 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5248 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 168896 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 180792 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 349688 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273296807 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6682967 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 496833 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 310834 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 69908252 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 4108684 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275651028 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 34465 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6408841 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3580904 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 237862 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 162562 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3635003 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4669 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 168040 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 174694 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 342734 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 272728091 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6566445 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 490893 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 10058933 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27720177 # Number of branches executed -system.cpu2.iew.exec_stores 3375966 # Number of stores executed -system.cpu2.iew.exec_rate 1.740423 # Inst execution rate -system.cpu2.iew.wb_sent 273120714 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272343375 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212424693 # num instructions producing a value -system.cpu2.iew.wb_consumers 348436865 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.734352 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609650 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 8207919 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 347376 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 304652 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 154587808 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.732912 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.636931 # Number of insts commited each cycle +system.cpu2.iew.exec_refs 9797112 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27676327 # Number of branches executed +system.cpu2.iew.exec_stores 3230667 # Number of stores executed +system.cpu2.iew.exec_rate 1.750473 # Inst execution rate +system.cpu2.iew.wb_sent 272561668 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 271786495 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 212223501 # num instructions producing a value +system.cpu2.iew.wb_consumers 348135650 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.744430 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609600 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 8370841 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 341865 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 298631 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153304959 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.743439 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.641523 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 97422616 63.02% 63.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4263028 2.76% 65.78% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258481 0.81% 66.59% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24441508 15.81% 82.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 948995 0.61% 83.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 702646 0.45% 83.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 422583 0.27% 83.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23085730 14.93% 98.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2042221 1.32% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 96327195 62.83% 62.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4172265 2.72% 65.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1243558 0.81% 66.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24424351 15.93% 82.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 933210 0.61% 82.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 700271 0.46% 83.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 423861 0.28% 83.64% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23073889 15.05% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2006359 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 154587808 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135835515 # Number of instructions committed -system.cpu2.commit.committedOps 267887100 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153304959 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135448052 # Number of instructions committed +system.cpu2.commit.committedOps 267277890 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8515843 # Number of memory references committed -system.cpu2.commit.loads 5385222 # Number of loads committed -system.cpu2.commit.membars 151391 # Number of memory barriers committed -system.cpu2.commit.branches 27354284 # Number of branches committed +system.cpu2.commit.refs 8267159 # Number of memory references committed +system.cpu2.commit.loads 5276003 # Number of loads committed +system.cpu2.commit.membars 150855 # Number of memory barriers committed +system.cpu2.commit.branches 27313126 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244770291 # Number of committed integer instructions. -system.cpu2.commit.function_calls 437535 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 44208 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259226210 96.77% 96.78% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 54262 0.02% 96.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 46624 0.02% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.82% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5385159 2.01% 98.83% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3130621 1.17% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244177571 # Number of committed integer instructions. +system.cpu2.commit.function_calls 431165 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 43823 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258865945 96.85% 96.87% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52891 0.02% 96.89% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 48103 0.02% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.91% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5275956 1.97% 98.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2991156 1.12% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 267887100 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2042221 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 428611967 # The number of ROB reads -system.cpu2.rob.rob_writes 553425779 # The number of ROB writes -system.cpu2.timesIdled 117856 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1211126 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4911627157 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135835515 # Number of Instructions Simulated -system.cpu2.committedOps 267887100 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.156023 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.156023 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.865035 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.865035 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364164831 # number of integer regfile reads -system.cpu2.int_regfile_writes 218212592 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73112 # number of floating regfile reads +system.cpu2.commit.op_class_0::total 267277890 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2006359 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 426921144 # The number of ROB reads +system.cpu2.rob.rob_writes 552547339 # The number of ROB writes +system.cpu2.timesIdled 113614 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1253027 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4915786083 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135448052 # Number of Instructions Simulated +system.cpu2.committedOps 267277890 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.150275 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.150275 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.869357 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.869357 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363036550 # number of integer regfile reads +system.cpu2.int_regfile_writes 217868300 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73154 # number of floating regfile reads system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 138818129 # number of cc regfile reads -system.cpu2.cc_regfile_writes 106823368 # number of cc regfile writes -system.cpu2.misc_regfile_reads 88818544 # number of misc regfile reads -system.cpu2.misc_regfile_writes 142989 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3545369 # Transaction distribution -system.iobus.trans_dist::ReadResp 3545369 # Transaction distribution -system.iobus.trans_dist::WriteReq 57733 # Transaction distribution -system.iobus.trans_dist::WriteResp 57733 # Transaction distribution -system.iobus.trans_dist::MessageReq 1667 # Transaction distribution -system.iobus.trans_dist::MessageResp 1667 # Transaction distribution +system.cpu2.cc_regfile_reads 138663599 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106715601 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88486209 # number of misc regfile reads +system.cpu2.misc_regfile_writes 136274 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3545384 # Transaction distribution +system.iobus.trans_dist::ReadResp 3545384 # Transaction distribution +system.iobus.trans_dist::WriteReq 57740 # Transaction distribution +system.iobus.trans_dist::WriteResp 57740 # Transaction distribution +system.iobus.trans_dist::MessageReq 1683 # Transaction distribution +system.iobus.trans_dist::MessageResp 1683 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7066646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1182 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27896 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7110938 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95266 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3334 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7209538 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7110986 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7209614 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3533323 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2364 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13933 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13948 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3561710 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6596226 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2386632 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3561695 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6732 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6732 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6596259 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2351548 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 41000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 6479000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5836500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 921000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 921500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 40500 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) @@ -1202,68 +1209,68 @@ system.iobus.reqLayer7.occupancy 21000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 199976000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 478500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 454000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 170000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11054500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 10925000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 117264991 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 135494828 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1060500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 284201000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 283574000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 25798000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 29242000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 987000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 969000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47578 # number of replacements -system.iocache.tags.tagsinuse 0.106179 # Cycle average of tags in use +system.iocache.tags.replacements 47576 # number of replacements +system.iocache.tags.tagsinuse 0.114834 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47594 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 5000689447509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106179 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.114834 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007177 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007177 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428697 # Number of tag accesses -system.iocache.tags.data_accesses 428697 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses -system.iocache.ReadReq_misses::total 913 # number of ReadReq misses +system.iocache.tags.tag_accesses 428679 # Number of tag accesses +system.iocache.tags.data_accesses 428679 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses -system.iocache.demand_misses::pc.south_bridge.ide 913 # number of demand (read+write) misses -system.iocache.demand_misses::total 913 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 913 # number of overall misses -system.iocache.overall_misses::total 913 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 126475754 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 126475754 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 2945894237 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 2945894237 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 126475754 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 126475754 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 126475754 # number of overall miss cycles -system.iocache.overall_miss_latency::total 126475754 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses +system.iocache.demand_misses::total 911 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses +system.iocache.overall_misses::total 911 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130436776 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 130436776 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 3277643052 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 3277643052 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 130436776 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 130436776 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 130436776 # number of overall miss cycles +system.iocache.overall_miss_latency::total 130436776 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 913 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 913 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 913 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 913 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses @@ -1272,327 +1279,341 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 138527.660460 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 63054.243086 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 63054.243086 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 138527.660460 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138527.660460 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 138527.660460 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 657 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 143179.776070 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 143179.776070 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 70155.031079 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 70155.031079 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 143179.776070 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 143179.776070 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 143179.776070 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 143179.776070 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 254 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 59 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 23 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.135593 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.043478 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 755 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 755 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 22656 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 22656 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 755 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 755 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 755 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 755 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 88725754 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1813094237 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 1813094237 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 88725754 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88725754 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 88725754 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.826944 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.484932 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.484932 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.826944 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.826944 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.826944 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117517.554967 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 80027.111450 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80027.111450 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117517.554967 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117517.554967 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117517.554967 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 757 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 757 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 26096 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 26096 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 757 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 757 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 757 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 757 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92586776 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 92586776 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 1971782289 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 1971782289 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 92586776 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 92586776 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 92586776 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 92586776 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.830955 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.830955 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 0.558562 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.558562 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.830955 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.830955 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.830955 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.830955 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 122307.498018 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75558.794030 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75558.794030 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 122307.498018 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 122307.498018 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 122307.498018 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104233 # number of replacements -system.l2c.tags.tagsinuse 64807.184468 # Cycle average of tags in use -system.l2c.tags.total_refs 4648895 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 27.601512 # Average number of references to valid blocks. +system.l2c.tags.replacements 104171 # number of replacements +system.l2c.tags.tagsinuse 64805.453766 # Cycle average of tags in use +system.l2c.tags.total_refs 4641601 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168365 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 27.568681 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50959.111320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.136263 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1606.978228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4944.954504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 496.939087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1891.921055 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.257150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 951.270746 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3946.616114 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777574 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50961.018177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1604.778639 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4964.722322 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 496.770357 # Average occupied blocks per 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+system.l2c.ReadReq_mshr_miss_latency::total 4608000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 23180500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 24515500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 47696000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3169658500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4136862000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7306520500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 227080000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 731219008 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 958299008 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 595125000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 1233657003 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1828782003 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 227080000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3764783500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 4471000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 137000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 731219008 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 5370519003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10098209511 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 227080000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3764783500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 4471000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 137000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 731219008 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 5370519003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10098209511 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 28424367000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30587128500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59011495500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 578845500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 652662500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1231508000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 29003212500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 31239791000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60243003500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.796729 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.839161 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.425364 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.428290 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.375181 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.213812 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.008944 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021789 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.016437 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.010920 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.111962 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.064279 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.032235 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011220 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.111962 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000083 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015459 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.064279 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.032235 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 139636.363636 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67978.005865 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 68098.611111 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68039.942939 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 116754.770149 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 119097.797610 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 118069.914193 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 124260.763485 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 122832.817337 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 124750.430074 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 124119.859034 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117675.225831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 120350.461702 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 119700.925903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120466.843501 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117675.225831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 139718.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 137000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 125488.074138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 120350.461702 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 119700.925903 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161432.375792 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157860.902663 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 159561.252826 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183818.831375 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 195407.934132 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 189783.942056 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 161825.707909 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158497.163876 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 160082.384907 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5063475 # Transaction distribution -system.membus.trans_dist::ReadResp 5112044 # Transaction distribution -system.membus.trans_dist::WriteReq 13928 # Transaction distribution -system.membus.trans_dist::WriteResp 13928 # Transaction distribution -system.membus.trans_dist::WritebackDirty 142811 # Transaction distribution -system.membus.trans_dist::CleanEvict 8387 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1702 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1702 # Transaction distribution -system.membus.trans_dist::ReadExReq 129429 # Transaction distribution -system.membus.trans_dist::ReadExResp 129429 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 48569 # Transaction distribution -system.membus.trans_dist::MessageReq 1667 # Transaction distribution -system.membus.trans_dist::MessageResp 1667 # Transaction distribution +system.membus.trans_dist::ReadReq 5063492 # Transaction distribution +system.membus.trans_dist::ReadResp 5112114 # Transaction distribution +system.membus.trans_dist::WriteReq 13953 # Transaction distribution +system.membus.trans_dist::WriteResp 13953 # Transaction distribution +system.membus.trans_dist::WritebackDirty 142728 # Transaction distribution +system.membus.trans_dist::CleanEvict 8956 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1657 # Transaction distribution +system.membus.trans_dist::UpgradeResp 756 # Transaction distribution +system.membus.trans_dist::ReadExReq 129246 # Transaction distribution +system.membus.trans_dist::ReadExResp 129246 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 48622 # Transaction distribution +system.membus.trans_dist::MessageReq 1683 # Transaction distribution +system.membus.trans_dist::MessageResp 1683 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3334 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110938 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043868 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 461232 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10616038 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141982 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10761354 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6668 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561710 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087733 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17454144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27103587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3025152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3025152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 30135407 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 824 # Total snoops (count) -system.membus.snoop_fanout::samples 5457240 # Request fanout histogram -system.membus.snoop_fanout::mean 1.000305 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.017475 # Request fanout histogram +system.membus.trans_dist::InvalidateResp 20624 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3366 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7110986 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3043904 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 460036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10614926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 116428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 116428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10734720 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6732 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6732 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3561695 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6087805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17447936 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27097436 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3024896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3024896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30129064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 713 # Total snoops (count) +system.membus.snoop_fanout::samples 5457064 # Request fanout histogram +system.membus.snoop_fanout::mean 1.000308 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.017559 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 5455573 99.97% 99.97% # Request fanout histogram -system.membus.snoop_fanout::2 1667 0.03% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 5455381 99.97% 99.97% # Request fanout histogram +system.membus.snoop_fanout::2 1683 0.03% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 5457240 # Request fanout histogram -system.membus.reqLayer0.occupancy 220305500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5457064 # Request fanout histogram +system.membus.reqLayer0.occupancy 219508500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 286836500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 286793500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2385368 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2349452 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 534782231 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 523492338 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1398368 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1380452 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1230215238 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1192096252 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 43264654 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 3875571 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -1812,60 +1845,60 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.snoop_filter.tot_requests 5045999 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2542699 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 716 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1209 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1209 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5037396 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2536385 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 720 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1161 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1161 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 5211020 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7425092 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13930 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13930 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 1629876 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 862717 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 95523 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1686 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1686 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 289480 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 289480 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 863740 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1350844 # Transaction distribution -system.toL2Bus.trans_dist::MessageReq 987 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 22656 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2590172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15076396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68863 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 204307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17939738 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110491648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213734051 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 254408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 750576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 325230683 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 223463 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8879878 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.004588 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.067577 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5204527 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7416348 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13955 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13955 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1627719 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 861781 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 95177 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1648 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1648 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 289427 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 289427 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 862301 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1350048 # Transaction distribution +system.toL2Bus.trans_dist::MessageReq 969 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 26096 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2586381 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15074051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 68680 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 194868 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17923980 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 110341120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213628444 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 723128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 324949652 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 219979 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8897461 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.004125 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.064090 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 8839140 99.54% 99.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 40738 0.46% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 8860763 99.59% 99.59% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 36698 0.41% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8879878 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3300004999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8897461 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3238433000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 437354 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 410366 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 839896281 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 817982794 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1865125250 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1843572784 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 24363482 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 22804980 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 87735122 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 80183573 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 508ed63ed..5d753bb44 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061241 # Nu sim_ticks 61241011500 # Number of ticks simulated final_tick 61241011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 266495 # Simulator instruction rate (inst/s) -host_op_rate 267822 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 180131185 # Simulator tick rate (ticks/s) -host_mem_usage 451088 # Number of bytes of host memory used -host_seconds 339.98 # Real time elapsed on the host +host_inst_rate 253883 # Simulator instruction rate (inst/s) +host_op_rate 255147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171606317 # Simulator tick rate (ticks/s) +host_mem_usage 452068 # Number of bytes of host memory used +host_seconds 356.87 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -791,18 +791,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 904230 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 943278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2670 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46765 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 903428 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846334 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2847942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846483 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121233728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121233792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 950995 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 8cda29cfd..9603ee85e 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,111 +1,111 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058178 # Number of seconds simulated -sim_ticks 58178156500 # Number of ticks simulated -final_tick 58178156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058179 # Number of seconds simulated +sim_ticks 58178990500 # Number of ticks simulated +final_tick 58178990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123327 # Simulator instruction rate (inst/s) -host_op_rate 123942 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79202629 # Simulator tick rate (ticks/s) -host_mem_usage 528964 # Number of bytes of host memory used -host_seconds 734.55 # Real time elapsed on the host +host_inst_rate 122973 # Simulator instruction rate (inst/s) +host_op_rate 123585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 78976040 # Simulator tick rate (ticks/s) +host_mem_usage 539340 # Number of bytes of host memory used +host_seconds 736.67 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 55744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 924288 # Number of bytes read from this memory -system.physmem.bytes_read::total 1024768 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 10048 # Number of bytes written to this memory -system.physmem.bytes_written::total 10048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 16012 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 157 # Number of write requests responded to by this memory -system.physmem.num_writes::total 157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 768948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 958160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15887200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17614309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 768948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 768948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 172711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 172711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 172711 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 768948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 958160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15887200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17787019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 16013 # Number of read requests accepted -system.physmem.writeReqs 157 # Number of write requests accepted -system.physmem.readBursts 16013 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1017152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 8064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1024832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 56 # Number of requests that are neither read nor write +system.physmem.bytes_read::cpu.inst 44864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 57344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 923968 # Number of bytes read from this memory +system.physmem.bytes_read::total 1026176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44864 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10880 # Number of bytes written to this memory +system.physmem.bytes_written::total 10880 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 701 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14437 # Number of read requests responded to by this memory +system.physmem.num_reads::total 16034 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 170 # Number of write requests responded to by this memory +system.physmem.num_writes::total 170 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 771137 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 985648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15881472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17638257 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 771137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 771137 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187009 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 771137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 985648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15881472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17825266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 16035 # Number of read requests accepted +system.physmem.writeReqs 170 # Number of write requests accepted +system.physmem.readBursts 16035 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 170 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1017600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8576 # Total number of bytes read from write queue +system.physmem.bytesWritten 9088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1026240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10880 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 134 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1166 # Per bank write bursts system.physmem.perBankRdBursts::1 919 # Per bank write bursts -system.physmem.perBankRdBursts::2 952 # Per bank write bursts -system.physmem.perBankRdBursts::3 1030 # Per bank write bursts +system.physmem.perBankRdBursts::2 953 # Per bank write bursts +system.physmem.perBankRdBursts::3 1033 # Per bank write bursts system.physmem.perBankRdBursts::4 1062 # Per bank write bursts -system.physmem.perBankRdBursts::5 1117 # Per bank write bursts -system.physmem.perBankRdBursts::6 1098 # Per bank write bursts -system.physmem.perBankRdBursts::7 1090 # Per bank write bursts +system.physmem.perBankRdBursts::5 1116 # Per bank write bursts +system.physmem.perBankRdBursts::6 1091 # Per bank write bursts +system.physmem.perBankRdBursts::7 1089 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 936 # Per bank write bursts -system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 905 # Per bank write bursts -system.physmem.perBankRdBursts::13 898 # Per bank write bursts -system.physmem.perBankRdBursts::14 901 # Per bank write bursts -system.physmem.perBankRdBursts::15 934 # Per bank write bursts +system.physmem.perBankRdBursts::10 937 # Per bank write bursts +system.physmem.perBankRdBursts::11 900 # Per bank write bursts +system.physmem.perBankRdBursts::12 906 # Per bank write bursts +system.physmem.perBankRdBursts::13 899 # Per bank write bursts +system.physmem.perBankRdBursts::14 910 # Per bank write bursts +system.physmem.perBankRdBursts::15 933 # Per bank write bursts system.physmem.perBankWrBursts::0 7 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 6 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 8 # Per bank write bursts +system.physmem.perBankWrBursts::2 12 # Per bank write bursts +system.physmem.perBankWrBursts::3 4 # Per bank write bursts +system.physmem.perBankWrBursts::4 3 # Per bank write bursts system.physmem.perBankWrBursts::5 12 # Per bank write bursts -system.physmem.perBankWrBursts::6 30 # Per bank write bursts +system.physmem.perBankWrBursts::6 37 # Per bank write bursts system.physmem.perBankWrBursts::7 2 # Per bank write bursts -system.physmem.perBankWrBursts::8 5 # Per bank write bursts +system.physmem.perBankWrBursts::8 2 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 11 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 4 # Per bank write bursts -system.physmem.perBankWrBursts::13 16 # Per bank write bursts -system.physmem.perBankWrBursts::14 23 # Per bank write bursts -system.physmem.perBankWrBursts::15 2 # Per bank write bursts +system.physmem.perBankWrBursts::10 6 # Per bank write bursts +system.physmem.perBankWrBursts::11 4 # Per bank write bursts +system.physmem.perBankWrBursts::12 7 # Per bank write bursts +system.physmem.perBankWrBursts::13 12 # Per bank write bursts +system.physmem.perBankWrBursts::14 33 # Per bank write bursts +system.physmem.perBankWrBursts::15 1 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58178148000 # Total gap between requests +system.physmem.totGap 58178982000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 16013 # Read request sizes (log2) +system.physmem.readPktSize::6 16035 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2533 # What read queue length does an incoming req see +system.physmem.writePktSize::6 170 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10985 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2530 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 292 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 315 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 291 # What read queue length does an incoming req see @@ -150,22 +150,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,90 +197,92 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 579.332201 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 345.781267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 429.630743 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 460 26.03% 26.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 205 11.60% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 5.26% 42.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 3.57% 46.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 46 2.60% 49.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 3.23% 52.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 50 2.83% 55.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 49 2.77% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 744 42.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1767 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2257.857143 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 93.171857 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 5824.405132 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 6 85.71% 85.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 14.29% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7 # Writes before turning the bus around for reads -system.physmem.totQLat 173222344 # Total ticks spent queuing -system.physmem.totMemAccLat 471216094 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 79465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10899.29 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29649.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.14 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s +system.physmem.bytesPerActivate::samples 1792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 572.928571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 339.689561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 430.205419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 476 26.56% 26.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 210 11.72% 38.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 97 5.41% 43.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 3.52% 47.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 46 2.57% 49.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 57 3.18% 52.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 50 2.79% 55.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 48 2.68% 58.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 745 41.57% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1792 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1980.250000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 75.328493 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 5451.280656 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.750000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.736929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.707107 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 12.50% 12.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 7 87.50% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 173529353 # Total ticks spent queuing +system.physmem.totMemAccLat 471654353 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 79500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10913.11 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4999.69 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29661.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.20 # Average write queue length when enqueuing +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.26 # Average write queue length when enqueuing system.physmem.readRowHits 14205 # Number of row buffer hits during reads -system.physmem.writeRowHits 38 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 25.00 # Row buffer hit rate for writes -system.physmem.avgGap 3597906.49 # Average gap between requests -system.physmem.pageHitRate 88.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7673400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 4186875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 65488800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 421200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2652037290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32576451750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 39105711075 # Total energy per rank (pJ) -system.physmem_0.averagePower 672.250549 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54182179525 # Time in different power states +system.physmem.writeRowHits 45 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 27.11 # Row buffer hit rate for writes +system.physmem.avgGap 3590187.10 # Average gap between requests +system.physmem.pageHitRate 88.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7794360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4252875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 65746200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 498960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2649738195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32583140250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39111131160 # Total energy per rank (pJ) +system.physmem_0.averagePower 672.253743 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54193285294 # Time in different power states system.physmem_0.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2046707975 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2043128456 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58141200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 395280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3799451760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2310125355 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32876366250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 39053220225 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.348359 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54689145986 # Time in different power states +system.physmem_1.actEnergy 5753160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3139125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58273800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 421200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3799960320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2342596545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32852562750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39062706900 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.421412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54644034494 # Time in different power states system.physmem_1.memoryStateTime::REF 1942460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1544922014 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1592379256 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28257532 # Number of BP lookups -system.cpu.branchPred.condPredicted 23279536 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837837 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11842353 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11784700 # Number of BTB hits +system.cpu.branchPred.lookups 28257760 # Number of BP lookups +system.cpu.branchPred.condPredicted 23279733 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837848 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11842330 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11784674 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.513163 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75800 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 99.513136 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75804 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -400,83 +402,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 116356314 # number of cpu cycles simulated +system.cpu.numCycles 116357982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748715 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134987552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28257532 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11860500 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 114713884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679087 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 748703 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134988401 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28257760 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11860478 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114715121 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679113 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.IcacheWaitRetryStallCycles 833 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32302381 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 573 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 116303952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.165899 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 32302514 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 574 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116305190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165894 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.319044 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58732386 50.50% 50.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13942591 11.99% 62.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230864 7.94% 70.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34398111 29.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58733287 50.50% 50.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13942631 11.99% 62.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9230901 7.94% 70.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34398371 29.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 116303952 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.242853 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.160122 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8839872 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64043721 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33034735 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9558318 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827306 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101307 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 116305190 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242852 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.160113 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8839704 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64044923 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33035218 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9558027 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827318 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101316 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 12341 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114430502 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1996250 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827306 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15281424 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49886472 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 109365 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35424721 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14774664 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110898746 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1414946 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11132654 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1143672 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1526966 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 487708 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129956476 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483272295 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119473751 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 114430969 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1996281 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827318 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15281065 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49888125 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 109559 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35425090 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14774033 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110899108 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1414941 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11132282 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143663 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1527047 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 487517 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129956871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483273963 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119474159 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 431 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22643557 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22643952 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4364 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4359 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21508806 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26812600 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5350060 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 518904 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253933 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109691142 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 21508074 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26812702 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5350076 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 518927 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 253927 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109691489 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 8248 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101388881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1075842 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18658360 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41690770 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 101389067 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075877 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18658707 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41691247 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 116303952 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.871758 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.989325 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 116305190 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871750 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989327 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54663353 47.00% 47.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31360946 26.96% 73.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22009705 18.92% 92.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7071580 6.08% 98.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1198055 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54664640 47.00% 47.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31360805 26.96% 73.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22009670 18.92% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7071691 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1198071 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -484,9 +486,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 116303952 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116305190 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9787032 48.68% 48.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9787073 48.68% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 50 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.68% # attempts to use FU when none available @@ -515,12 +517,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614737 47.82% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 704136 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9614641 47.82% 96.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 704123 3.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71984931 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71985140 71.00% 71.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 10711 0.01% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued @@ -549,82 +551,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24343463 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049594 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343416 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049618 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101388881 # Type of FU issued -system.cpu.iq.rate 0.871366 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20105968 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198305 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 340263064 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128358435 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99626003 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101389067 # Type of FU issued +system.cpu.iq.rate 0.871355 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20105900 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198304 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340264641 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128359131 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626279 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121494609 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_wakeup_accesses 113 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121494727 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 289420 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 289423 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4336689 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 4336791 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1514 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1345 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 605216 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1348 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 605232 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7563 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130752 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7566 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130606 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827306 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8114677 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 684104 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109712059 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827318 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8114310 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 683997 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109712406 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26812600 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5350060 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26812702 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5350076 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 4360 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 178830 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 342365 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1345 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436596 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412868 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849464 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100127809 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23806782 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1261072 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 178818 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 342272 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1348 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436595 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412881 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849476 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100127969 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23806710 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261098 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12669 # number of nop insts executed -system.cpu.iew.exec_refs 28724706 # number of memory reference insts executed -system.cpu.iew.exec_branches 20624810 # Number of branches executed -system.cpu.iew.exec_stores 4917924 # Number of stores executed -system.cpu.iew.exec_rate 0.860528 # Inst execution rate -system.cpu.iew.wb_sent 99710755 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99626115 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59703966 # num instructions producing a value -system.cpu.iew.wb_consumers 95545842 # num instructions consuming a value -system.cpu.iew.wb_rate 0.856216 # insts written-back per cycle +system.cpu.iew.exec_refs 28724643 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624882 # Number of branches executed +system.cpu.iew.exec_stores 4917933 # Number of stores executed +system.cpu.iew.exec_rate 0.860517 # Inst execution rate +system.cpu.iew.wb_sent 99711034 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626392 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59704097 # num instructions producing a value +system.cpu.iew.wb_consumers 95546076 # num instructions consuming a value +system.cpu.iew.wb_rate 0.856206 # insts written-back per cycle system.cpu.iew.wb_fanout 0.624872 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17384633 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17384953 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825600 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 113611791 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.801445 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.737925 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113612998 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737923 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 77186972 67.94% 67.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18613328 16.38% 84.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7152554 6.30% 90.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469014 3.05% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644498 1.45% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541954 0.48% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 704210 0.62% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 178949 0.16% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120312 3.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77188479 67.94% 67.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18612991 16.38% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152574 6.30% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3468909 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1644585 1.45% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 541952 0.48% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 704226 0.62% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178939 0.16% 96.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4120343 3.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 113611791 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113612998 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -670,78 +672,78 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120312 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 217924017 # The number of ROB reads -system.cpu.rob.rob_writes 219569293 # The number of ROB writes -system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 52362 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4120343 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 217925513 # The number of ROB reads +system.cpu.rob.rob_writes 219569964 # The number of ROB writes +system.cpu.timesIdled 581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52792 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.284431 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.284431 # CPI: Total CPI of All Threads -system.cpu.ipc 0.778555 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.778555 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108111974 # number of integer regfile reads -system.cpu.int_regfile_writes 58701043 # number of integer regfile writes +system.cpu.cpi 1.284449 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284449 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778544 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778544 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108112150 # number of integer regfile reads +system.cpu.int_regfile_writes 58701199 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 92 # number of floating regfile writes -system.cpu.cc_regfile_reads 369066936 # number of cc regfile reads -system.cpu.cc_regfile_writes 58693781 # number of cc regfile writes -system.cpu.misc_regfile_reads 28415091 # number of misc regfile reads +system.cpu.fp_regfile_writes 93 # number of floating regfile writes +system.cpu.cc_regfile_reads 369067542 # number of cc regfile reads +system.cpu.cc_regfile_writes 58693892 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415154 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5470182 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.784909 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18253071 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5470694 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.336518 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 5470195 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.784912 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18253010 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470707 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.336499 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 35707500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.784909 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.784912 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999580 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61911082 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61911082 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13891036 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13891036 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4353748 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4353748 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61911209 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61911209 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13890997 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13890997 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4353726 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4353726 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18244784 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18244784 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18245306 # number of overall hits -system.cpu.dcache.overall_hits::total 18245306 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9585874 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9585874 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 381233 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 381233 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18244723 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18244723 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18245245 # number of overall hits +system.cpu.dcache.overall_hits::total 18245245 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9585970 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9585970 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 381255 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 381255 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9967107 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9967107 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9967114 # number of overall misses -system.cpu.dcache.overall_misses::total 9967114 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 88735069500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 88735069500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002231848 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4002231848 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9967225 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9967225 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9967232 # number of overall misses +system.cpu.dcache.overall_misses::total 9967232 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88736242500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88736242500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4002302858 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4002302858 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 296500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 296500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 92737301348 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 92737301348 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 92737301348 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 92737301348 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23476910 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23476910 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 92738545358 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92738545358 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92738545358 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92738545358 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23476967 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23476967 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -750,100 +752,100 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28211891 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28211891 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28212420 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28212420 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408311 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408311 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28211948 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28211948 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28212477 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28212477 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408314 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408314 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080519 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080519 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353295 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353295 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353288 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353288 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.857486 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.857486 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10498.125419 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10498.125419 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353298 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353298 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353292 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353292 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9256.887149 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9256.887149 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10497.705887 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10497.705887 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19766.666667 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19766.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.334884 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9304.334884 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.328349 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9304.328349 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 329976 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 109342 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121408 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12843 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717910 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.513743 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9304.349541 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9304.349541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9304.343007 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9304.343007 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 330007 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 109189 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121421 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12842 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717874 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8.502492 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5470182 # number of writebacks -system.cpu.dcache.writebacks::total 5470182 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337666 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4337666 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158748 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158748 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5470195 # number of writebacks +system.cpu.dcache.writebacks::total 5470195 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4337753 # number of ReadReq MSHR hits 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-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222485 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222485 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4496519 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4496519 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4496519 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4496519 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248217 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248217 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222489 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222489 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5470693 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5470693 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5470697 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5470697 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43256008000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43256008000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285824228 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285824228 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 5470706 # number of demand (read+write) MSHR misses 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-system.cpu.dcache.demand_mshr_miss_latency::total 45541832228 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45542046728 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45542046728 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223548 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223548 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45543210239 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 45543210239 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45543424739 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 45543424739 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223547 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223547 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046988 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193914 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193914 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193915 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193915 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193911 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.193911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.052906 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.052906 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.059950 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.059950 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8242.295526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8242.295526 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10274.012374 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10274.012374 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.691630 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.691630 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.724752 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.724752 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8324.923737 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8324.923737 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8324.956859 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8324.956859 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 452 # number of replacements -system.cpu.icache.tags.tagsinuse 428.759370 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32301211 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 428.759642 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32301343 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 911 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35456.872667 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 35457.017563 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.759370 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 428.759642 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.837421 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.837421 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id @@ -852,208 +854,207 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 52 system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 331 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64605645 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64605645 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32301211 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32301211 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32301211 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32301211 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32301211 # number of overall hits -system.cpu.icache.overall_hits::total 32301211 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1156 # number of overall misses -system.cpu.icache.overall_misses::total 1156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 61324481 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 61324481 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 61324481 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 61324481 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 61324481 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 61324481 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32302367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32302367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32302367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32302367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32302367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32302367 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64605911 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64605911 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32301343 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32301343 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32301343 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32301343 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32301343 # number of overall hits +system.cpu.icache.overall_hits::total 32301343 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1157 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1157 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1157 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1157 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1157 # number of overall misses +system.cpu.icache.overall_misses::total 1157 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61697981 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61697981 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61697981 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61697981 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61697981 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61697981 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32302500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32302500 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32302500 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32302500 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32302500 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32302500 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53048.858997 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53048.858997 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53048.858997 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53048.858997 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53048.858997 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 18977 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53325.826275 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53325.826275 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53325.826275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53325.826275 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53325.826275 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 18986 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 108 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.342222 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 84.382222 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 21.600000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.writebacks::writebacks 452 # number of writebacks system.cpu.icache.writebacks::total 452 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 244 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 244 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 244 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 244 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 244 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 245 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 245 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 245 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 245 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 245 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 245 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 912 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 912 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 912 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 912 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 912 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50084985 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 50084985 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50084985 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 50084985 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50084985 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 50084985 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50324485 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50324485 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50324485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50324485 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50324485 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50324485 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54917.746711 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54917.746711 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54917.746711 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54917.746711 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55180.356360 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55180.356360 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55180.356360 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55180.356360 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4981768 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296904 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 273976 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4981576 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5296807 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 274066 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14074864 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 212 # number of replacements -system.cpu.l2cache.tags.tagsinuse 11227.859430 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5316692 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 14883 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 357.232547 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14075593 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 236 # number of replacements +system.cpu.l2cache.tags.tagsinuse 11228.158132 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5318864 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 14906 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 356.827050 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11063.435293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 164.424136 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.675259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010036 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.685294 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 174 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 14497 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11064.722538 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 163.435594 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.675337 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009975 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.685312 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 176 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 14494 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3710 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9301 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 891 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.010620 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884827 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180497662 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180497662 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 5453533 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 5453533 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 14185 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 14185 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 226016 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 226016 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 211 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 211 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243612 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5243612 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5469628 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5469839 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5469628 # number of overall hits -system.cpu.l2cache.overall_hits::total 5469839 # number of overall hits +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 160 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3697 # Occupied blocks per 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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32684500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32684500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43736000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43736000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 35150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 35150000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43736000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 67834500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 111570500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43736000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 67834500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 851895298 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 963465798 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.767544 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000101 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000287 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.767544 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000160 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001505 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.769737 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000106 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000106 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000292 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.769737 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000164 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058087 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.383003 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16666.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95492.690058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95492.690058 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62135 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62135 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64145.951036 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64145.951036 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70066.433566 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62135 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76426.116838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.383003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3027.820907 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058077 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2694.370534 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95848.973607 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95848.973607 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62301.994302 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62301.994302 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63219.424460 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63219.424460 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69775.171982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62301.994302 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75623.745819 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2694.370534 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3031.911881 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 10942243 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470651 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 10942269 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5470664 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2916 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 303048 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302740 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 303004 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302696 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 308 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 5245086 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5453690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 14185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1285 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318131 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5245095 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5450772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 20045 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1323 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 226523 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 912 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244175 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16408677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16410940 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700030528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700116992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 319578 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5791182 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052888 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.224048 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244184 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2275 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16411619 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16413894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700217984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 700305216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 319547 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5791165 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052881 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.224033 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485204 94.72% 94.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305670 5.28% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485231 94.72% 94.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 305626 5.28% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 308 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5791182 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10941755515 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5791165 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10941781515 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 7525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1367997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1367498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8206046991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 8206066491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) -system.membus.trans_dist::ReadResp 15672 # Transaction distribution -system.membus.trans_dist::WritebackDirty 157 # Transaction distribution -system.membus.trans_dist::CleanEvict 51 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5 # Transaction distribution -system.membus.trans_dist::UpgradeResp 5 # Transaction distribution +system.membus.trans_dist::ReadResp 15694 # Transaction distribution +system.membus.trans_dist::WritebackDirty 170 # Transaction distribution +system.membus.trans_dist::CleanEvict 58 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4 # Transaction distribution system.membus.trans_dist::ReadExReq 340 # Transaction distribution system.membus.trans_dist::ReadExResp 340 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 15673 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32243 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32243 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1034816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1034816 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 15695 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32301 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1037056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1037056 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16226 # Request fanout histogram +system.membus.snoop_fanout::samples 16267 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16226 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16267 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16226 # Request fanout histogram -system.membus.reqLayer0.occupancy 26763807 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16267 # Request fanout histogram +system.membus.reqLayer0.occupancy 26872796 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 83802056 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 83907066 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 5dc111e3a..4cc0ff469 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.361598 # Nu sim_ticks 361597758500 # Number of ticks simulated final_tick 361597758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1135132 # Simulator instruction rate (inst/s) -host_op_rate 1135179 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1683423955 # Simulator tick rate (ticks/s) -host_mem_usage 429008 # Number of bytes of host memory used -host_seconds 214.80 # Real time elapsed on the host +host_inst_rate 1193747 # Simulator instruction rate (inst/s) +host_op_rate 1193796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1770350920 # Simulator tick rate (ticks/s) +host_mem_usage 429888 # Number of bytes of host memory used +host_seconds 204.25 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -473,14 +473,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 935266 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 882 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 892857 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2816405 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2814617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2816406 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58048 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 119989568 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 120047616 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index ddbe14f27..9741f69fb 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.061602 # Nu sim_ticks 61602281500 # Number of ticks simulated final_tick 61602281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 108860 # Simulator instruction rate (inst/s) -host_op_rate 191684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42446103 # Simulator tick rate (ticks/s) -host_mem_usage 458164 # Number of bytes of host memory used -host_seconds 1451.31 # Real time elapsed on the host +host_inst_rate 110070 # Simulator instruction rate (inst/s) +host_op_rate 193816 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42918086 # Simulator tick rate (ticks/s) +host_mem_usage 460124 # Number of bytes of host memory used +host_seconds 1435.35 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 1947008 # To system.physmem.bytesWrittenSys 12160 # Total written bytes from the system interface side system.physmem.servicedByWrQ 86 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 24 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 1928 # Per bank write bursts system.physmem.perBankRdBursts::1 2059 # Per bank write bursts system.physmem.perBankRdBursts::2 2023 # Per bank write bursts @@ -343,15 +343,15 @@ system.cpu.rename.tempSerializingInsts 490 # co system.cpu.rename.skidInsts 66412323 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 105336194 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 36169392 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49402348 # Number of conflicting loads. +system.cpu.memDep0.conflictingLoads 49401722 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 8500449 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 322302018 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1714 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsAdded 322301392 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2340 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 306103027 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 45906 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 44111268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 63884608 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1269 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 63882730 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1895 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 123139703 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.485819 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 2.139102 # Number of insts issued each cycle @@ -467,7 +467,7 @@ system.cpu.iew.iewDispatchedInsts 322303732 # Nu system.cpu.iew.iewDispSquashedInsts 76830 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 105336194 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 36169392 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 475 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 1101 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2588 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 3102623 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 41328 # Number of memory order violations @@ -486,9 +486,9 @@ system.cpu.iew.exec_rate 2.476830 # In system.cpu.iew.wb_sent 304565842 # cumulative count of insts sent to commit system.cpu.iew.wb_count 304282792 # cumulative count of insts written-back system.cpu.iew.wb_producers 230213909 # num instructions producing a value -system.cpu.iew.wb_consumers 333860979 # num instructions consuming a value +system.cpu.iew.wb_consumers 333860423 # num instructions consuming a value system.cpu.iew.wb_rate 2.469736 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689550 # average fanout of values written-back +system.cpu.iew.wb_fanout 0.689551 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 44209690 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 742008 # The number of times a branch was mispredicted @@ -956,7 +956,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 1995354 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2066791 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 53 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5974 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6015 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 82069 # Transaction distribution @@ -964,8 +964,8 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 82069 # T system.cpu.toL2Bus.trans_dist::ReadCleanReq 1014 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1994340 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2081 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225092 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6227173 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6225133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6227214 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68288 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265152640 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 265220928 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 168253993..c6f6cfa54 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.412076 # Nu sim_ticks 412076211500 # Number of ticks simulated final_tick 412076211500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 332870 # Simulator instruction rate (inst/s) -host_op_rate 332870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224166223 # Simulator tick rate (ticks/s) -host_mem_usage 300688 # Number of bytes of host memory used -host_seconds 1838.26 # Real time elapsed on the host +host_inst_rate 319842 # Simulator instruction rate (inst/s) +host_op_rate 319842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215393213 # Simulator tick rate (ticks/s) +host_mem_usage 301832 # Number of bytes of host memory used +host_seconds 1913.13 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 24299648 # To system.physmem.bytesWrittenSys 18790784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 352 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 51706 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 23686 # Per bank write bursts system.physmem.perBankRdBursts::1 23158 # Per bank write bursts system.physmem.perBankRdBursts::2 23442 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 17195 # Pe system.physmem.perBankWrBursts::15 17131 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 412076182000 # Total gap between requests +system.physmem.totGap 412076123500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -256,7 +256,7 @@ system.physmem.readRowHits 314253 # Nu system.physmem.writeRowHits 216307 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate 73.67 # Row buffer hit rate for writes -system.physmem.avgGap 612035.54 # Average gap between requests +system.physmem.avgGap 612035.45 # Average gap between requests system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 548334360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 299190375 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 232b217c8..2d282091b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.363578 # Nu sim_ticks 363578056500 # Number of ticks simulated final_tick 363578056500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237399 # Simulator instruction rate (inst/s) -host_op_rate 257134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 170382928 # Simulator tick rate (ticks/s) -host_mem_usage 321244 # Number of bytes of host memory used -host_seconds 2133.89 # Real time elapsed on the host +host_inst_rate 233007 # Simulator instruction rate (inst/s) +host_op_rate 252377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167231069 # Simulator tick rate (ticks/s) +host_mem_usage 322224 # Number of bytes of host memory used +host_seconds 2174.11 # Real time elapsed on the host sim_insts 506582156 # Number of instructions simulated sim_ops 548695379 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 9212032 # To system.physmem.bytesWrittenSys 6219008 # Total written bytes from the system interface side system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12571 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9337 # Per bank write bursts system.physmem.perBankRdBursts::1 8920 # Per bank write bursts system.physmem.perBankRdBursts::2 8993 # Per bank write bursts @@ -835,18 +835,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2620 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 807247 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1165429 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 17475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 82243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 17711 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 86920 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 19583 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 787664 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56641 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3423464 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3480105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2371712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56877 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3428141 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3485018 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2386816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141589504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 143961216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 143976320 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 112366 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1276028 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.005963 # Request fanout histogram diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 4134d7329..965a91be2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.234001 # Number of seconds simulated -sim_ticks 234001297000 # Number of ticks simulated -final_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233976 # Number of seconds simulated +sim_ticks 233975583000 # Number of ticks simulated +final_tick 233975583000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134504 # Simulator instruction rate (inst/s) -host_op_rate 145716 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62295833 # Simulator tick rate (ticks/s) -host_mem_usage 343376 # Number of bytes of host memory used -host_seconds 3756.29 # Real time elapsed on the host +host_inst_rate 134400 # Simulator instruction rate (inst/s) +host_op_rate 145602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62240486 # Simulator tick rate (ticks/s) +host_mem_usage 347620 # Number of bytes of host memory used +host_seconds 3759.22 # Real time elapsed on the host sim_insts 505237724 # Number of instructions simulated sim_ops 547350945 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory -system.physmem.bytes_read::total 27128576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory -system.physmem.bytes_written::total 18730688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423884 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292667 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423884 # Number of read requests accepted -system.physmem.writeReqs 292667 # Number of write requests accepted -system.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue -system.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26584 # Per bank write bursts -system.physmem.perBankRdBursts::1 25337 # Per bank write bursts -system.physmem.perBankRdBursts::2 25274 # Per bank write bursts -system.physmem.perBankRdBursts::3 32197 # Per bank write bursts -system.physmem.perBankRdBursts::4 27335 # Per bank write bursts -system.physmem.perBankRdBursts::5 28299 # Per bank write bursts -system.physmem.perBankRdBursts::6 25126 # Per bank write bursts -system.physmem.perBankRdBursts::7 24198 # Per bank write bursts -system.physmem.perBankRdBursts::8 25368 # Per bank write bursts -system.physmem.perBankRdBursts::9 25926 # Per bank write bursts -system.physmem.perBankRdBursts::10 25318 # Per bank write bursts -system.physmem.perBankRdBursts::11 26278 # Per bank write bursts -system.physmem.perBankRdBursts::12 27572 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 519680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10101184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16452992 # Number of bytes read from this memory +system.physmem.bytes_read::total 27073856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 519680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 519680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18693440 # Number of bytes written to this memory +system.physmem.bytes_written::total 18693440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257078 # Number of read requests responded to by this memory +system.physmem.num_reads::total 423029 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292085 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292085 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2221086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43171958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70319269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 115712313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2221086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2221086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79894832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79894832 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79894832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2221086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 43171958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70319269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195607146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 423029 # Number of read requests accepted +system.physmem.writeReqs 292085 # Number of write requests accepted +system.physmem.readBursts 423029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292085 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26921664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue +system.physmem.bytesWritten 18690816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27073856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18693440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 26587 # Per bank write bursts +system.physmem.perBankRdBursts::1 25566 # Per bank write bursts +system.physmem.perBankRdBursts::2 25266 # Per bank write bursts +system.physmem.perBankRdBursts::3 32149 # Per bank write bursts +system.physmem.perBankRdBursts::4 27127 # Per bank write bursts +system.physmem.perBankRdBursts::5 28227 # Per bank write bursts +system.physmem.perBankRdBursts::6 25084 # Per bank write bursts +system.physmem.perBankRdBursts::7 24199 # Per bank write bursts +system.physmem.perBankRdBursts::8 25413 # Per bank write bursts +system.physmem.perBankRdBursts::9 25760 # Per bank write bursts +system.physmem.perBankRdBursts::10 25321 # Per bank write bursts +system.physmem.perBankRdBursts::11 26053 # Per bank write bursts +system.physmem.perBankRdBursts::12 27496 # Per bank write bursts system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25056 # Per bank write bursts -system.physmem.perBankRdBursts::15 25713 # Per bank write bursts -system.physmem.perBankWrBursts::0 18662 # Per bank write bursts -system.physmem.perBankWrBursts::1 18231 # Per bank write bursts -system.physmem.perBankWrBursts::2 18003 # Per bank write bursts -system.physmem.perBankWrBursts::3 17875 # Per bank write bursts -system.physmem.perBankWrBursts::4 18721 # Per bank write bursts -system.physmem.perBankWrBursts::5 18310 # Per bank write bursts -system.physmem.perBankWrBursts::6 17836 # Per bank write bursts -system.physmem.perBankWrBursts::7 17744 # Per bank write bursts -system.physmem.perBankWrBursts::8 17983 # Per bank write bursts -system.physmem.perBankWrBursts::9 17940 # Per bank write bursts -system.physmem.perBankWrBursts::10 18239 # Per bank write bursts -system.physmem.perBankWrBursts::11 18938 # Per bank write bursts -system.physmem.perBankWrBursts::12 18976 # Per bank write bursts -system.physmem.perBankWrBursts::13 18211 # Per bank write bursts -system.physmem.perBankWrBursts::14 18390 # Per bank write bursts -system.physmem.perBankWrBursts::15 18579 # Per bank write bursts +system.physmem.perBankRdBursts::14 24848 # Per bank write bursts +system.physmem.perBankRdBursts::15 25683 # Per bank write bursts +system.physmem.perBankWrBursts::0 18549 # Per bank write bursts +system.physmem.perBankWrBursts::1 18359 # Per bank write bursts +system.physmem.perBankWrBursts::2 17952 # Per bank write bursts +system.physmem.perBankWrBursts::3 17851 # Per bank write bursts +system.physmem.perBankWrBursts::4 18559 # Per bank write bursts +system.physmem.perBankWrBursts::5 18328 # Per bank write bursts +system.physmem.perBankWrBursts::6 17864 # Per bank write bursts +system.physmem.perBankWrBursts::7 17725 # Per bank write bursts +system.physmem.perBankWrBursts::8 17897 # Per bank write bursts +system.physmem.perBankWrBursts::9 17869 # Per bank write bursts +system.physmem.perBankWrBursts::10 18218 # Per bank write bursts +system.physmem.perBankWrBursts::11 18760 # Per bank write bursts +system.physmem.perBankWrBursts::12 18894 # Per bank write bursts +system.physmem.perBankWrBursts::13 18283 # Per bank write bursts +system.physmem.perBankWrBursts::14 18348 # Per bank write bursts +system.physmem.perBankWrBursts::15 18588 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 234001244500 # Total gap between requests +system.physmem.totGap 233975530500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423884 # Read request sizes (log2) +system.physmem.readPktSize::6 423029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292667 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292085 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 323238 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 49503 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,35 +148,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 7196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18832 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19060 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -197,112 +197,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 321539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 141.852976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 99.721857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 179.991773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 202400 62.95% 62.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79393 24.69% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15074 4.69% 92.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7330 2.28% 94.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4928 1.53% 96.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2561 0.80% 96.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1887 0.59% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1542 0.48% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6424 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 321539 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17050 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.666979 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 143.647395 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17048 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17050 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17050 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.128680 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.068427 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.524733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 9277 54.41% 54.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 307 1.80% 56.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5331 31.27% 87.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1349 7.91% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 375 2.20% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 167 0.98% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 95 0.56% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 68 0.40% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 36 0.21% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 9 0.05% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads -system.physmem.totQLat 8693371575 # Total ticks spent queuing -system.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::42 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17050 # Writes before turning the bus around for reads +system.physmem.totQLat 8699002486 # Total ticks spent queuing +system.physmem.totMemAccLat 16586208736 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2103255000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20679.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39429.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 115.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.88 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 115.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.89 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.53 # Data bus utilization in percentage +system.physmem.busUtil 1.52 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing -system.physmem.readRowHits 306420 # Number of row buffer hits during reads -system.physmem.writeRowHits 85606 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes -system.physmem.avgGap 326566.07 # Average gap between requests -system.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) -system.physmem_0.averagePower 727.632069 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states -system.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states +system.physmem.avgWrQLen 21.61 # Average write queue length when enqueuing +system.physmem.readRowHits 305767 # Number of row buffer hits during reads +system.physmem.writeRowHits 85381 # Number of row buffer hits during writes +system.physmem.readRowHitRate 72.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 29.23 # Row buffer hit rate for writes +system.physmem.avgGap 327186.34 # Average gap between requests +system.physmem.pageHitRate 54.88 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1223691840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 667689000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1670487000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 940811760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 82095857685 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 68367661500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 170247918225 # Total energy per rank (pJ) +system.physmem_0.averagePower 727.650714 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 113204918849 # Time in different power states +system.physmem_0.memoryStateTime::REF 7812740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states +system.physmem_0.memoryStateTime::ACT 112953795651 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) -system.physmem_1.averagePower 726.230337 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states -system.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states +system.physmem_1.actEnergy 1207044720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 658605750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1610044800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 951633360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79725813930 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 70446639000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 169881501000 # Total energy per rank (pJ) +system.physmem_1.averagePower 726.084666 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 116677189668 # Time in different power states +system.physmem_1.memoryStateTime::REF 7812740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states +system.physmem_1.memoryStateTime::ACT 109482083332 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175128597 # Number of BP lookups -system.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83893856 # Number of BTB hits +system.cpu.branchPred.lookups 175127231 # Number of BP lookups +system.cpu.branchPred.condPredicted 131371482 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7444734 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90531038 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83892410 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.667014 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12111505 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -421,94 +421,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 468002595 # number of cpu cycles simulated +system.cpu.numCycles 467951167 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7807571 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731933483 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175127231 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 96003915 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 452021991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942209 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11591 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236759344 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34037 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 467317920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.696233 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.181442 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95319924 20.40% 20.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132721002 28.40% 48.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57871857 12.38% 61.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181405137 38.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 286955454 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276569326 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 467317920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.374243 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.564124 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32360208 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 118941905 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 286956233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22076930 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982644 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24050421 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715840292 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30013840 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982644 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63442941 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 55755110 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40375220 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276571280 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24190725 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686624983 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13341882 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9442632 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2386991 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1673870 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1900758 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831052151 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019309313 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723953553 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176928400 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535125 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42420493 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143531079 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67984063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12865529 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11219958 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668189770 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978336 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610255971 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5862329 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 123817161 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319322709 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 704 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 467317920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.305869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.102065 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 150163836 32.13% 32.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101159501 21.65% 53.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145796763 31.20% 84.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63288828 13.54% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6908500 1.48% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 492 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 467317920 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71905236 52.96% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available @@ -537,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44555950 32.82% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19306846 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151233 67.70% 67.70% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued @@ -571,82 +571,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134217204 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62535736 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610253474 # Type of FU issued -system.cpu.iq.rate 1.303953 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610255971 # Type of FU issued +system.cpu.iq.rate 1.304102 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135768062 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222477 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1829459960 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 795013485 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984726 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746023856 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7274448 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27646323 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25541 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28976 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11123586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225332 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22431 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982644 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 22928683 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 924923 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672655804 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143531079 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67984063 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489794 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 258689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 530260 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28976 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731718 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554534 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400071 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129576716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10855900 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1487469 # number of nop insts executed -system.cpu.iew.exec_refs 190532110 # number of memory reference insts executed -system.cpu.iew.exec_branches 131373386 # Number of branches executed -system.cpu.iew.exec_stores 60956801 # Number of stores executed -system.cpu.iew.exec_rate 1.280758 # Inst execution rate -system.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594983958 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349895185 # num instructions producing a value -system.cpu.iew.wb_consumers 570621697 # num instructions consuming a value -system.cpu.iew.wb_rate 1.271326 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1487698 # number of nop insts executed +system.cpu.iew.exec_refs 190533409 # number of memory reference insts executed +system.cpu.iew.exec_branches 131373584 # Number of branches executed +system.cpu.iew.exec_stores 60956693 # Number of stores executed +system.cpu.iew.exec_rate 1.280903 # Inst execution rate +system.cpu.iew.wb_sent 596279806 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984742 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349898988 # num instructions producing a value +system.cpu.iew.wb_consumers 570632014 # num instructions consuming a value +system.cpu.iew.wb_rate 1.271468 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613178 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 110042423 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956274 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 450200687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.218778 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.886375 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 221166453 49.13% 49.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116327626 25.84% 74.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43750418 9.72% 84.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23323090 5.18% 89.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11527236 2.56% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7779283 1.73% 94.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8247237 1.83% 95.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4226436 0.94% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13852908 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 450200687 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581608 # Number of instructions committed system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -692,78 +692,78 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction -system.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1095134181 # The number of ROB reads -system.cpu.rob.rob_writes 1334612111 # The number of ROB writes -system.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13852908 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095077893 # The number of ROB reads +system.cpu.rob.rob_writes 1334621527 # The number of ROB writes +system.cpu.timesIdled 12496 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 633247 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237724 # Number of Instructions Simulated system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.926302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads -system.cpu.ipc 1.079562 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611088799 # number of integer regfile reads -system.cpu.int_regfile_writes 328120173 # number of integer regfile writes +system.cpu.cpi 0.926200 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.926200 # CPI: Total CPI of All Threads +system.cpu.ipc 1.079680 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.079680 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089761 # number of integer regfile reads +system.cpu.int_regfile_writes 328120494 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads -system.cpu.cc_regfile_writes 376542810 # number of cc regfile writes -system.cpu.misc_regfile_reads 217972310 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170189724 # number of cc regfile reads +system.cpu.cc_regfile_writes 376542500 # number of cc regfile writes +system.cpu.misc_regfile_reads 217973496 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2820726 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2820720 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.629803 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169353985 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821232 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.028379 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.629803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 356246516 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356246516 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114648880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114648880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51725160 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51725160 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits -system.cpu.dcache.overall_hits::total 166375784 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 166374040 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166374040 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166376823 # number of overall hits +system.cpu.dcache.overall_hits::total 166376823 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4844495 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4844495 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2514146 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2514146 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses -system.cpu.dcache.overall_misses::total 7359142 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 7358641 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7358641 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7358653 # number of overall misses +system.cpu.dcache.overall_misses::total 7358653 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57544876000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57544876000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18904875439 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18904875439 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 76449751439 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 76449751439 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 76449751439 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 76449751439 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119493375 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119493375 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) @@ -772,72 +772,72 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173732681 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173732681 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173735476 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173735476 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040542 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040542 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046353 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.042356 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042356 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042356 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042356 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11878.405489 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11878.405489 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7519.402389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7519.402389 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10389.112805 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10389.112805 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10389.095863 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10389.095863 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 904831 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 221213 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.090316 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks -system.cpu.dcache.writebacks::total 2820726 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits 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(read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4537391 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537391 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537391 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537391 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301669 # number of ReadReq MSHR misses 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miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2821250 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821250 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821260 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821260 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29551116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29551116000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4600493494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4600493494 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 704500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 704500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34151609494 # number of demand (read+write) MSHR miss cycles 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-system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473597840 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473597840 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236680067 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236680067 # number of ReadReq hits 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latency -system.cpu.icache.overall_avg_miss_latency::total 16154.674854 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 160057 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 121 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6454 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 24.799659 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 24.200000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473592523 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473592523 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236677467 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236677467 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 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# number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1323960223 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1323960223 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1323960223 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236759246 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236759246 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236759246 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236759246 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236759246 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236759246 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000345 # miss rate for ReadReq accesses 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latency +system.cpu.icache.blocked_cycles::no_mshrs 155623 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6523 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 23.857581 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 73505 # number of writebacks -system.cpu.icache.writebacks::total 73505 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7785 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7785 # number of ReadReq MSHR hits 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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76637.208028 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1085,159 +1087,158 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292667 # number of writebacks -system.cpu.l2cache.writebacks::total 292667 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1428 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1428 # number of ReadExReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 292085 # number of writebacks +system.cpu.l2cache.writebacks::total 292085 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1398 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1398 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4193 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4193 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4146 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4146 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # 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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30402176863 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 5544 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5551 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 351023 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 351023 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3657 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3657 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8121 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8121 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154177 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8121 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 157834 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 165955 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8121 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 157834 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 351023 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 516978 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18646833753 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 389000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 389000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 334746500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 334746500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 540727000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 540727000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10842464500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10842464500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 540727000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11177211000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11717938000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 540727000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11177211000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30364771753 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109740 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067055 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.057320 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.178562 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53121.401598 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14407.407407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14407.407407 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91535.821712 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91535.821712 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66583.795099 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66583.795099 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70324.785798 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70324.785798 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70609.128981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58735.133319 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 5789505 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894253 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23731 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 260682 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16011 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 2373290 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2650619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 535678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 265254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 392218 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 950663 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 521973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521973 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 74033 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299259 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221525 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8463241 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8684766 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9439488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361084992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370524480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 949589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3844850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.078147 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283493 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3560398 92.60% 92.60% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 268441 6.98% 99.58% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 16011 0.42% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3844850 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788964505 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 111128336 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4231881960 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadResp 420198 # Transaction distribution -system.membus.trans_dist::WritebackDirty 292667 # Transaction distribution -system.membus.trans_dist::CleanEvict 98618 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33 # Transaction distribution -system.membus.trans_dist::ReadExReq 3685 # Transaction distribution -system.membus.trans_dist::ReadExResp 3685 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 419375 # Transaction distribution +system.membus.trans_dist::WritebackDirty 292085 # Transaction distribution +system.membus.trans_dist::CleanEvict 98517 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31 # Transaction distribution +system.membus.trans_dist::ReadExReq 3653 # Transaction distribution +system.membus.trans_dist::ReadExResp 3653 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 419376 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1236690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1236690 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45767232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45767232 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 815202 # Request fanout histogram +system.membus.snoop_fanout::samples 813662 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 813662 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 815202 # Request fanout histogram -system.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 813662 # Request fanout histogram +system.membus.reqLayer0.occupancy 2208946039 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2237977923 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index d23424e24..d35883c7b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.708526 # Nu sim_ticks 708526400500 # Number of ticks simulated final_tick 708526400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 974268 # Simulator instruction rate (inst/s) -host_op_rate 1055088 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1366955379 # Simulator tick rate (ticks/s) -host_mem_usage 319428 # Number of bytes of host memory used -host_seconds 518.32 # Real time elapsed on the host +host_inst_rate 942956 # Simulator instruction rate (inst/s) +host_op_rate 1021179 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1323022561 # Simulator tick rate (ticks/s) +host_mem_usage 320452 # Number of bytes of host memory used +host_seconds 535.54 # Real time elapsed on the host sim_insts 504986854 # Number of instructions simulated sim_ops 546878105 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -608,18 +608,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2145 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1161008 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 80784 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 9788 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 84208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 782658 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32793 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3409234 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3442027 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1361408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3412658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3445488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142391552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142393920 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 110394 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1260833 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.004489 # Request fanout histogram diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1285bd093..b098baae5 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.403750 # Number of seconds simulated -sim_ticks 403750101500 # Number of ticks simulated -final_tick 403750101500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.403427 # Number of seconds simulated +sim_ticks 403427114500 # Number of ticks simulated +final_tick 403427114500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79008 # Simulator instruction rate (inst/s) -host_op_rate 146095 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38578288 # Simulator tick rate (ticks/s) -host_mem_usage 372460 # Number of bytes of host memory used -host_seconds 10465.73 # Real time elapsed on the host +host_inst_rate 97075 # Simulator instruction rate (inst/s) +host_op_rate 179503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47362243 # Simulator tick rate (ticks/s) +host_mem_usage 432836 # Number of bytes of host memory used +host_seconds 8517.91 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24546112 # Number of bytes read from this memory -system.physmem.bytes_read::total 24709696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18890432 # Number of bytes written to this memory -system.physmem.bytes_written::total 18890432 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295163 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295163 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 405162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 60795309 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 61200470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 405162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 405162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 46787436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 46787436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 46787436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 405162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 60795309 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 107987906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386089 # Number of read requests accepted -system.physmem.writeReqs 295163 # Number of write requests accepted -system.physmem.readBursts 386089 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24690880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18816 # Total number of bytes read from write queue -system.physmem.bytesWritten 18889216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24709696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18890432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 294 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 163328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24540032 # Number of bytes read from this memory +system.physmem.bytes_read::total 24703360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 163328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 163328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory +system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2552 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385990 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 404851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 60828911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 61233762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 404851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 404851 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 46816645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 46816645 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 46816645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 404851 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 60828911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 108050407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385990 # Number of read requests accepted +system.physmem.writeReqs 295111 # Number of write requests accepted +system.physmem.readBursts 385990 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24683712 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue +system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24703360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 250150 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24088 # Per bank write bursts -system.physmem.perBankRdBursts::1 26446 # Per bank write bursts -system.physmem.perBankRdBursts::2 24837 # Per bank write bursts -system.physmem.perBankRdBursts::3 24496 # Per bank write bursts -system.physmem.perBankRdBursts::4 23228 # Per bank write bursts -system.physmem.perBankRdBursts::5 23719 # Per bank write bursts -system.physmem.perBankRdBursts::6 24505 # Per bank write bursts -system.physmem.perBankRdBursts::7 24301 # Per bank write bursts -system.physmem.perBankRdBursts::8 23634 # Per bank write bursts -system.physmem.perBankRdBursts::9 23532 # Per bank write bursts -system.physmem.perBankRdBursts::10 24794 # Per bank write bursts -system.physmem.perBankRdBursts::11 23986 # Per bank write bursts -system.physmem.perBankRdBursts::12 23318 # Per bank write bursts -system.physmem.perBankRdBursts::13 22932 # Per bank write bursts -system.physmem.perBankRdBursts::14 24086 # Per bank write bursts -system.physmem.perBankRdBursts::15 23893 # Per bank write bursts -system.physmem.perBankWrBursts::0 18617 # Per bank write bursts -system.physmem.perBankWrBursts::1 19942 # Per bank write bursts -system.physmem.perBankWrBursts::2 19199 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24081 # Per bank write bursts +system.physmem.perBankRdBursts::1 26417 # Per bank write bursts +system.physmem.perBankRdBursts::2 24826 # Per bank write bursts +system.physmem.perBankRdBursts::3 24490 # Per bank write bursts +system.physmem.perBankRdBursts::4 23233 # Per bank write bursts +system.physmem.perBankRdBursts::5 23715 # Per bank write bursts +system.physmem.perBankRdBursts::6 24493 # Per bank write bursts +system.physmem.perBankRdBursts::7 24296 # Per bank write bursts +system.physmem.perBankRdBursts::8 23625 # Per bank write bursts +system.physmem.perBankRdBursts::9 23520 # Per bank write bursts +system.physmem.perBankRdBursts::10 24786 # Per bank write bursts +system.physmem.perBankRdBursts::11 23961 # Per bank write bursts +system.physmem.perBankRdBursts::12 23329 # Per bank write bursts +system.physmem.perBankRdBursts::13 22937 # Per bank write bursts +system.physmem.perBankRdBursts::14 24074 # Per bank write bursts +system.physmem.perBankRdBursts::15 23900 # Per bank write bursts +system.physmem.perBankWrBursts::0 18616 # Per bank write bursts +system.physmem.perBankWrBursts::1 19936 # Per bank write bursts +system.physmem.perBankWrBursts::2 19195 # Per bank write bursts system.physmem.perBankWrBursts::3 19026 # Per bank write bursts -system.physmem.perBankWrBursts::4 18119 # Per bank write bursts -system.physmem.perBankWrBursts::5 18516 # Per bank write bursts -system.physmem.perBankWrBursts::6 19139 # Per bank write bursts +system.physmem.perBankWrBursts::4 18116 # Per bank write bursts +system.physmem.perBankWrBursts::5 18513 # Per bank write bursts +system.physmem.perBankWrBursts::6 19137 # Per bank write bursts system.physmem.perBankWrBursts::7 19093 # Per bank write bursts -system.physmem.perBankWrBursts::8 18647 # Per bank write bursts -system.physmem.perBankWrBursts::9 17956 # Per bank write bursts -system.physmem.perBankWrBursts::10 18916 # Per bank write bursts -system.physmem.perBankWrBursts::11 17762 # Per bank write bursts -system.physmem.perBankWrBursts::12 17409 # Per bank write bursts -system.physmem.perBankWrBursts::13 17014 # Per bank write bursts -system.physmem.perBankWrBursts::14 17906 # Per bank write bursts -system.physmem.perBankWrBursts::15 17883 # Per bank write bursts +system.physmem.perBankWrBursts::8 18645 # Per bank write bursts +system.physmem.perBankWrBursts::9 17955 # Per bank write bursts +system.physmem.perBankWrBursts::10 18907 # Per bank write bursts +system.physmem.perBankWrBursts::11 17752 # Per bank write bursts +system.physmem.perBankWrBursts::12 17408 # Per bank write bursts +system.physmem.perBankWrBursts::13 17006 # Per bank write bursts +system.physmem.perBankWrBursts::14 17895 # Per bank write bursts +system.physmem.perBankWrBursts::15 17879 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 403750059500 # Total gap between requests +system.physmem.totGap 403427072500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386089 # Read request sizes (log2) +system.physmem.readPktSize::6 385990 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4562 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295111 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 308 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17662 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 17655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17770 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see @@ -193,43 +193,43 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146856 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.750885 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.556415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.540822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54126 36.86% 36.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 39800 27.10% 63.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13820 9.41% 73.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7615 5.19% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5593 3.81% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4060 2.76% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2963 2.02% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2671 1.82% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16208 11.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146856 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.039017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 217.962707 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17495 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 296.528440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.268112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 322.869611 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54238 36.92% 36.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39906 27.16% 64.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13861 9.43% 73.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7527 5.12% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5392 3.67% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3977 2.71% 85.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3022 2.06% 87.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2802 1.91% 88.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16198 11.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146923 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17507 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.029360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 217.887118 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17497 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17505 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17505 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.860554 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.781765 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.832914 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17316 98.92% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 135 0.77% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 27 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17507 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17507 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.854915 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.776896 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.816664 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17316 98.91% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 131 0.75% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 0.19% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 8 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads @@ -238,202 +238,202 @@ system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Wr system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17505 # Writes before turning the bus around for reads -system.physmem.totQLat 4284897750 # Total ticks spent queuing -system.physmem.totMemAccLat 11518554000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1928975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11106.67 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17507 # Writes before turning the bus around for reads +system.physmem.totQLat 4287997000 # Total ticks spent queuing +system.physmem.totMemAccLat 11519553250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1928415000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11117.93 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29856.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 61.15 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 46.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 61.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 46.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29867.93 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 61.19 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 46.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 46.82 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.84 # Data bus utilization in percentage system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.88 # Average write queue length when enqueuing -system.physmem.readRowHits 318212 # Number of row buffer hits during reads -system.physmem.writeRowHits 215865 # Number of row buffer hits during writes +system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing +system.physmem.readRowHits 318108 # Number of row buffer hits during reads +system.physmem.writeRowHits 215717 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.13 # Row buffer hit rate for writes -system.physmem.avgGap 592658.90 # Average gap between requests -system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 568406160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310142250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1525828200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 982679040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 62107024725 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 187769234250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 279634184865 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.595037 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 311821526250 # Time in different power states -system.physmem_0.memoryStateTime::REF 13482040000 # Time in different power states +system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes +system.physmem.avgGap 592316.08 # Average gap between requests +system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 568655640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 310278375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1525157400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 982374480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62248054410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 187449302250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 279433333275 # Total energy per rank (pJ) +system.physmem_0.averagePower 692.658624 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 311288113000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13471120000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 78445652750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78663487000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 541726920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 295585125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1483162200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 929646720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26370870240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60264291960 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 189385666500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 279270949665 # Total energy per rank (pJ) -system.physmem_1.averagePower 691.695380 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 314524575500 # Time in different power states -system.physmem_1.memoryStateTime::REF 13482040000 # Time in different power states +system.physmem_1.actEnergy 541689120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 295564500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1482585000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 929322720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26349510720 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 60147053505 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 189292285500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 279038011065 # Total energy per rank (pJ) +system.physmem_1.averagePower 691.678700 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 314369366250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13471120000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75741865750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 75582067750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 219275491 # Number of BP lookups -system.cpu.branchPred.condPredicted 219275491 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 8530842 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 123996876 # Number of BTB lookups -system.cpu.branchPred.BTBHits 121809369 # Number of BTB hits +system.cpu.branchPred.lookups 219277494 # Number of BP lookups +system.cpu.branchPred.condPredicted 219277494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8530091 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 124020025 # Number of BTB lookups +system.cpu.branchPred.BTBHits 121811454 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.235837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 27061771 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1406477 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.219182 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 27064699 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1406143 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 807500204 # number of cpu cycles simulated +system.cpu.numCycles 806854230 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 175896513 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1208663738 # Number of instructions fetch has processed -system.cpu.fetch.Branches 219275491 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 148871140 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 621734900 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 17770351 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 92919 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 734617 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1497 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 170765697 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2319587 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.icacheStallCycles 175890438 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1208681477 # Number of instructions fetch has processed +system.cpu.fetch.Branches 219277494 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 148876153 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621110348 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17764353 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 91101 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 722324 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1300 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 170768195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2322348 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 807345886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.785599 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.367664 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 806697934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.787860 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.367990 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 417315550 51.69% 51.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 32556197 4.03% 55.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31914797 3.95% 59.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 32648264 4.04% 63.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 26601298 3.29% 67.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 26865092 3.33% 70.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 35140610 4.35% 74.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 31395380 3.89% 78.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 172908698 21.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 416692027 51.65% 51.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 32514924 4.03% 55.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31852485 3.95% 59.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32737208 4.06% 63.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 26535487 3.29% 66.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 26940530 3.34% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 35175393 4.36% 74.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 31366288 3.89% 78.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 172883592 21.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 807345886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.271549 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.496797 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 120455538 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 370723147 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 225174137 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82107889 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 8885175 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2132090689 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 8885175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 152508786 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 150703188 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 44276 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 271505228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 223699233 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2088450374 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 134027 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 138145056 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24847890 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 50675847 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2190623948 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5277971052 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3356955770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 59583 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 806697934 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.271768 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.498017 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 120436174 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 370050155 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 225346926 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 81982503 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 8882176 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2132175908 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 8882176 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 152549485 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 150499256 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 41235 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 271495233 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 223230549 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2088541699 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 133771 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 138231059 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24777266 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 50120464 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2190713921 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5278163786 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3357090809 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 59859 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 576583094 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 3244 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 3058 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 422095496 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 507123971 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 200816092 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 229029695 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68201156 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2023089277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22810 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1789046992 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 413186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 494123386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 832685562 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 22258 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 807345886 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.215961 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.071124 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 576673067 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3285 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3078 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 422612041 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 507148674 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 200824572 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 228968697 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68242516 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2023165492 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27791 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1789027795 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 414599 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 494204582 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 832990276 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 27239 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 806697934 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.217717 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.070743 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 238839063 29.58% 29.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 123555302 15.30% 44.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 118726852 14.71% 59.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 107721401 13.34% 72.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 89742056 11.12% 84.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 60203262 7.46% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 42304747 5.24% 96.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18964857 2.35% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7288346 0.90% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 238149356 29.52% 29.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 123576451 15.32% 44.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 118711028 14.72% 59.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 107747587 13.36% 72.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 89829016 11.14% 84.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 60156883 7.46% 91.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 42289548 5.24% 96.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18955760 2.35% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7282305 0.90% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 807345886 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 806697934 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11498108 42.65% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12352662 45.82% 88.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3109525 11.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11505863 42.68% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12343295 45.78% 88.46% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3110421 11.54% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2715586 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1183095329 66.13% 66.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 369789 0.02% 66.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881135 0.22% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 131 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2715990 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1183116627 66.13% 66.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 369664 0.02% 66.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881147 0.22% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 118 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 62 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 375 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 58 0.00% 66.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 380 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued @@ -455,82 +455,82 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 428554849 23.95% 90.47% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170429736 9.53% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 428537576 23.95% 90.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170406235 9.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1789046992 # Type of FU issued -system.cpu.iq.rate 2.215538 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26960295 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.015070 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4412783736 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2517485001 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1762397634 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 29615 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 68960 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 5614 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1813278705 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12996 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 186120882 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1789027795 # Type of FU issued +system.cpu.iq.rate 2.217287 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26959579 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.015069 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4412098039 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2517646847 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1762392188 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 29663 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 69110 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 5652 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1813258358 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 13026 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185949248 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 123024315 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213288 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 372216 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 51655906 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 123048931 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 213773 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 371791 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 51664386 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 23026 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 23126 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1127 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 8885175 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 97857746 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6188485 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2023112087 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 370282 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 507126472 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 200816092 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7124 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1833420 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3447634 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 372216 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4845141 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4138975 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8984116 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1770027933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 423156069 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19019059 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 8882176 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 97661574 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6126306 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2023193283 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 371095 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 507151088 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 200824572 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12039 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1828108 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3395741 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 371791 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4845230 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4136012 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8981242 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1770011750 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 423132476 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19016045 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590393535 # number of memory reference insts executed -system.cpu.iew.exec_branches 168976878 # Number of branches executed -system.cpu.iew.exec_stores 167237466 # Number of stores executed -system.cpu.iew.exec_rate 2.191985 # Inst execution rate -system.cpu.iew.wb_sent 1766902573 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1762403248 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1339734836 # num instructions producing a value -system.cpu.iew.wb_consumers 2050019870 # num instructions consuming a value -system.cpu.iew.wb_rate 2.182542 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.653523 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 494186003 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 590347878 # number of memory reference insts executed +system.cpu.iew.exec_branches 168976982 # Number of branches executed +system.cpu.iew.exec_stores 167215402 # Number of stores executed +system.cpu.iew.exec_rate 2.193719 # Inst execution rate +system.cpu.iew.wb_sent 1766881473 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1762397840 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1339889750 # num instructions producing a value +system.cpu.iew.wb_consumers 2050179516 # num instructions consuming a value +system.cpu.iew.wb_rate 2.184283 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.653548 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 494265381 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8613223 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 740134628 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.065825 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.576078 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 8610728 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 739482483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.067647 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.576172 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 276181742 37.32% 37.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 172028130 23.24% 60.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 55891908 7.55% 68.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86294140 11.66% 79.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 25858762 3.49% 83.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26505188 3.58% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9830635 1.33% 88.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9003447 1.22% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78540676 10.61% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 275479046 37.25% 37.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172073402 23.27% 60.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 55823940 7.55% 68.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86367064 11.68% 79.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 25894199 3.50% 83.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26482728 3.58% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9848964 1.33% 88.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9023113 1.22% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 78490027 10.61% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 740134628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 739482483 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -576,350 +576,350 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 78540676 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 2684768656 # The number of ROB reads -system.cpu.rob.rob_writes 4113734804 # The number of ROB writes -system.cpu.timesIdled 1976 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 154318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 78490027 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 2684246538 # The number of ROB reads +system.cpu.rob.rob_writes 4113897788 # The number of ROB writes +system.cpu.timesIdled 1953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 156296 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.976566 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.976566 # CPI: Total CPI of All Threads -system.cpu.ipc 1.023996 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.023996 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2722734844 # number of integer regfile reads -system.cpu.int_regfile_writes 1435842493 # number of integer regfile writes -system.cpu.fp_regfile_reads 5827 # number of floating regfile reads -system.cpu.fp_regfile_writes 544 # number of floating regfile writes -system.cpu.cc_regfile_reads 596643147 # number of cc regfile reads -system.cpu.cc_regfile_writes 405466657 # number of cc regfile writes -system.cpu.misc_regfile_reads 971667313 # number of misc regfile reads +system.cpu.cpi 0.975785 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.975785 # CPI: Total CPI of All Threads +system.cpu.ipc 1.024816 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.024816 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2722631435 # number of integer regfile reads +system.cpu.int_regfile_writes 1435841734 # number of integer regfile writes +system.cpu.fp_regfile_reads 5845 # number of floating regfile reads +system.cpu.fp_regfile_writes 533 # number of floating regfile writes +system.cpu.cc_regfile_reads 596631944 # number of cc regfile reads +system.cpu.cc_regfile_writes 405465564 # number of cc regfile writes +system.cpu.misc_regfile_reads 971632310 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2531012 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.814248 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 381842819 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2535108 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.621914 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2530979 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.807694 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 381987598 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2535075 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.680985 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.814248 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998002 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998002 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.807694 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998000 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998000 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 871 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 866 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3174 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 772778472 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 772778472 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 233189012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 233189012 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148175395 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148175395 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 381364407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 381364407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 381364407 # number of overall hits -system.cpu.dcache.overall_hits::total 381364407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2772468 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2772468 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 984807 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 984807 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3757275 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3757275 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3757275 # number of overall misses -system.cpu.dcache.overall_misses::total 3757275 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 59137035000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 59137035000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31243406496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31243406496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90380441496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90380441496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90380441496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90380441496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 235961480 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 235961480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 773071261 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 773071261 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 233342532 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 233342532 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148176085 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148176085 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 381518617 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 381518617 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 381518617 # number of overall hits +system.cpu.dcache.overall_hits::total 381518617 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2765359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2765359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 984117 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 984117 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3749476 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3749476 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3749476 # number of overall misses +system.cpu.dcache.overall_misses::total 3749476 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 58561335000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 58561335000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30709347495 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30709347495 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89270682495 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89270682495 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89270682495 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89270682495 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 236107891 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 236107891 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 385121682 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 385121682 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 385121682 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 385121682 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011750 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006602 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006602 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009756 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009756 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009756 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009756 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21330.105523 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21330.105523 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31725.410660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31725.410660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24054.784783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24054.784783 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24054.784783 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9718 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 22 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1069 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 385268093 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 385268093 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 385268093 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 385268093 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011712 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011712 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006598 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006598 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009732 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009732 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009732 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009732 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21176.756797 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21176.756797 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31204.976131 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31204.976131 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23808.842221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23808.842221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23808.842221 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9995 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1075 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.090739 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 11 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.297674 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2330580 # number of writebacks -system.cpu.dcache.writebacks::total 2330580 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1007465 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1007465 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19412 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 19412 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1026877 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1026877 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1026877 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1026877 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765003 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1765003 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 965395 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 965395 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2730398 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2730398 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2730398 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2730398 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33567375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33567375500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 30021732998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 30021732998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63589108498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 63589108498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63589108498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 63589108498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007480 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006472 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19018.310734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19018.310734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31097.874961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31097.874961 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23289.318443 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23289.318443 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2330614 # number of writebacks +system.cpu.dcache.writebacks::total 2330614 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1000418 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1000418 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19400 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 19400 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1019818 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1019818 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1019818 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1019818 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764941 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764941 # number of ReadReq MSHR misses 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references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.831951 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506754 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506754 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1611 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1037.931814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506803 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1153 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.786621 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 341735047 # Number of tag accesses -system.cpu.icache.tags.data_accesses 341735047 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 170559843 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 170559843 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 170559843 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 170559843 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 170559843 # number of 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-system.cpu.icache.overall_miss_latency::cpu.inst 1200128500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1200128500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 170765696 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 170765696 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 170765696 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 170765696 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 170765696 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 170765696 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001205 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001205 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001205 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001205 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001205 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001205 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5830.026767 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 5830.026767 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 5830.026767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 5830.026767 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 5830.026767 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1227 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 316 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1161 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341739287 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341739287 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 170563080 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 170563080 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 170563080 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 170563080 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 170563080 # number of overall hits +system.cpu.icache.overall_hits::total 170563080 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 205114 # number of ReadReq misses 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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -928,143 +928,142 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 295163 # number of writebacks -system.cpu.l2cache.writebacks::total 295163 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks +system.cpu.l2cache.writebacks::total 295111 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 8 # number of CleanEvict MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 193439 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206924 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206924 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176660 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383584 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383584 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386141 # number of overall MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 4268097007 # number of UpgradeReq MSHR miss cycles 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cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26960077000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182391500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26777685500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26960077000 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 192758 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 192758 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206906 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 206906 # number of ReadExReq MSHR misses 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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26772805041 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26956970541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184165500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26772805041 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26956970541 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990522 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990522 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268556 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268556 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.310353 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100113 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100113 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.310353 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151309 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22064.304546 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22064.304546 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69331.310046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69331.310046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71330.269847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71330.269847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70368.920525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70368.920525 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71330.269847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69809.182604 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69819.255143 # average overall mshr miss latency +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990621 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990621 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268525 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.311646 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100070 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100070 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151788 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.311646 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151788 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19293.191427 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19293.191427 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69330.398828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69330.398828 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72136.897767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72136.897767 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70381.696244 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70381.696244 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72136.897767 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69814.477857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69829.836806 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5471713 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729811 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 210473 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3600 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3600 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5470136 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2729158 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 209637 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3579 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3579 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 1968256 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2625743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6244 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 249948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 195290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 195290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 770507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 770507 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 203657 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764601 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 218138 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7981134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8199272 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 926784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312330816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 550771 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3289408 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.123462 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.328967 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadResp 1967447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2625725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 260490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 194583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 194583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 770527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 770527 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 202901 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764548 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7990295 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8207984 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 946432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311404096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312350528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 549945 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3287795 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.123088 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.328538 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2883292 87.65% 87.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 406116 12.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2883107 87.69% 87.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 404688 12.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3289408 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5101560430 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3287795 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5100517412 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 305490983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304355486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3900309572 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3899906073 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 179215 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295163 # Transaction distribution -system.membus.trans_dist::CleanEvict 56660 # Transaction distribution -system.membus.trans_dist::UpgradeReq 193490 # Transaction distribution -system.membus.trans_dist::UpgradeResp 193490 # Transaction distribution -system.membus.trans_dist::ReadExReq 206873 # Transaction distribution -system.membus.trans_dist::ReadExResp 206873 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 179216 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1510980 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43600064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43600064 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43600064 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 179130 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution +system.membus.trans_dist::CleanEvict 56614 # Transaction distribution +system.membus.trans_dist::UpgradeReq 192805 # Transaction distribution +system.membus.trans_dist::ReadExReq 206859 # Transaction distribution +system.membus.trans_dist::ReadExResp 206859 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 179131 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1316509 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43590400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43590400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43590400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 931402 # Request fanout histogram +system.membus.snoop_fanout::samples 930520 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 931402 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 930520 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 931402 # Request fanout histogram -system.membus.reqLayer0.occupancy 2242581485 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 930520 # Request fanout histogram +system.membus.reqLayer0.occupancy 2239434504 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2429056686 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2041939000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index 54314baaf..84e6b72bf 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.215512 # Nu sim_ticks 215512229500 # Number of ticks simulated final_tick 215512229500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175368 # Simulator instruction rate (inst/s) -host_op_rate 210548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138419960 # Simulator tick rate (ticks/s) -host_mem_usage 326400 # Number of bytes of host memory used -host_seconds 1556.94 # Real time elapsed on the host +host_inst_rate 167901 # Simulator instruction rate (inst/s) +host_op_rate 201584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132526721 # Simulator tick rate (ticks/s) +host_mem_usage 327404 # Number of bytes of host memory used +host_seconds 1626.18 # Real time elapsed on the host sim_insts 273037857 # Number of instructions simulated sim_ops 327812214 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -795,18 +795,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 40448 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 21970 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 228 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 36871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 344 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 38808 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 99585 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10260 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 109845 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3889728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 114486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10376 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 124862 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4843392 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 4243072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5196736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 43319 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.349062 # Request fanout histogram diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index d3ae1eec4..ac901384d 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.116576 # Nu sim_ticks 116576497500 # Number of ticks simulated final_tick 116576497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122787 # Simulator instruction rate (inst/s) -host_op_rate 147419 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 52425325 # Simulator tick rate (ticks/s) -host_mem_usage 336136 # Number of bytes of host memory used -host_seconds 2223.67 # Real time elapsed on the host +host_inst_rate 117910 # Simulator instruction rate (inst/s) +host_op_rate 141564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50343079 # Simulator tick rate (ticks/s) +host_mem_usage 339456 # Number of bytes of host memory used +host_seconds 2315.64 # Real time elapsed on the host sim_insts 273037220 # Number of instructions simulated sim_ops 327811602 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -44,7 +44,7 @@ system.physmem.bytesReadSys 5414912 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 955 # Per bank write bursts system.physmem.perBankRdBursts::1 811 # Per bank write bursts system.physmem.perBankRdBursts::2 833 # Per bank write bursts @@ -204,12 +204,12 @@ system.physmem.bytesPerActivate::768-895 32 0.14% 98.92% # By system.physmem.bytesPerActivate::896-1023 31 0.14% 99.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 209 0.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 22133 # Bytes accessed per row activation -system.physmem.totQLat 841966540 # Total ticks spent queuing -system.physmem.totMemAccLat 2428366540 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 841969540 # Total ticks spent queuing +system.physmem.totMemAccLat 2428369540 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 423040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9951.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9951.42 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28701.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28701.42 # Average memory access latency per DRAM burst system.physmem.avgRdBW 46.45 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 46.45 # Average system read bandwidth in MiByte/s @@ -231,28 +231,28 @@ system.physmem_0.preEnergy 78007875 # En system.physmem_0.readEnergy 595896600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63983016135 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 13820144250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 86234192340 # Total energy per rank (pJ) -system.physmem_0.averagePower 739.725124 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22625694019 # Time in different power states +system.physmem_0.actBackEnergy 63983019555 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 13820141250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 86234192760 # Total energy per rank (pJ) +system.physmem_0.averagePower 739.725127 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22625688019 # Time in different power states system.physmem_0.memoryStateTime::REF 3892720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 90057594731 # Time in different power states +system.physmem_0.memoryStateTime::ACT 90057600731 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 24358320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 13290750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 63999000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 7614160320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11183516280 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 60135495000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 79034819670 # Total energy per rank (pJ) -system.physmem_1.averagePower 677.968219 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 99984327847 # Time in different power states +system.physmem_1.actBackEnergy 11183518845 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 60135492750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 79034819985 # Total energy per rank (pJ) +system.physmem_1.averagePower 677.968221 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 99984324847 # Time in different power states system.physmem_1.memoryStateTime::REF 3892720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 12698960903 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12698963903 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 37744347 # Number of BP lookups system.cpu.branchPred.condPredicted 20165678 # Number of conditional branches predicted @@ -388,29 +388,29 @@ system.cpu.fetch.icacheStallCycles 12613908 # Nu system.cpu.fetch.Insts 334078036 # Number of instructions fetch has processed system.cpu.fetch.Branches 37744347 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 24523917 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 217730983 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.Cycles 217730977 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3511013 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 2593 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 89097958 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 22048 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 232104146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 232104140 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.745924 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.249191 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58364727 25.15% 25.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58364721 25.15% 25.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 42980177 18.52% 43.66% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 30021674 12.93% 56.60% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 100737568 43.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 232104146 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 232104140 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.161887 # Number of branch fetches per cycle system.cpu.fetch.rate 1.432870 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 28023980 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 70770838 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 70770832 # Number of cycles decode is blocked system.cpu.decode.RunCycles 108573375 # Number of cycles decode is running system.cpu.decode.UnblockCycles 23115192 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1620761 # Number of cycles decode is squashing @@ -421,7 +421,7 @@ system.cpu.decode.SquashedInsts 6170266 # Nu system.cpu.rename.SquashCycles 1620761 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 45363672 # Number of cycles rename is idle system.cpu.rename.BlockCycles 24814789 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 341990 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 341984 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 113350212 # Number of cycles rename is running system.cpu.rename.UnblockCycles 46612722 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 355770088 # Number of instructions processed by rename @@ -451,11 +451,11 @@ system.cpu.iq.iqSquashedInstsIssued 2301561 # Nu system.cpu.iq.iqSquashedInstsExamined 25470529 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 73751649 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 5712 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 232104146 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 232104140 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.492598 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.113201 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 47511470 20.47% 20.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 47511464 20.47% 20.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 78618745 33.87% 54.34% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 60884809 26.23% 80.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 34936770 15.05% 95.63% # Number of insts issued each cycle @@ -467,7 +467,7 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 232104146 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 232104140 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9573854 7.69% 7.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 7345 0.01% 7.69% # attempts to use FU when none available @@ -540,7 +540,7 @@ system.cpu.iq.FU_type_0::total 346438253 # Ty system.cpu.iq.rate 1.485884 # Inst issue rate system.cpu.iq.fu_busy_cnt 124543678 # FU busy when requested system.cpu.iq.fu_busy_rate 0.359497 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 764166784 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 764166778 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 251741027 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 223260031 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 287659107 # Number of floating instruction queue reads @@ -591,11 +591,11 @@ system.cpu.iew.wb_fanout 0.576282 # av system.cpu.commit.commitSquashedInsts 23083392 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1611406 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 228378919 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 228378913 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.435387 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.036441 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 94653053 41.45% 41.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 94653047 41.45% 41.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 70419351 30.83% 72.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 20855772 9.13% 81.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 13391170 5.86% 87.28% # Number of insts commited each cycle @@ -607,7 +607,7 @@ system.cpu.commit.committed_per_cycle::8 10359612 4.54% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 228378919 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 228378913 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037832 # Number of instructions committed system.cpu.commit.committedOps 327812214 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,10 +654,10 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812214 # Class of committed instruction system.cpu.commit.bw_lim_events 10359612 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 568912390 # The number of ROB reads +system.cpu.rob.rob_reads 568912384 # The number of ROB reads system.cpu.rob.rob_writes 705520379 # The number of ROB writes system.cpu.timesIdled 58444 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1048850 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 1048856 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037220 # Number of Instructions Simulated system.cpu.committedOps 327811602 # Number of Ops (including micro ops) Simulated system.cpu.cpi 0.853924 # CPI: Cycles Per Instruction @@ -717,14 +717,14 @@ system.cpu.dcache.overall_misses::cpu.data 3911467 # system.cpu.dcache.overall_misses::total 3911467 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 31000710000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 31000710000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973516996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8973516996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8973513996 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8973513996 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39974226996 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39974226996 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39974226996 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39974226996 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39974223996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39974223996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39974223996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39974223996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 85407824 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 85407824 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) @@ -753,14 +753,14 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.023348 system.cpu.dcache.overall_miss_rate::total 0.023348 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11074.775169 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 11074.775169 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.033525 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.033525 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8068.030828 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8068.030828 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37800 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37800 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.800129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10219.800129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.753099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10219.753099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10219.799362 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10219.799362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10219.752332 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10219.752332 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1061203 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,14 +793,14 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 1534352 system.cpu.dcache.overall_mshr_misses::total 1534352 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15231288500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 15231288500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828351773 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828351773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1828348773 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1828348773 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 681500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 681500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059640273 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17059640273 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060321773 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17060321773 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17059637273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17059637273 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17060318773 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17060318773 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015381 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015381 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses @@ -813,14 +813,14 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11594.314395 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11594.314395 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.020136 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.020136 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8286.006540 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8286.006540 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61954.545455 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61954.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.545534 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.545534 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.909985 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.909985 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11118.543579 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11118.543579 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11118.908030 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11118.908030 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 715978 # number of replacements system.cpu.icache.tags.tagsinuse 511.829667 # Cycle average of tags in use @@ -852,12 +852,12 @@ system.cpu.icache.demand_misses::cpu.inst 722244 # n system.cpu.icache.demand_misses::total 722244 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 722244 # number of overall misses system.cpu.icache.overall_misses::total 722244 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486041445 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 6486041445 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 6486041445 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 6486041445 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 6486041445 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 6486041445 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 6486047445 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 6486047445 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 6486047445 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 6486047445 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 6486047445 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 6486047445 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 89097944 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 89097944 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 89097944 # number of demand (read+write) accesses @@ -870,12 +870,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.008106 system.cpu.icache.demand_miss_rate::total 0.008106 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.008106 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.008106 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.401976 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8980.401976 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8980.401976 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.401976 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8980.401976 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8980.410284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8980.410284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8980.410284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8980.410284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8980.410284 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 66919 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2190 # number of cycles access was blocked @@ -898,38 +898,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 716491 system.cpu.icache.demand_mshr_misses::total 716491 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 716491 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 716491 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035132455 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6035132455 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035132455 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6035132455 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035132455 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6035132455 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6035135455 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6035135455 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6035135455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6035135455 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6035135455 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6035135455 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008042 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.008042 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008042 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.008042 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.179712 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.179712 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.179712 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.179712 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8423.183899 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8423.183899 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8423.183899 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8423.183899 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 404824 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 404865 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 404830 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404871 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 38 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28167 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28177 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5610.545510 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 5610.545509 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3011470 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 6745 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 446.474426 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326452 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 5502.326450 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 108.219059 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.335835 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006605 # Average percentage of cache occupancy @@ -982,20 +982,20 @@ system.cpu.l2cache.demand_misses::total 82055 # nu system.cpu.l2cache.overall_misses::cpu.inst 9709 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 72346 # number of overall misses system.cpu.l2cache.overall_misses::total 82055 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 19500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 19500 # number of UpgradeReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55912000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 55912000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697537000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 697537000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 697540000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 697540000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5069165500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 5069165500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 697537000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 697540000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 5125077500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 5822614500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 697537000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 5822617500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 697540000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 5125077500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 5822614500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 5822617500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 965413 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 965413 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 1035068 # number of WritebackClean accesses(hits+misses) @@ -1028,20 +1028,20 @@ system.cpu.l2cache.demand_miss_rate::total 0.036464 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013561 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.047151 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.036464 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 22500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 22500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19500 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19500 # average UpgradeReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72424.870466 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72424.870466 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.371202 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.371202 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71844.680194 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71844.680194 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 70824.119094 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 70824.119094 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.371202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70959.898848 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.371202 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70959.935409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71844.680194 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70841.200619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70959.898848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70959.935409 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1062,8 +1062,8 @@ system.cpu.l2cache.demand_mshr_hits::total 89 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 77 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51607 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 51607 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 51610 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 51610 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 728 # number of ReadExReq MSHR misses @@ -1077,25 +1077,25 @@ system.cpu.l2cache.demand_mshr_misses::cpu.data 72269 system.cpu.l2cache.demand_mshr_misses::total 81966 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 9697 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 72269 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51607 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 133573 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 51610 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 133576 # number of overall MSHR misses system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 180856312 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 50141500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 50141500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638751500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638751500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 638754500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 638754500 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4638052000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4638052000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638751500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 638754500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4688193500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5326945000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638751500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5326948000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 638754500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4688193500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 180856312 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5507801312 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5507804312 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses @@ -1112,60 +1112,60 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.036424 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013544 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.059358 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.491871 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.059359 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3504.288161 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13500 # average UpgradeReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68875.686813 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68875.686813 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.042590 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.042590 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65871.351965 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65871.351965 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64830.684503 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64830.684503 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.690847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.042590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64989.727448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65871.351965 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64871.431734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.491871 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41234.391022 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3504.288161 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41233.487393 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4500659 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2249836 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 249343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 130203 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52857 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 130206 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 52860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 77346 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 2030188 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 965413 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1035068 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1284403 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 81238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 52995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 52998 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 220653 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 716491 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1313697 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2123993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4377646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6501639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 90080128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 181970688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 272050816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134761 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2385076 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.191571 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2148432 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4602542 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6750974 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 91644224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 196364032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 288008256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 134764 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2385079 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.191572 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.468754 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 2005511 84.09% 84.09% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 302219 12.67% 96.76% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 302222 12.67% 96.76% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 77346 3.24% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2385076 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2385079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 4500145500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1075017936 # Layer occupancy (ticks) @@ -1174,12 +1174,11 @@ system.cpu.toL2Bus.respLayer1.occupancy 2302043463 # La system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) system.membus.trans_dist::ReadResp 83880 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1 # Transaction distribution system.membus.trans_dist::ReadExReq 728 # Transaction distribution system.membus.trans_dist::ReadExResp 728 # Transaction distribution system.membus.trans_dist::ReadSharedReq 83880 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169218 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 169218 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 169217 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 169217 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 5414912 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 5414912 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) @@ -1195,7 +1194,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 84609 # Request fanout histogram system.membus.reqLayer0.occupancy 103435410 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 446650667 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 446648668 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 863619ff4..42b8a5c86 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.517291 # Nu sim_ticks 517291025500 # Number of ticks simulated final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 635145 # Simulator instruction rate (inst/s) -host_op_rate 762516 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1204648551 # Simulator tick rate (ticks/s) -host_mem_usage 323584 # Number of bytes of host memory used -host_seconds 429.41 # Real time elapsed on the host +host_inst_rate 634406 # Simulator instruction rate (inst/s) +host_op_rate 761628 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1203245454 # Simulator tick rate (ticks/s) +host_mem_usage 324572 # Number of bytes of host memory used +host_seconds 429.91 # Real time elapsed on the host sim_insts 272739286 # Number of instructions simulated sim_ops 327433744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -602,18 +602,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37418 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10207 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 47625 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1396160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1746624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 1ecb81d4d..fb73a0a48 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.560955 # Nu sim_ticks 560955232000 # Number of ticks simulated final_tick 560955232000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340981 # Simulator instruction rate (inst/s) -host_op_rate 340981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 205940379 # Simulator tick rate (ticks/s) -host_mem_usage 308844 # Number of bytes of host memory used -host_seconds 2723.87 # Real time elapsed on the host +host_inst_rate 326346 # Simulator instruction rate (inst/s) +host_op_rate 326346 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197101410 # Simulator tick rate (ticks/s) +host_mem_usage 309500 # Number of bytes of host memory used +host_seconds 2846.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18704768 # To system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 191173 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18033 # Per bank write bursts system.physmem.perBankRdBursts::1 18359 # Per bank write bursts system.physmem.perBankRdBursts::2 18394 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 560955208000 # Total gap between requests +system.physmem.totGap 560955150000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -248,7 +248,7 @@ system.physmem.readRowHits 202530 # Nu system.physmem.writeRowHits 52011 # Number of row buffer hits during writes system.physmem.readRowHitRate 69.37 # Row buffer hit rate for reads system.physmem.writeRowHitRate 78.00 # Row buffer hit rate for writes -system.physmem.avgGap 1562788.75 # Average gap between requests +system.physmem.avgGap 1562788.59 # Average gap between requests system.physmem.pageHitRate 70.98 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 392416920 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 214116375 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index a16b516f4..72a187780 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.276414 # Nu sim_ticks 276414065500 # Number of ticks simulated final_tick 276414065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180346 # Simulator instruction rate (inst/s) -host_op_rate 180346 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59177560 # Simulator tick rate (ticks/s) -host_mem_usage 308352 # Number of bytes of host memory used -host_seconds 4670.93 # Real time elapsed on the host +host_inst_rate 168860 # Simulator instruction rate (inst/s) +host_op_rate 168860 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55408638 # Simulator tick rate (ticks/s) +host_mem_usage 309496 # Number of bytes of host memory used +host_seconds 4988.65 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18696320 # To system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side system.physmem.servicedByWrQ 331 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 191079 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18006 # Per bank write bursts system.physmem.perBankRdBursts::1 18321 # Per bank write bursts system.physmem.perBankRdBursts::2 18379 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 276414034500 # Total gap between requests +system.physmem.totGap 276413976000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -247,7 +247,7 @@ system.physmem.readRowHits 207034 # Nu system.physmem.writeRowHits 52000 # Number of row buffer hits during writes system.physmem.readRowHitRate 70.95 # Row buffer hit rate for reads system.physmem.writeRowHitRate 77.98 # Row buffer hit rate for writes -system.physmem.avgGap 770356.80 # Average gap between requests +system.physmem.avgGap 770356.64 # Average gap between requests system.physmem.pageHitRate 72.26 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 374197320 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 204175125 # Energy for precharge commands per rank (pJ) diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index c95abda26..5f2d8e18a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.542265 # Nu sim_ticks 542265386500 # Number of ticks simulated final_tick 542265386500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179877 # Simulator instruction rate (inst/s) -host_op_rate 221452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152251725 # Simulator tick rate (ticks/s) -host_mem_usage 325476 # Number of bytes of host memory used -host_seconds 3561.64 # Real time elapsed on the host +host_inst_rate 173269 # Simulator instruction rate (inst/s) +host_op_rate 213317 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 146659072 # Simulator tick rate (ticks/s) +host_mem_usage 328008 # Number of bytes of host memory used +host_seconds 3697.46 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 18637888 # To system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side system.physmem.servicedByWrQ 317 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 190686 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 18283 # Per bank write bursts system.physmem.perBankRdBursts::1 18129 # Per bank write bursts system.physmem.perBankRdBursts::2 18220 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 542265360500 # Total gap between requests +system.physmem.totGap 542265292000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -243,7 +243,7 @@ system.physmem.readRowHits 194203 # Nu system.physmem.writeRowHits 51643 # Number of row buffer hits during writes system.physmem.readRowHitRate 66.76 # Row buffer hit rate for reads system.physmem.writeRowHitRate 78.13 # Row buffer hit rate for writes -system.physmem.avgGap 1517611.52 # Average gap between requests +system.physmem.avgGap 1517611.33 # Average gap between requests system.physmem.pageHitRate 68.86 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 420789600 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 229597500 # Energy for precharge commands per rank (pJ) @@ -818,18 +818,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2013 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 738455 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 154791 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 22257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 880344 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 23591 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882361 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 25343 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 713113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341192 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2414134 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3046336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2343209 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2417485 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3131712 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 58798528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 58883904 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 258813 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1066591 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.005113 # Request fanout histogram diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 9a207ffb1..9b1e23041 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,81 +1,81 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.452586 # Number of seconds simulated -sim_ticks 452585997000 # Number of ticks simulated -final_tick 452585997000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.452564 # Number of seconds simulated +sim_ticks 452563515000 # Number of ticks simulated +final_tick 452563515000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89374 # Simulator instruction rate (inst/s) -host_op_rate 110031 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63138171 # Simulator tick rate (ticks/s) -host_mem_usage 323296 # Number of bytes of host memory used -host_seconds 7168.18 # Real time elapsed on the host +host_inst_rate 88595 # Simulator instruction rate (inst/s) +host_op_rate 109072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62584453 # Simulator tick rate (ticks/s) +host_mem_usage 324544 # Number of bytes of host memory used +host_seconds 7231.25 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 234368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 47997568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12828032 # Number of bytes read from this memory -system.physmem.bytes_read::total 61059968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 234368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 234368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4243520 # Number of bytes written to this memory -system.physmem.bytes_written::total 4243520 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3662 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 749962 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 200438 # Number of read requests responded to by this memory -system.physmem.num_reads::total 954062 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66305 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66305 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 517842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 106051818 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 28343855 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134913516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 517842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 517842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9376163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 9376163 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9376163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 517842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 106051818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 28343855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 144289678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 954063 # Number of read requests accepted -system.physmem.writeReqs 66305 # Number of write requests accepted -system.physmem.readBursts 954063 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66305 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61041664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18368 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 234304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48000768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12823616 # Number of bytes read from this memory +system.physmem.bytes_read::total 61058688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 234304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 234304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4243456 # Number of bytes written to this memory +system.physmem.bytes_written::total 4243456 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 750012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 200369 # Number of read requests responded to by this memory +system.physmem.num_reads::total 954042 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66304 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 517726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 106064158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 28335506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134917389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517726 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9376487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 9376487 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9376487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 106064158 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 28335506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 144293877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 954043 # Number of read requests accepted +system.physmem.writeReqs 66304 # Number of write requests accepted +system.physmem.readBursts 954043 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66304 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61040512 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue system.physmem.bytesWritten 4238400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61060032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4243520 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 287 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 227627 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19636 # Per bank write bursts -system.physmem.perBankRdBursts::1 19225 # Per bank write bursts -system.physmem.perBankRdBursts::2 656809 # Per bank write bursts -system.physmem.perBankRdBursts::3 20104 # Per bank write bursts -system.physmem.perBankRdBursts::4 19566 # Per bank write bursts -system.physmem.perBankRdBursts::5 20746 # Per bank write bursts -system.physmem.perBankRdBursts::6 19449 # Per bank write bursts -system.physmem.perBankRdBursts::7 19830 # Per bank write bursts -system.physmem.perBankRdBursts::8 19282 # Per bank write bursts -system.physmem.perBankRdBursts::9 19792 # Per bank write bursts -system.physmem.perBankRdBursts::10 19287 # Per bank write bursts -system.physmem.perBankRdBursts::11 19476 # Per bank write bursts -system.physmem.perBankRdBursts::12 19427 # Per bank write bursts -system.physmem.perBankRdBursts::13 20933 # Per bank write bursts -system.physmem.perBankRdBursts::14 19357 # Per bank write bursts -system.physmem.perBankRdBursts::15 20857 # Per bank write bursts +system.physmem.bytesReadSys 61058752 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4243456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 53 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19632 # Per bank write bursts +system.physmem.perBankRdBursts::1 19241 # Per bank write bursts +system.physmem.perBankRdBursts::2 656774 # Per bank write bursts +system.physmem.perBankRdBursts::3 20103 # Per bank write bursts +system.physmem.perBankRdBursts::4 19565 # Per bank write bursts +system.physmem.perBankRdBursts::5 20788 # Per bank write bursts +system.physmem.perBankRdBursts::6 19429 # Per bank write bursts +system.physmem.perBankRdBursts::7 19781 # Per bank write bursts +system.physmem.perBankRdBursts::8 19292 # Per bank write bursts +system.physmem.perBankRdBursts::9 19805 # Per bank write bursts +system.physmem.perBankRdBursts::10 19337 # Per bank write bursts +system.physmem.perBankRdBursts::11 19452 # Per bank write bursts +system.physmem.perBankRdBursts::12 19407 # Per bank write bursts +system.physmem.perBankRdBursts::13 20952 # Per bank write bursts +system.physmem.perBankRdBursts::14 19359 # Per bank write bursts +system.physmem.perBankRdBursts::15 20841 # Per bank write bursts system.physmem.perBankWrBursts::0 4254 # Per bank write bursts -system.physmem.perBankWrBursts::1 4108 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts system.physmem.perBankWrBursts::2 4140 # Per bank write bursts system.physmem.perBankWrBursts::3 4154 # Per bank write bursts system.physmem.perBankWrBursts::4 4243 # Per bank write bursts system.physmem.perBankWrBursts::5 4230 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts -system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::7 4093 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts @@ -83,27 +83,27 @@ system.physmem.perBankWrBursts::11 4097 # Pe system.physmem.perBankWrBursts::12 4098 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4153 # Per bank write bursts +system.physmem.perBankWrBursts::15 4155 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 452585986500 # Total gap between requests +system.physmem.totGap 452563504500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 954063 # Read request sizes (log2) +system.physmem.readPktSize::6 954043 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66305 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 760072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121484 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14330 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66304 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 760089 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14329 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 6788 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 6461 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 7610 # What read queue length does an incoming req see @@ -150,15 +150,15 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4997 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 5065 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 5200 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 5020 # What write queue length does an incoming req see @@ -197,30 +197,32 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 205647 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 317.429381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.568290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.974442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59802 29.08% 29.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 62661 30.47% 59.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15924 7.74% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3207 1.56% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3374 1.64% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 48035 23.36% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7705 3.75% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 205577 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.529062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.622998 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.021434 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59787 29.08% 29.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62582 30.44% 59.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15931 7.75% 67.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3214 1.56% 68.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3392 1.65% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 47997 23.35% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7735 3.76% 97.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1172 0.57% 98.17% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3767 1.83% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 205647 # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 205577 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4029 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 234.045421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.559432 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3989.674296 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 4017 99.70% 99.70% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-16383 7 0.17% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-32767 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::90112-98303 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::212992-221183 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 209.250931 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 40.553257 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2756.803776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 4005 99.40% 99.40% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24576-28671 2 0.05% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::61440-65535 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::94208-98303 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::114688-118783 1 0.02% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::total 4029 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4029 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.437081 # Writes before turning the bus around for reads @@ -242,65 +244,65 @@ system.physmem.wrPerTurnAround::28 3 0.07% 99.90% # Wr system.physmem.wrPerTurnAround::29 2 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 2 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4029 # Writes before turning the bus around for reads -system.physmem.totQLat 15106541272 # Total ticks spent queuing -system.physmem.totMemAccLat 32989841272 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4768880000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15838.67 # Average queueing delay per DRAM burst +system.physmem.totQLat 15078460254 # Total ticks spent queuing +system.physmem.totMemAccLat 32961422754 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4768790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15809.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34588.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.87 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 9.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.91 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 34559.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 9.37 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.92 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 9.38 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.13 # Data bus utilization in percentage system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 788463 # Number of row buffer hits during reads -system.physmem.writeRowHits 25883 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing +system.physmem.readRowHits 788510 # Number of row buffer hits during reads +system.physmem.writeRowHits 25885 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.07 # Row buffer hit rate for writes -system.physmem.avgGap 443551.72 # Average gap between requests +system.physmem.avgGap 443538.82 # Average gap between requests system.physmem.pageHitRate 79.84 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1032091200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 563145000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6203792400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216412560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 305512170480 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 3557164500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 346645334700 # Total energy per rank (pJ) -system.physmem_0.averagePower 765.925147 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4194914578 # Time in different power states -system.physmem_0.memoryStateTime::REF 15112760000 # Time in different power states +system.physmem_0.actEnergy 1031660280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 562909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6203308800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216399600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305467849845 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 3582027000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 346623188280 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.915744 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4235605578 # Time in different power states +system.physmem_0.memoryStateTime::REF 15111980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 433276166672 # Time in different power states +system.physmem_0.memoryStateTime::ACT 433212896922 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 522539640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 285115875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1235348400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29560558560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96876011835 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 186571355250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 315263655000 # Total energy per rank (pJ) -system.physmem_1.averagePower 696.586172 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 309737229647 # Time in different power states -system.physmem_1.memoryStateTime::REF 15112760000 # Time in different power states +system.physmem_1.actEnergy 522411120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 285045750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1235535600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212738400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29559032880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96975747585 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 186469836000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 315260347335 # Total energy per rank (pJ) +system.physmem_1.averagePower 696.614859 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 309568131397 # Time in different power states +system.physmem_1.memoryStateTime::REF 15111980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127733879103 # Time in different power states +system.physmem_1.memoryStateTime::ACT 127880371103 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 234612390 # Number of BP lookups -system.cpu.branchPred.condPredicted 162472835 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514556 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121579993 # Number of BTB lookups -system.cpu.branchPred.BTBHits 107625887 # Number of BTB hits +system.cpu.branchPred.lookups 234612924 # Number of BP lookups +system.cpu.branchPred.condPredicted 162473080 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514448 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121580360 # Number of BTB lookups +system.cpu.branchPred.BTBHits 107626063 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.522696 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035644 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300133 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 88.522573 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25035646 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300027 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -419,84 +421,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 905171995 # number of cpu cycles simulated +system.cpu.numCycles 905127031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 86003110 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1202048869 # Number of instructions fetch has processed -system.cpu.fetch.Branches 234612390 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 132661531 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 803279049 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064713 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1868 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 85998683 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1202051079 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234612924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 132661709 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 803240111 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31064493 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1917 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3204 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370083974 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652982 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 904819618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.657214 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.229926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3269 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370084311 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652880 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 904776257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.657297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 222849160 24.63% 24.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 224059075 24.76% 49.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98313082 10.87% 60.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 359598301 39.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 222804793 24.63% 24.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 224059137 24.76% 49.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98313262 10.87% 60.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 359599065 39.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 904819618 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259191 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.327978 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 121904104 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 244100755 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484657410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38638668 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518681 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24546049 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13811 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248144086 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39968857 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518681 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 178914873 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 163328471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207028 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464319861 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82530704 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190654266 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 24276153 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24946873 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2269725 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 41528835 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1707155 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1226040359 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5813734095 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358184137 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876447 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 904776257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259204 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.328047 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 121900634 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 244061321 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484657119 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38638613 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518570 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24546046 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13813 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248144936 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39968729 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518570 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 178911503 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 163289745 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 206869 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464319515 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82530055 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190655236 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 24276259 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24947259 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2269584 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41529012 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1706231 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1226042317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5813738555 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358185798 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876436 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 351262129 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 351264087 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 7264 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108789591 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 367388897 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236094901 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1672944 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5307285 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1169836169 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12331 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017123135 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19093941 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 381123542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1038508983 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 177 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 904819618 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.124117 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.093910 # Number of insts issued each cycle +system.cpu.rename.skidInsts 108789745 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 367388846 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236095095 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1811043 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5312656 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1169837126 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12332 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1017086167 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18990404 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 381124500 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1038523748 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 904776257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.124130 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.093860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 347160042 38.37% 38.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 227103662 25.10% 63.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 217769500 24.07% 87.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 96665190 10.68% 98.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16121217 1.78% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 347117204 38.36% 38.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227104713 25.10% 63.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 217802755 24.07% 87.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 96630403 10.68% 98.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16121175 1.78% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -504,9 +506,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 904819618 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 904776257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 63881232 18.86% 18.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 63882217 18.87% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 18143 0.01% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 18.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.87% # attempts to use FU when none available @@ -535,12 +537,12 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.06% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.06% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 158064095 46.67% 65.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116064822 34.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 158029640 46.67% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116058922 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456367780 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456367665 44.87% 44.87% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5195678 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued @@ -565,86 +567,86 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478995 1.13% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322109040 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215596292 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322074351 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215594127 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017123135 # Type of FU issued -system.cpu.iq.rate 1.123679 # Inst issue rate -system.cpu.iq.fu_busy_cnt 338665181 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.332964 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3234948583 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1507425320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934275773 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61876427 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565693 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 1017086167 # Type of FU issued +system.cpu.iq.rate 1.123694 # Inst issue rate +system.cpu.iq.fu_busy_cnt 338625811 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.332937 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3234688378 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1507427240 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934273902 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61876428 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565689 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 26152450 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1321978571 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 1321902233 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33809745 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9959468 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9959480 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 115147959 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 115147908 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1093 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 18974 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107114405 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 107114599 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065764 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19863 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19869 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518681 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35329232 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 27153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1169854056 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518570 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35329075 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 27772 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1169855013 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 367388897 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236094901 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6591 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 89 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29598 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 367388846 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236095095 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6592 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 88 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 30218 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 18974 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437212 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784515 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19221727 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974753111 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303296723 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42370024 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 15437101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784620 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221721 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974751329 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303296690 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42334838 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497769972 # number of memory reference insts executed -system.cpu.iew.exec_branches 150611064 # Number of branches executed -system.cpu.iew.exec_stores 194473249 # Number of stores executed -system.cpu.iew.exec_rate 1.076871 # Inst execution rate -system.cpu.iew.wb_sent 963726707 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960428223 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536045857 # num instructions producing a value -system.cpu.iew.wb_consumers 893287669 # num instructions consuming a value -system.cpu.iew.wb_rate 1.061045 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600082 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 357425551 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 5555 # number of nop insts executed +system.cpu.iew.exec_refs 497768330 # number of memory reference insts executed +system.cpu.iew.exec_branches 150610966 # Number of branches executed +system.cpu.iew.exec_stores 194471640 # Number of stores executed +system.cpu.iew.exec_rate 1.076922 # Inst execution rate +system.cpu.iew.wb_sent 963724922 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960426352 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536046741 # num instructions producing a value +system.cpu.iew.wb_consumers 893290325 # num instructions consuming a value +system.cpu.iew.wb_rate 1.061096 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600081 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 357426439 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15500881 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 853996264 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.923576 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.715161 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500772 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 853952830 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.923623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.715196 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 515355287 60.35% 60.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174404345 20.42% 80.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 72937486 8.54% 89.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 32899801 3.85% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8539084 1.00% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14259189 1.67% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7267219 0.85% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 5975069 0.70% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22358784 2.62% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 515313788 60.34% 60.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 174402011 20.42% 80.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 72937800 8.54% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 32899590 3.85% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8538808 1.00% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14259214 1.67% 95.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7267758 0.85% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 5975049 0.70% 97.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22358812 2.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 853996264 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 853952830 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -690,80 +692,80 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 22358784 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1977784350 # The number of ROB reads -system.cpu.rob.rob_writes 2343138350 # The number of ROB writes -system.cpu.timesIdled 648611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 352377 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 22358812 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1977741776 # The number of ROB reads +system.cpu.rob.rob_writes 2343140199 # The number of ROB writes +system.cpu.timesIdled 648615 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 350774 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.412898 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.412898 # CPI: Total CPI of All Threads -system.cpu.ipc 0.707765 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.707765 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995811618 # number of integer regfile reads -system.cpu.int_regfile_writes 567906414 # number of integer regfile writes +system.cpu.cpi 1.412828 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.412828 # CPI: Total CPI of All Threads +system.cpu.ipc 0.707800 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.707800 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995808117 # number of integer regfile reads +system.cpu.int_regfile_writes 567906123 # number of integer regfile writes system.cpu.fp_regfile_reads 31889839 # number of floating regfile reads system.cpu.fp_regfile_writes 22959494 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794441379 # number of cc regfile reads -system.cpu.cc_regfile_writes 384896518 # number of cc regfile writes -system.cpu.misc_regfile_reads 715823215 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794435958 # number of cc regfile reads +system.cpu.cc_regfile_writes 384896498 # number of cc regfile writes +system.cpu.misc_regfile_reads 715821566 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756185 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.937157 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414216587 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756697 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.258294 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2756183 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.937153 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414216547 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756695 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.258388 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267553000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.937157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.937153 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347973 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347973 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286293800 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286293800 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127906811 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127906811 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 839347867 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839347867 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286293756 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286293756 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906808 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906808 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414200611 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414200611 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414203768 # number of overall hits -system.cpu.dcache.overall_hits::total 414203768 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3035079 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3035079 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044666 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044666 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 414200564 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414200564 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414203721 # number of overall hits +system.cpu.dcache.overall_hits::total 414203721 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3035071 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3035071 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1044669 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1044669 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4079745 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4079745 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4080391 # number of overall misses -system.cpu.dcache.overall_misses::total 4080391 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 76869214000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 76869214000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10006334850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10006334850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4079740 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4079740 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4080386 # number of overall misses +system.cpu.dcache.overall_misses::total 4080386 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 76845731000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 76845731000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10002174850 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10002174850 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 187500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86875548850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86875548850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86875548850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86875548850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 86847905850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86847905850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86847905850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86847905850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289328827 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289328827 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3803 # number of SoftPFReq accesses(hits+misses) @@ -772,10 +774,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284159 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284159 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 418280304 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418280304 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418284107 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418284107 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010490 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.010490 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008101 # miss rate for WriteReq accesses @@ -788,56 +790,56 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009754 system.cpu.dcache.demand_miss_rate::total 0.009754 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009755 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009755 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25326.923615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25326.923615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9578.501502 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9578.501502 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25319.253158 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25319.253158 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9574.491873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9574.491873 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 21294.357576 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 21294.357576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21290.986293 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21290.986293 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21287.607997 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21287.607997 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21284.237778 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21284.237778 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 352038 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 351058 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4878 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4882 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.168512 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 71.908644 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2756185 # number of writebacks -system.cpu.dcache.writebacks::total 2756185 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 999872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323643 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323643 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2756183 # number of writebacks +system.cpu.dcache.writebacks::total 2756183 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999866 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 999866 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323646 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 323646 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1323515 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1323515 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1323515 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1323515 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035207 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035207 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1323512 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1323512 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1323512 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1323512 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035205 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035205 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 721023 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 721023 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756230 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756230 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756871 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756871 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65569114500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 65569114500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5957184350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5957184350 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5576500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71526298850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 71526298850 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71531875350 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 71531875350 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756228 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756228 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756869 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756869 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 65547149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 65547149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5956550350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5956550350 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5499000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5499000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 71503699350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 71503699350 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 71509198350 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 71509198350 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005591 # mshr miss rate for WriteReq accesses @@ -848,229 +850,229 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32217.417933 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32217.417933 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8262.128046 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8262.128046 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8699.687988 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8699.687988 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25950.772922 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25950.772922 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25946.761872 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25946.761872 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32206.656823 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32206.656823 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8261.248740 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8261.248740 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8578.783151 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8578.783151 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25942.592322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25942.592322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25938.555060 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25938.555060 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169363 # number of replacements -system.cpu.icache.tags.tagsinuse 510.872217 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364909729 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169873 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.583886 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5169029 # number of replacements +system.cpu.icache.tags.tagsinuse 510.720775 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 364910405 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5169539 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.588578 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 257528500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.872217 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997797 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.720775 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997502 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997502 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id 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-system.cpu.icache.demand_misses::cpu.inst 5174203 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5174203 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5174203 # number of overall misses -system.cpu.icache.overall_misses::total 5174203 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41972246420 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41972246420 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41972246420 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41972246420 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41972246420 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41972246420 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370083947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370083947 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370083947 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370083947 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370083947 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370083947 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013981 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013981 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013981 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013981 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013981 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013981 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.828318 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8111.828318 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8111.828318 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.828318 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8111.828318 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 80154 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 745338281 # Number of tag accesses +system.cpu.icache.tags.data_accesses 745338281 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 364910416 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 364910416 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 364910416 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 364910416 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 364910416 # number of overall hits +system.cpu.icache.overall_hits::total 364910416 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5173868 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5173868 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5173868 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5173868 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5173868 # number of overall misses +system.cpu.icache.overall_misses::total 5173868 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41967552420 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41967552420 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41967552420 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41967552420 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41967552420 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41967552420 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370084284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370084284 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370084284 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370084284 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370084284 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370084284 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013980 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013980 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013980 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013980 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8111.446295 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8111.446295 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8111.446295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8111.446295 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8111.446295 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 79493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 135 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3667 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3635 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.858195 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.868776 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 5169363 # number of writebacks -system.cpu.icache.writebacks::total 5169363 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4154 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4154 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4154 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4154 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4154 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4154 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170049 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5170049 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5170049 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5170049 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5170049 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5170049 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39346514434 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 39346514434 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39346514434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 39346514434 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39346514434 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 39346514434 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.472248 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.472248 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.472248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.472248 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5169029 # number of writebacks +system.cpu.icache.writebacks::total 5169029 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4153 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4153 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4153 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4153 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4153 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169715 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5169715 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5169715 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5169715 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5169715 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5169715 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 39342077434 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 39342077434 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 39342077434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 39342077434 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 39342077434 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 39342077434 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013969 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013969 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013969 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013969 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7610.105670 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7610.105670 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7610.105670 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7610.105670 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1350388 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355069 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 1350427 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355108 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 4095 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790235 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 301561 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16356.089687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13502376 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 317924 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 42.470452 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 4790132 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 301513 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16356.090183 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13598662 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 317875 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 42.779904 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 60356537500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9847.960617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6508.129070 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.601072 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397225 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998296 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6319 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 10044 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4867 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7658 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.385681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.613037 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 244381666 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 244381666 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::writebacks 9848.276079 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6507.814104 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.601091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.397205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6290 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 10072 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4827 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied 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number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2453000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2453000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 133666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 133666500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 246204000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 246204000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 49598643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 49598643500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 246204000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49732310000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 49978514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 246204000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49732310000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 16513318471 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66491832471 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001895 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000709 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367707 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367707 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.095076 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000709 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272051 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.000708 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.367734 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.367734 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.095086 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000708 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.272069 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.120374 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82372.666141 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17204.022989 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17204.022989 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 97926.061493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 97926.061493 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67728.091728 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67728.091728 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66284.957440 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66284.957440 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66349.323603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67728.091728 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66342.589358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82372.666141 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69716.843102 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120377 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82377.535910 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14097.701149 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14097.701149 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 98139.867841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 98139.867841 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67232.113599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67232.113599 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 66250.776064 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 66250.776064 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66313.172539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67232.113599 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66308.685728 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82377.535910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69688.222157 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 15852468 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925752 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 15851796 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 7925416 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644350 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 760150 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116849 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7205895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6546111 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 987513 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 243924 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_snoops 760180 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 116881 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 643299 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 7205559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 7189951 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 987519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 243847 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 174 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5170049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035848 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7626630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23135037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661654912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311653440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 973308352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1297915 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9224662 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.222014 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.558747 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadCleanReq 5169715 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2035846 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15508284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8269921 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23778205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 661668416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352824192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1014492608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1297843 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9224254 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.222027 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.558758 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7819958 84.77% 84.77% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 761403 8.25% 93.03% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 643301 6.97% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7819520 84.77% 84.77% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 761435 8.25% 93.03% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 643299 6.97% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9224662 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15851782000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9224254 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15851110000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755313513 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7754813511 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135165933 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135160937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadResp 952696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66305 # Transaction distribution -system.membus.trans_dist::CleanEvict 227453 # Transaction distribution +system.membus.trans_dist::ReadResp 952680 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66304 # Transaction distribution +system.membus.trans_dist::CleanEvict 227429 # Transaction distribution system.membus.trans_dist::UpgradeReq 174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 174 # Transaction distribution -system.membus.trans_dist::ReadExReq 1366 # Transaction distribution -system.membus.trans_dist::ReadExResp 1366 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 952697 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2202231 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2202231 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65303488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65303488 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 1362 # Transaction distribution +system.membus.trans_dist::ReadExResp 1362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 952681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2201992 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2201992 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65302144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65302144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1247995 # Request fanout histogram +system.membus.snoop_fanout::samples 1247950 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1247995 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1247950 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1247995 # Request fanout histogram -system.membus.reqLayer0.occupancy 1752388071 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1247950 # Request fanout histogram +system.membus.reqLayer0.occupancy 1752348040 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5021031104 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5020538027 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index dd5f11d63..92b150303 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.045756 # Nu sim_ticks 1045756396500 # Number of ticks simulated final_tick 1045756396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734670 # Simulator instruction rate (inst/s) -host_op_rate 902587 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1201635964 # Simulator tick rate (ticks/s) -host_mem_usage 323928 # Number of bytes of host memory used -host_seconds 870.28 # Real time elapsed on the host +host_inst_rate 725560 # Simulator instruction rate (inst/s) +host_op_rate 891395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1186735876 # Simulator tick rate (ticks/s) +host_mem_usage 325196 # Number of bytes of host memory used +host_seconds 881.20 # Real time elapsed on the host sim_insts 639366787 # Number of instructions simulated sim_ops 785501035 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -609,18 +609,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1573 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 155093 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 8752 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879632 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 8769 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 880725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29168 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2341237 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2370405 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1213440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2371515 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55752768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56966208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56967296 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 257772 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1050122 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.002597 # Request fanout histogram diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index e086bc978..2126b1202 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.059474 # Nu sim_ticks 59473862000 # Number of ticks simulated final_tick 59473862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 342067 # Simulator instruction rate (inst/s) -host_op_rate 342067 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230037089 # Simulator tick rate (ticks/s) -host_mem_usage 307480 # Number of bytes of host memory used -host_seconds 258.54 # Real time elapsed on the host +host_inst_rate 330532 # Simulator instruction rate (inst/s) +host_op_rate 330532 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 222279677 # Simulator tick rate (ticks/s) +host_mem_usage 308876 # Number of bytes of host memory used +host_seconds 267.56 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 10581824 # To system.physmem.bytesWrittenSys 7325760 # Total written bytes from the system interface side system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14983 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10312 # Per bank write bursts system.physmem.perBankRdBursts::1 10359 # Per bank write bursts system.physmem.perBankRdBursts::2 10206 # Per bank write bursts diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index ead89988f..5beee1623 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.022297 # Nu sim_ticks 22296591500 # Number of ticks simulated final_tick 22296591500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 221726 # Simulator instruction rate (inst/s) -host_op_rate 221726 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62113736 # Simulator tick rate (ticks/s) -host_mem_usage 308500 # Number of bytes of host memory used -host_seconds 358.96 # Real time elapsed on the host +host_inst_rate 210659 # Simulator instruction rate (inst/s) +host_op_rate 210659 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59013272 # Simulator tick rate (ticks/s) +host_mem_usage 309644 # Number of bytes of host memory used +host_seconds 377.82 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 10563200 # To system.physmem.bytesWrittenSys 7322432 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14730 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10292 # Per bank write bursts system.physmem.perBankRdBursts::1 10329 # Per bank write bursts system.physmem.perBankRdBursts::2 10209 # Per bank write bursts diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index c1732fe78..6fa7b21e8 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.056961 # Nu sim_ticks 56960656500 # Number of ticks simulated final_tick 56960656500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 199606 # Simulator instruction rate (inst/s) -host_op_rate 255266 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 160327771 # Simulator tick rate (ticks/s) -host_mem_usage 325784 # Number of bytes of host memory used -host_seconds 355.28 # Real time elapsed on the host +host_inst_rate 189048 # Simulator instruction rate (inst/s) +host_op_rate 241764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 151847358 # Simulator tick rate (ticks/s) +host_mem_usage 327812 # Number of bytes of host memory used +host_seconds 375.12 # Real time elapsed on the host sim_insts 70915128 # Number of instructions simulated sim_ops 90690084 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 8209792 # To system.physmem.bytesWrittenSys 5517504 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6908 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8061 # Per bank write bursts system.physmem.perBankRdBursts::1 8314 # Per bank write bursts system.physmem.perBankRdBursts::2 8233 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 5703 # Pe system.physmem.perBankWrBursts::15 5432 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 56960630500 # Total gap between requests +system.physmem.totGap 56960624500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -247,7 +247,7 @@ system.physmem.readRowHits 111810 # Nu system.physmem.writeRowHits 63793 # Number of row buffer hits during writes system.physmem.readRowHitRate 87.17 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes -system.physmem.avgGap 265564.34 # Average gap between requests +system.physmem.avgGap 265564.32 # Average gap between requests system.physmem.pageHitRate 81.87 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 153158040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 83568375 # Energy for precharge commands per rank (pJ) @@ -825,18 +825,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3333 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 98414 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 39288 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34000 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 42868 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38234 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107028 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 44911 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 53504 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 129109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473266 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 602375 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5388672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 132689 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477500 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 610189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5617792 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18490176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 23878848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24107968 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 96386 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 301829 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.037243 # Request fanout histogram diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index b6f1be7c5..56872871d 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,119 +1,119 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033788 # Number of seconds simulated -sim_ticks 33787619000 # Number of ticks simulated -final_tick 33787619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033784 # Number of seconds simulated +sim_ticks 33784139000 # Number of ticks simulated +final_tick 33784139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117892 # Simulator instruction rate (inst/s) -host_op_rate 150770 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56175899 # Simulator tick rate (ticks/s) -host_mem_usage 326928 # Number of bytes of host memory used -host_seconds 601.46 # Real time elapsed on the host +host_inst_rate 118438 # Simulator instruction rate (inst/s) +host_op_rate 151468 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56430150 # Simulator tick rate (ticks/s) +host_mem_usage 329476 # Number of bytes of host memory used +host_seconds 598.69 # Real time elapsed on the host sim_insts 70907630 # Number of instructions simulated sim_ops 90682585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 736896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2854400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6176576 # Number of bytes read from this memory -system.physmem.bytes_read::total 9767872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 736896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 736896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6229632 # Number of bytes written to this memory -system.physmem.bytes_written::total 6229632 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 11514 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 44600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96509 # Number of read requests responded to by this memory -system.physmem.num_reads::total 152623 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97338 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97338 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21809646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 84480650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 182805897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 289096192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21809646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21809646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 184376176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 184376176 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 184376176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21809646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 84480650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 182805897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 473472369 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 152624 # Number of read requests accepted -system.physmem.writeReqs 97338 # Number of write requests accepted -system.physmem.readBursts 152624 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97338 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9758080 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue -system.physmem.bytesWritten 6227712 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9767936 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6229632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 27837 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9027 # Per bank write bursts -system.physmem.perBankRdBursts::1 9355 # Per bank write bursts -system.physmem.perBankRdBursts::2 9548 # Per bank write bursts -system.physmem.perBankRdBursts::3 12185 # Per bank write bursts -system.physmem.perBankRdBursts::4 10599 # Per bank write bursts -system.physmem.perBankRdBursts::5 10432 # Per bank write bursts -system.physmem.perBankRdBursts::6 9787 # Per bank write bursts -system.physmem.perBankRdBursts::7 9285 # Per bank write bursts -system.physmem.perBankRdBursts::8 9499 # Per bank write bursts -system.physmem.perBankRdBursts::9 9569 # Per bank write bursts -system.physmem.perBankRdBursts::10 9134 # Per bank write bursts -system.physmem.perBankRdBursts::11 8776 # Per bank write bursts -system.physmem.perBankRdBursts::12 8706 # Per bank write bursts -system.physmem.perBankRdBursts::13 8772 # Per bank write bursts -system.physmem.perBankRdBursts::14 8686 # Per bank write bursts -system.physmem.perBankRdBursts::15 9110 # Per bank write bursts -system.physmem.perBankWrBursts::0 5979 # Per bank write bursts -system.physmem.perBankWrBursts::1 6226 # Per bank write bursts -system.physmem.perBankWrBursts::2 6146 # Per bank write bursts -system.physmem.perBankWrBursts::3 6158 # Per bank write bursts -system.physmem.perBankWrBursts::4 6081 # Per bank write bursts -system.physmem.perBankWrBursts::5 6325 # Per bank write bursts -system.physmem.perBankWrBursts::6 6021 # Per bank write bursts -system.physmem.perBankWrBursts::7 5966 # Per bank write bursts -system.physmem.perBankWrBursts::8 5954 # Per bank write bursts -system.physmem.perBankWrBursts::9 6102 # Per bank write bursts -system.physmem.perBankWrBursts::10 6248 # Per bank write bursts -system.physmem.perBankWrBursts::11 5872 # Per bank write bursts -system.physmem.perBankWrBursts::12 6030 # Per bank write bursts -system.physmem.perBankWrBursts::13 6061 # Per bank write bursts -system.physmem.perBankWrBursts::14 6151 # Per bank write bursts -system.physmem.perBankWrBursts::15 5988 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 781248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6167232 # Number of bytes read from this memory +system.physmem.bytes_read::total 9784768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 781248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 781248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6226432 # Number of bytes written to this memory +system.physmem.bytes_written::total 6226432 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 12207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 44317 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96363 # Number of read requests responded to by this memory +system.physmem.num_reads::total 152887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97288 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97288 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 23124698 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 83953242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 182548148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 289626088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 23124698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 23124698 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 184300449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 184300449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 184300449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 23124698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 83953242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 182548148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 473926537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 152888 # Number of read requests accepted +system.physmem.writeReqs 97288 # Number of write requests accepted +system.physmem.readBursts 152888 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97288 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9777152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 6224960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9784832 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6226432 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9124 # Per bank write bursts +system.physmem.perBankRdBursts::1 9348 # Per bank write bursts +system.physmem.perBankRdBursts::2 9757 # Per bank write bursts +system.physmem.perBankRdBursts::3 12566 # Per bank write bursts +system.physmem.perBankRdBursts::4 10929 # Per bank write bursts +system.physmem.perBankRdBursts::5 10090 # Per bank write bursts +system.physmem.perBankRdBursts::6 9786 # Per bank write bursts +system.physmem.perBankRdBursts::7 8974 # Per bank write bursts +system.physmem.perBankRdBursts::8 9178 # Per bank write bursts +system.physmem.perBankRdBursts::9 9832 # Per bank write bursts +system.physmem.perBankRdBursts::10 9165 # Per bank write bursts +system.physmem.perBankRdBursts::11 8819 # Per bank write bursts +system.physmem.perBankRdBursts::12 8693 # Per bank write bursts +system.physmem.perBankRdBursts::13 8672 # Per bank write bursts +system.physmem.perBankRdBursts::14 8813 # Per bank write bursts +system.physmem.perBankRdBursts::15 9022 # Per bank write bursts +system.physmem.perBankWrBursts::0 5950 # Per bank write bursts +system.physmem.perBankWrBursts::1 6192 # Per bank write bursts +system.physmem.perBankWrBursts::2 6162 # Per bank write bursts +system.physmem.perBankWrBursts::3 6171 # Per bank write bursts +system.physmem.perBankWrBursts::4 6089 # Per bank write bursts +system.physmem.perBankWrBursts::5 6262 # Per bank write bursts +system.physmem.perBankWrBursts::6 6013 # Per bank write bursts +system.physmem.perBankWrBursts::7 5971 # Per bank write bursts +system.physmem.perBankWrBursts::8 5978 # Per bank write bursts +system.physmem.perBankWrBursts::9 6080 # Per bank write bursts +system.physmem.perBankWrBursts::10 6215 # Per bank write bursts +system.physmem.perBankWrBursts::11 5915 # Per bank write bursts +system.physmem.perBankWrBursts::12 6050 # Per bank write bursts +system.physmem.perBankWrBursts::13 6057 # Per bank write bursts +system.physmem.perBankWrBursts::14 6142 # Per bank write bursts +system.physmem.perBankWrBursts::15 6018 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33787609500 # Total gap between requests +system.physmem.totGap 33784127500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152624 # Read request sizes (log2) +system.physmem.readPktSize::6 152888 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97338 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 49823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13781 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3645 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97288 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 50168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 54297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4371 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -148,34 +148,34 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 39 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see @@ -197,103 +197,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95484 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 167.396422 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 105.401782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 235.895158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 59753 62.58% 62.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22097 23.14% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4150 4.35% 90.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1579 1.65% 91.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 956 1.00% 92.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 842 0.88% 93.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 589 0.62% 94.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 882 0.92% 95.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4636 4.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95484 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5850 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.058462 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 198.495488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5849 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 95539 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 167.474225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 105.587098 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 235.887781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 59486 62.26% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22475 23.52% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4141 4.33% 90.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1560 1.63% 91.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 915 0.96% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 855 0.89% 93.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 603 0.63% 94.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 793 0.83% 95.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4711 4.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 95539 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5851 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.107332 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 198.473486 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5850 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5850 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5850 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.633846 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.583273 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.382653 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4554 77.85% 77.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.43% 78.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 781 13.35% 91.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 204 3.49% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 105 1.79% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 84 1.44% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 47 0.80% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 32 0.55% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5850 # Writes before turning the bus around for reads -system.physmem.totQLat 6712073801 # Total ticks spent queuing -system.physmem.totMemAccLat 9570886301 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 762350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44022.26 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5851 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5851 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.623654 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.576655 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.320793 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4551 77.78% 77.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 30 0.51% 78.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 752 12.85% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 225 3.85% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 138 2.36% 97.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 80 1.37% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 45 0.77% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.38% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 8 0.14% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5851 # Writes before turning the bus around for reads +system.physmem.totQLat 6694958033 # Total ticks spent queuing +system.physmem.totMemAccLat 9559358033 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 763840000 # Total ticks spent in databus transfers +system.physmem.avgQLat 43824.35 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 62772.26 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 288.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 184.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 289.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 184.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 62574.35 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 289.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 184.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 289.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 184.30 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.70 # Data bus utilization in percentage system.physmem.busUtilRead 2.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.44 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.45 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 121004 # Number of row buffer hits during reads -system.physmem.writeRowHits 33280 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.19 # Row buffer hit rate for writes -system.physmem.avgGap 135170.98 # Average gap between requests -system.physmem.pageHitRate 61.76 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 375641280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 204963000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 625404000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 316826640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15342350850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6812703000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25884530610 # Total energy per rank (pJ) -system.physmem_0.averagePower 766.158096 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11227638574 # Time in different power states -system.physmem_0.memoryStateTime::REF 1128140000 # Time in different power states +system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing +system.physmem.readRowHits 121417 # Number of row buffer hits during reads +system.physmem.writeRowHits 33065 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 33.99 # Row buffer hit rate for writes +system.physmem.avgGap 135041.44 # Average gap between requests +system.physmem.pageHitRate 61.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 374855040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 204534000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 627829800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 316068480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 15176758725 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6953261250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25859440575 # Total energy per rank (pJ) +system.physmem_0.averagePower 765.592889 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11461051997 # Time in different power states +system.physmem_0.memoryStateTime::REF 1127880000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21429077176 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21188094253 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 346043880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 188813625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563401800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313625520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2206641840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13705423425 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 8248614750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25572564840 # Total energy per rank (pJ) -system.physmem_1.averagePower 756.923807 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 13625050098 # Time in different power states -system.physmem_1.memoryStateTime::REF 1128140000 # Time in different power states +system.physmem_1.actEnergy 346777200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 189213750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562754400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 313787520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2206133280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13818315060 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 8144878500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25581859710 # Total energy per rank (pJ) +system.physmem_1.averagePower 757.374848 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 13453093141 # Time in different power states +system.physmem_1.memoryStateTime::REF 1127880000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 19031683152 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19196289859 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17216173 # Number of BP lookups -system.cpu.branchPred.condPredicted 11524251 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 650211 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9349330 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7678783 # Number of BTB hits +system.cpu.branchPred.lookups 17214384 # Number of BP lookups +system.cpu.branchPred.condPredicted 11522342 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 650449 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9351216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7679376 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.131907 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872954 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101563 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.121683 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1872997 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101556 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -412,129 +408,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 67575239 # number of cpu cycles simulated +system.cpu.numCycles 67568279 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5134859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88248834 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17216173 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9551737 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 60707500 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1326839 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5350 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5160872 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88245051 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17214384 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9552373 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60651743 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1327287 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6028 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 12635 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22778595 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 70008 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 66523790 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.678669 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300955 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 12780 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22780660 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69845 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 66495093 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.679326 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300807 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20715769 31.14% 31.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8270385 12.43% 43.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9211836 13.85% 57.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28325800 42.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20690371 31.12% 31.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8267529 12.43% 43.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9212157 13.85% 57.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28325036 42.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 66523790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 66495093 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.254770 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.305934 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8696241 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 20116868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31576119 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5641245 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 493317 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3182236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172097 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101426011 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3049995 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 493317 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13462916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5983097 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 839028 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32232549 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13512883 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99220100 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 979828 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3816376 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 66808 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4343458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5148151 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103925700 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457807646 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115438955 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 552 # Number of floating rename lookups +system.cpu.fetch.rate 1.306013 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8713541 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 20066003 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31587262 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5634718 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 493569 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3182821 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172049 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101434518 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3052676 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 493569 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13478922 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5884192 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 838725 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32239032 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13560653 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99228097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 981180 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3845119 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 69162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4384146 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5165586 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103939784 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457840373 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115445962 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10296474 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18669 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 10310558 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18670 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 18667 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12740509 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24326602 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22004719 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1418947 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2350394 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98183255 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94912265 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 694103 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7535192 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20267739 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 66523790 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.426742 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.152135 # Number of insts issued each cycle +system.cpu.rename.skidInsts 12730367 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24327975 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22005134 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1415958 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2369050 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98190630 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34517 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94916965 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 695759 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7542562 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20296667 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 66495093 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.427428 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151996 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18209770 27.37% 27.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17473699 26.27% 53.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17129113 25.75% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11665460 17.54% 96.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2044780 3.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 968 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18174968 27.33% 27.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17486428 26.30% 53.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17117325 25.74% 79.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11670567 17.55% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2044839 3.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 966 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 66523790 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 66495093 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6707680 22.40% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11186120 37.35% 59.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12052780 40.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6711532 22.43% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 41 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11180045 37.36% 59.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12034310 40.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49503200 52.16% 52.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89866 0.09% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49505832 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89861 0.09% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.25% # Type of FU issued @@ -555,89 +551,89 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.25% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 9 0.00% 52.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24070106 25.36% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21249051 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24073706 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21247526 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94912265 # Type of FU issued -system.cpu.iq.rate 1.404542 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29946621 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.315519 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 286988829 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105764420 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93479370 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 62 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124858764 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 122 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1365617 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94916965 # Type of FU issued +system.cpu.iq.rate 1.404756 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29925928 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315285 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286950501 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105779157 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93480434 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124842774 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1366701 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1460340 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2088 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11950 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1448981 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1461713 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2105 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11942 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1449396 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 137954 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 185768 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 140491 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185859 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 493317 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 628934 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 513918 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98227667 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 493569 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 630289 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 523749 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98235038 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24326602 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22004719 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1669 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 509191 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11950 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 303594 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221648 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 525242 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93991933 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23762441 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 920332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24327975 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22005134 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18597 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1652 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 519239 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11942 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303965 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221737 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 525702 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93996105 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23765772 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 920860 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9890 # number of nop insts executed -system.cpu.iew.exec_refs 44753885 # number of memory reference insts executed -system.cpu.iew.exec_branches 14253415 # Number of branches executed -system.cpu.iew.exec_stores 20991444 # Number of stores executed -system.cpu.iew.exec_rate 1.390923 # Inst execution rate -system.cpu.iew.wb_sent 93601796 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93479432 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44975266 # num instructions producing a value -system.cpu.iew.wb_consumers 76559860 # num instructions consuming a value -system.cpu.iew.wb_rate 1.383339 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587452 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6553334 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9891 # number of nop insts executed +system.cpu.iew.exec_refs 44755693 # number of memory reference insts executed +system.cpu.iew.exec_branches 14254152 # Number of branches executed +system.cpu.iew.exec_stores 20989921 # Number of stores executed +system.cpu.iew.exec_rate 1.391128 # Inst execution rate +system.cpu.iew.wb_sent 93602702 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93480493 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44980132 # num instructions producing a value +system.cpu.iew.wb_consumers 76556790 # num instructions consuming a value +system.cpu.iew.wb_rate 1.383497 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587539 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 6559945 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 480109 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 65462437 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.385346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.157754 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 480375 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 65432608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.385978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.157554 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 31857215 48.66% 48.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16813031 25.68% 74.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4347273 6.64% 80.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4157866 6.35% 87.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1935310 2.96% 90.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1259510 1.92% 92.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 744006 1.14% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 581672 0.89% 94.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3766554 5.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31819625 48.63% 48.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16816004 25.70% 74.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4349451 6.65% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4164400 6.36% 87.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1932309 2.95% 90.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1260445 1.93% 92.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 747040 1.14% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 580342 0.89% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3762992 5.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 65462437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 65432608 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913182 # Number of instructions committed system.cpu.commit.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -683,386 +679,386 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688137 # Class of committed instruction -system.cpu.commit.bw_lim_events 3766554 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 158912055 # The number of ROB reads -system.cpu.rob.rob_writes 195546008 # The number of ROB writes -system.cpu.timesIdled 28044 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1051449 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3762992 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 158892399 # The number of ROB reads +system.cpu.rob.rob_writes 195560325 # The number of ROB writes +system.cpu.timesIdled 28658 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1073186 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907630 # Number of Instructions Simulated system.cpu.committedOps 90682585 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.953004 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.953004 # CPI: Total CPI of All Threads -system.cpu.ipc 1.049314 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.049314 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102290506 # number of integer regfile reads -system.cpu.int_regfile_writes 56802248 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 24 # number of floating regfile writes -system.cpu.cc_regfile_reads 346154538 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804906 # number of cc regfile writes -system.cpu.misc_regfile_reads 44219892 # number of misc regfile reads +system.cpu.cpi 0.952906 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.952906 # CPI: Total CPI of All Threads +system.cpu.ipc 1.049422 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.049422 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102292430 # number of integer regfile reads +system.cpu.int_regfile_writes 56802415 # number of integer regfile writes +system.cpu.fp_regfile_reads 38 # number of floating regfile reads +system.cpu.fp_regfile_writes 22 # number of floating regfile writes +system.cpu.cc_regfile_reads 346166780 # number of cc regfile reads +system.cpu.cc_regfile_writes 38809001 # number of cc regfile writes +system.cpu.misc_regfile_reads 44218310 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485017 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.752563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40412566 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.234093 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 485025 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.752435 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40412261 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.232094 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 153371500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.752563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997564 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997564 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 510.752435 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997563 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997563 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 455 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84615901 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84615901 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21489624 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21489624 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18831353 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18831353 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60282 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60282 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15348 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15348 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84614979 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84614979 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21489272 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21489272 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831416 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831416 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60267 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60267 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15347 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15347 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40320977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40320977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40381259 # number of overall hits -system.cpu.dcache.overall_hits::total 40381259 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 564963 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 564963 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1018548 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1018548 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68572 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68572 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 577 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 577 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1583511 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1583511 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1652083 # number of overall misses -system.cpu.dcache.overall_misses::total 1652083 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9256149500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9256149500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14245975429 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14245975429 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5465000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 5465000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23502124929 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23502124929 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23502124929 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23502124929 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22054587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22054587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40320688 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40320688 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40380955 # number of overall hits +system.cpu.dcache.overall_hits::total 40380955 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 564863 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 564863 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018485 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018485 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68573 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68573 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 579 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 579 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1583348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1583348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1651921 # number of overall misses +system.cpu.dcache.overall_misses::total 1651921 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9285321000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9285321000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14250906929 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14250906929 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5341000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5341000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23536227929 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23536227929 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23536227929 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23536227929 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054135 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128854 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128854 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15925 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 15925 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128840 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41904488 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41904488 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42033342 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42033342 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025617 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025617 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051312 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051312 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532168 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532168 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037789 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037789 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039304 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039304 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16383.638398 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16383.638398 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13986.552847 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 13986.552847 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9471.403813 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9471.403813 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14841.781919 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14841.781919 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14225.753143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14225.753143 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 112 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2896869 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131288 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.466667 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.064995 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41904036 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904036 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42032876 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42032876 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025613 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025613 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051309 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532234 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.532234 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.036356 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.036356 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037785 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037785 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039301 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039301 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16438.182356 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16438.182356 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13992.260003 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13992.260003 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9224.525043 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9224.525043 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14864.848365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14864.848365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14247.792678 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14247.792678 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 81 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2899485 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131229 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.094849 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 485017 # number of writebacks -system.cpu.dcache.writebacks::total 485017 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265550 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 265550 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870019 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870019 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 577 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135569 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135569 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135569 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135569 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299413 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299413 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148529 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148529 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 485025 # number of writebacks +system.cpu.dcache.writebacks::total 485025 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 265446 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 265446 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 869952 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 869952 # number of WriteReq MSHR hits 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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1884857000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5931213971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5931213971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816070971 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7816070971 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 447950 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 447950 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485547 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485547 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3589129000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3589129000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2306203970 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2306203970 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1890576000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1890576000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5895332970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5895332970 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7785908970 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7785908970 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013576 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007483 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007483 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291780 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291780 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291812 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291812 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010690 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.010690 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011551 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12109.581080 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12109.581080 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15521.870954 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15521.870954 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50133.175519 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50133.175519 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13241.031140 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13241.031140 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16097.720206 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16097.720206 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11987.058183 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11987.058183 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15526.542721 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15526.542721 # average WriteReq mshr miss latency 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323617 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.354166 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 323129 # number of replacements +system.cpu.icache.tags.tagsinuse 510.280955 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22445799 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323641 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.354003 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 1133816500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.281102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996643 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996643 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 510.280955 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996642 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996642 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 341 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 335 # Occupied blocks per task id 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10621.157562 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10621.157562 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10621.157562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10621.157562 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10621.157562 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 261417 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45884745 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45884745 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22445799 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22445799 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22445799 # number of demand (read+write) hits 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system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055781 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.035582 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.107764 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.107764 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.069351 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.035582 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091859 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056284 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056284 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.037721 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037721 # mshr miss rate for ReadCleanReq accesses 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91619.328749 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91619.328749 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78895.981658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78895.981658 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69588.884064 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69588.884064 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76420.909867 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76420.909867 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75384.469393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69588.884064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76880.795964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91619.328749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86227.151487 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.208878 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91764.838551 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78696.723272 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78696.723272 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68924.680537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68924.680537 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76348.894451 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76348.894451 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75092.773109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68924.680537 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76791.897015 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91764.838551 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86189.202090 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 1617289 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 808162 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79873 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 67046 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56613 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10433 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 660594 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 350764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 474834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 78545 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 142478 # Transaction distribution +system.cpu.toL2Bus.snoop_filter.tot_requests 1617353 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 808194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 79842 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 67170 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10592 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 660621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 354016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 551426 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79011 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 142034 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148562 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 323628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 939793 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1406789 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2346582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39434560 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 58959360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 98393920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318372 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1127528 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.139590 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.372305 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 323652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336970 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 970420 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1456119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2426539 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41393152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62115968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103509120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318345 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1127532 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.139813 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.372899 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 980569 86.97% 86.97% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 136526 12.11% 99.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 10433 0.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 980480 86.96% 86.96% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 136460 12.10% 99.06% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 10592 0.94% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1127528 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1616766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1127532 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1616830500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 485882115 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 485918614 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728582930 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728566986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadResp 144336 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97338 # Transaction distribution -system.membus.trans_dist::CleanEvict 27827 # Transaction distribution +system.membus.trans_dist::ReadResp 144525 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97288 # Transaction distribution +system.membus.trans_dist::CleanEvict 27973 # Transaction distribution system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 8287 # Transaction distribution -system.membus.trans_dist::ReadExResp 8287 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 144337 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 430432 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 430432 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15997504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15997504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8362 # Transaction distribution +system.membus.trans_dist::ReadExResp 8362 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 144526 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431046 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16011200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16011200 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 277799 # Request fanout histogram +system.membus.snoop_fanout::samples 278159 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 277799 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 278159 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 277799 # Request fanout histogram -system.membus.reqLayer0.occupancy 747949896 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 278159 # Request fanout histogram +system.membus.reqLayer0.occupancy 748401121 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 797228853 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 798557507 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index ce3c1254b..5327d957c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.208729 # Nu sim_ticks 1208728699500 # Number of ticks simulated final_tick 1208728699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 339450 # Simulator instruction rate (inst/s) -host_op_rate 339450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 224654099 # Simulator tick rate (ticks/s) -host_mem_usage 299384 # Number of bytes of host memory used -host_seconds 5380.40 # Real time elapsed on the host +host_inst_rate 330067 # Simulator instruction rate (inst/s) +host_op_rate 330067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 218444071 # Simulator tick rate (ticks/s) +host_mem_usage 300788 # Number of bytes of host memory used +host_seconds 5533.36 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 125030976 # To system.physmem.bytesWrittenSys 65416576 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1301 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 897725 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 118310 # Per bank write bursts system.physmem.perBankRdBursts::1 113529 # Per bank write bursts system.physmem.perBankRdBursts::2 115745 # Per bank write bursts diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index a57e7be30..f994e016c 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.669525 # Nu sim_ticks 669525393000 # Number of ticks simulated final_tick 669525393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166227 # Simulator instruction rate (inst/s) -host_op_rate 166227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64107392 # Simulator tick rate (ticks/s) -host_mem_usage 299384 # Number of bytes of host memory used -host_seconds 10443.81 # Real time elapsed on the host +host_inst_rate 161577 # Simulator instruction rate (inst/s) +host_op_rate 161577 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 62314021 # Simulator tick rate (ticks/s) +host_mem_usage 300544 # Number of bytes of host memory used +host_seconds 10744.38 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 125551424 # To system.physmem.bytesWrittenSys 65555904 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1298 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 903686 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 118677 # Per bank write bursts system.physmem.perBankRdBursts::1 113900 # Per bank write bursts system.physmem.perBankRdBursts::2 116118 # Per bank write bursts diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 144dc4013..0ee27457c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.116861 # Nu sim_ticks 1116860578500 # Number of ticks simulated final_tick 1116860578500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237615 # Simulator instruction rate (inst/s) -host_op_rate 255994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171817202 # Simulator tick rate (ticks/s) -host_mem_usage 317996 # Number of bytes of host memory used -host_seconds 6500.28 # Real time elapsed on the host +host_inst_rate 228405 # Simulator instruction rate (inst/s) +host_op_rate 246072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 165157932 # Simulator tick rate (ticks/s) +host_mem_usage 318996 # Number of bytes of host memory used +host_seconds 6762.38 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -47,7 +47,7 @@ system.physmem.bytesReadSys 130981888 # To system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1309 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 962724 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 127279 # Per bank write bursts system.physmem.perBankRdBursts::1 124661 # Per bank write bursts system.physmem.perBankRdBursts::2 121601 # Per bank write bursts @@ -833,14 +833,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 system.cpu.toL2Bus.trans_dist::ReadResp 7335104 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4734689 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6498678 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6500272 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669721 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27671390 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27671315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27672984 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 826275328 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 67eb4b375..901b0011b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.767966 # Number of seconds simulated -sim_ticks 767965542000 # Number of ticks simulated -final_tick 767965542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.767875 # Number of seconds simulated +sim_ticks 767874998000 # Number of ticks simulated +final_tick 767874998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135762 # Simulator instruction rate (inst/s) -host_op_rate 146263 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67501614 # Simulator tick rate (ticks/s) -host_mem_usage 354608 # Number of bytes of host memory used -host_seconds 11377.00 # Real time elapsed on the host +host_inst_rate 133325 # Simulator instruction rate (inst/s) +host_op_rate 143638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66282190 # Simulator tick rate (ticks/s) +host_mem_usage 359880 # Number of bytes of host memory used +host_seconds 11584.94 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 65024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 235466816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63671744 # Number of bytes read from this memory -system.physmem.bytes_read::total 299203584 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104705856 # Number of bytes written to this memory -system.physmem.bytes_written::total 104705856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1016 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3679169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 994871 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4675056 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1636029 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1636029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 84670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 306611173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 82909637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 389605481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 84670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 84670 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 136341867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 136341867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 136341867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 84670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 306611173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 82909637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 525947348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4675056 # Number of read requests accepted -system.physmem.writeReqs 1636029 # Number of write requests accepted -system.physmem.readBursts 4675056 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1636029 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 298722176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 481408 # Total number of bytes read from write queue -system.physmem.bytesWritten 104702912 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299203584 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104705856 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7522 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3003359 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 301326 # Per bank write bursts -system.physmem.perBankRdBursts::1 298715 # Per bank write bursts -system.physmem.perBankRdBursts::2 284983 # Per bank write bursts -system.physmem.perBankRdBursts::3 287209 # Per bank write bursts -system.physmem.perBankRdBursts::4 287920 # Per bank write bursts -system.physmem.perBankRdBursts::5 285373 # Per bank write bursts -system.physmem.perBankRdBursts::6 281637 # Per bank write bursts -system.physmem.perBankRdBursts::7 277868 # Per bank write bursts -system.physmem.perBankRdBursts::8 293986 # Per bank write bursts -system.physmem.perBankRdBursts::9 298704 # Per bank write bursts -system.physmem.perBankRdBursts::10 291815 # Per bank write bursts -system.physmem.perBankRdBursts::11 297314 # Per bank write bursts -system.physmem.perBankRdBursts::12 299397 # Per bank write bursts -system.physmem.perBankRdBursts::13 298122 # Per bank write bursts -system.physmem.perBankRdBursts::14 294010 # Per bank write bursts -system.physmem.perBankRdBursts::15 289155 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 235361472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63663872 # Number of bytes read from this memory +system.physmem.bytes_read::total 299090176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104698048 # Number of bytes written to this memory +system.physmem.bytes_written::total 104698048 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3677523 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 994748 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4673284 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1635907 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1635907 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 84430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 306510139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82909161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 389503730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 84430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 84430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 136347776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 136347776 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 136347776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 84430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 306510139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82909161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 525851506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4673284 # Number of read requests accepted +system.physmem.writeReqs 1635907 # Number of write requests accepted +system.physmem.readBursts 4673284 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1635907 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 298596928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 493248 # Total number of bytes read from write queue +system.physmem.bytesWritten 104694592 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299090176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104698048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7707 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 24 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 300421 # Per bank write bursts +system.physmem.perBankRdBursts::1 298937 # Per bank write bursts +system.physmem.perBankRdBursts::2 284574 # Per bank write bursts +system.physmem.perBankRdBursts::3 288248 # Per bank write bursts +system.physmem.perBankRdBursts::4 288002 # Per bank write bursts +system.physmem.perBankRdBursts::5 284734 # Per bank write bursts +system.physmem.perBankRdBursts::6 280770 # Per bank write bursts +system.physmem.perBankRdBursts::7 278050 # Per bank write bursts +system.physmem.perBankRdBursts::8 293697 # Per bank write bursts +system.physmem.perBankRdBursts::9 299275 # Per bank write bursts +system.physmem.perBankRdBursts::10 291592 # Per bank write bursts +system.physmem.perBankRdBursts::11 297756 # Per bank write bursts +system.physmem.perBankRdBursts::12 299138 # Per bank write bursts +system.physmem.perBankRdBursts::13 298570 # Per bank write bursts +system.physmem.perBankRdBursts::14 293356 # Per bank write bursts +system.physmem.perBankRdBursts::15 288457 # Per bank write bursts system.physmem.perBankWrBursts::0 103823 # Per bank write bursts -system.physmem.perBankWrBursts::1 101759 # Per bank write bursts -system.physmem.perBankWrBursts::2 99255 # Per bank write bursts -system.physmem.perBankWrBursts::3 99822 # Per bank write bursts -system.physmem.perBankWrBursts::4 99277 # Per bank write bursts -system.physmem.perBankWrBursts::5 98671 # Per bank write bursts -system.physmem.perBankWrBursts::6 102768 # Per bank write bursts -system.physmem.perBankWrBursts::7 104279 # Per bank write bursts -system.physmem.perBankWrBursts::8 105369 # Per bank write bursts -system.physmem.perBankWrBursts::9 104220 # Per bank write bursts -system.physmem.perBankWrBursts::10 102032 # Per bank write bursts -system.physmem.perBankWrBursts::11 102651 # Per bank write bursts -system.physmem.perBankWrBursts::12 102828 # Per bank write bursts -system.physmem.perBankWrBursts::13 102619 # Per bank write bursts -system.physmem.perBankWrBursts::14 104194 # Per bank write bursts +system.physmem.perBankWrBursts::1 101786 # Per bank write bursts +system.physmem.perBankWrBursts::2 99158 # Per bank write bursts +system.physmem.perBankWrBursts::3 99952 # Per bank write bursts +system.physmem.perBankWrBursts::4 99094 # Per bank write bursts +system.physmem.perBankWrBursts::5 98779 # Per bank write bursts +system.physmem.perBankWrBursts::6 102513 # Per bank write bursts +system.physmem.perBankWrBursts::7 104359 # Per bank write bursts +system.physmem.perBankWrBursts::8 105182 # Per bank write bursts +system.physmem.perBankWrBursts::9 104512 # Per bank write bursts +system.physmem.perBankWrBursts::10 101930 # Per bank write bursts +system.physmem.perBankWrBursts::11 102694 # Per bank write bursts +system.physmem.perBankWrBursts::12 102904 # Per bank write bursts +system.physmem.perBankWrBursts::13 102694 # Per bank write bursts +system.physmem.perBankWrBursts::14 104057 # Per bank write bursts system.physmem.perBankWrBursts::15 102416 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 767965500500 # Total gap between requests +system.physmem.totGap 767874956500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4675056 # Read request sizes (log2) +system.physmem.readPktSize::6 4673284 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1636029 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2763524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1029428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 325669 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 231653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 149305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 81525 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 37575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18003 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 753 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1635907 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2762422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1028983 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 325435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 231330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 148884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 81578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 37725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18045 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1720 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,36 +148,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 28453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103836 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 106267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 107107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 109521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 111129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 111161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 101092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 100232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 25664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 28320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 100110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 107311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 108333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 109501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 111075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 103835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 101089 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 100454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -197,124 +197,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4246279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 95.006264 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.933304 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.667614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3382951 79.67% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 666013 15.68% 95.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94842 2.23% 97.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35210 0.83% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22787 0.54% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12374 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7276 0.17% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5157 0.12% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19669 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4246279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97783 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.733256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.725873 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 93691 95.82% 95.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1680 1.72% 97.53% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 798 0.82% 98.35% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 374 0.38% 98.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 374 0.38% 99.11% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 340 0.35% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 220 0.22% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 159 0.16% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 76 0.08% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 37 0.04% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 11 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1664-1791 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2431 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3712-3839 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97783 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97783 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.730751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.687620 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.251075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 68399 69.95% 69.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 2006 2.05% 72.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18369 18.79% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5745 5.88% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1950 1.99% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 718 0.73% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 317 0.32% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 149 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 75 0.08% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 10 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 4243203 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 95.043673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.954417 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.715127 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3379213 79.64% 79.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 666153 15.70% 95.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95338 2.25% 97.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35101 0.83% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 23158 0.55% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12215 0.29% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7169 0.17% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5140 0.12% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19716 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4243203 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 97801 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.704328 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.639805 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95408 97.55% 97.55% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1143 1.17% 98.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 693 0.71% 99.43% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 419 0.43% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 21 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 6 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 97801 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 97801 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.726342 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.683389 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.248647 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 68568 70.11% 70.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 2029 2.07% 72.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18244 18.65% 90.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5739 5.87% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1897 1.94% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 745 0.76% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 303 0.31% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 146 0.15% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 72 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 32 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 4 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97783 # Writes before turning the bus around for reads -system.physmem.totQLat 128413030932 # Total ticks spent queuing -system.physmem.totMemAccLat 215929293432 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23337670000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27511.96 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 97801 # Writes before turning the bus around for reads +system.physmem.totQLat 128464947947 # Total ticks spent queuing +system.physmem.totMemAccLat 215944516697 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23327885000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27534.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46261.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 388.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 46284.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 388.86 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 389.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 136.34 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 389.50 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 136.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.10 # Data bus utilization in percentage system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.89 # Average write queue length when enqueuing -system.physmem.readRowHits 1709654 # Number of row buffer hits during reads -system.physmem.writeRowHits 347571 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.63 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing +system.physmem.readRowHits 1710553 # Number of row buffer hits during reads +system.physmem.writeRowHits 347662 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes -system.physmem.avgGap 121685.18 # Average gap between requests -system.physmem.pageHitRate 32.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15953799960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8704950375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 17977486800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5246246880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 414403163865 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 97263315750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 609708236430 # Total energy per rank (pJ) -system.physmem_0.averagePower 793.934243 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 159282861364 # Time in different power states -system.physmem_0.memoryStateTime::REF 25643800000 # Time in different power states +system.physmem.avgGap 121707.36 # Average gap between requests +system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 15942837960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8698969125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 17968828800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5245261920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 415022318100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 96668804250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 609700698795 # Total energy per rank (pJ) +system.physmem_0.averagePower 794.012990 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 158294269639 # Time in different power states +system.physmem_0.memoryStateTime::REF 25640940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 583033093643 # Time in different power states +system.physmem_0.memoryStateTime::ACT 583937331861 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16147600560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8810694750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18427445400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5354300880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 50159272800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 410341742010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100825962000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 610067018400 # Total energy per rank (pJ) -system.physmem_1.averagePower 794.401440 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165241048217 # Time in different power states -system.physmem_1.memoryStateTime::REF 25643800000 # Time in different power states +system.physmem_1.actEnergy 16135663320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8804181375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18422297400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5354961840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 410145276690 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 100946910750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 609962970015 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.354545 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165441923935 # Time in different power states +system.physmem_1.memoryStateTime::REF 25640940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 577073869783 # Time in different power states +system.physmem_1.memoryStateTime::ACT 576789598565 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286290965 # Number of BP lookups -system.cpu.branchPred.condPredicted 223414875 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630075 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 157650249 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150360830 # Number of BTB hits +system.cpu.branchPred.lookups 286279645 # Number of BP lookups +system.cpu.branchPred.condPredicted 223407155 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157715633 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150347717 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.376208 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16641594 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.328354 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16640366 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -433,128 +425,128 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1535931085 # number of cpu cycles simulated +system.cpu.numCycles 1535749997 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13926236 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067547876 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286290965 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167002424 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1507284638 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29284969 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 196 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 917 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656963855 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 927 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1535854471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.442200 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13928863 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067540877 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286279645 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166988083 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1507099451 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29287501 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 190 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 976 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656956376 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 928 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1535673230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.442364 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228170 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 453416615 29.52% 29.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465436740 30.30% 59.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101431033 6.60% 66.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515570083 33.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 453232887 29.51% 29.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465446694 30.31% 59.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101428513 6.60% 66.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515565136 33.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1535854471 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.186396 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.346120 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74705927 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 538395080 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849912555 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58199125 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14641784 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42202960 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 1535673230 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.186410 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.346274 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74702692 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 538196786 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849939330 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58191372 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643050 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42203099 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037254051 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52495885 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14641784 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139801946 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 457449218 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13751 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837842602 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86105170 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976447004 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26743472 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45311241 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126368 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1599527 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 25035305 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985923292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128451044 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432959840 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 125 # Number of floating rename lookups +system.cpu.decode.DecodedInsts 2037258767 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52502216 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643050 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139798596 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 457232788 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14060 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837861639 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86123097 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976450357 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26748217 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45311443 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 127280 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1601349 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25060230 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985922281 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9128467759 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432961586 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311024347 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 154 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 145 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111506310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542573483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199309856 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26973622 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29535518 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948030100 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 311023336 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 153 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111484275 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542573994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199309930 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26884095 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29108781 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1948029821 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857442950 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13480165 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283997895 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647563158 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1857521274 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13507542 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283997616 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647442130 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1535854471 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.209387 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150580 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 1535673230 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.209581 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150633 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 582872858 37.95% 37.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 326140941 21.24% 59.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378202799 24.62% 83.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219661262 14.30% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28970430 1.89% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6181 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 582693827 37.94% 37.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326116884 21.24% 59.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378188392 24.63% 83.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219675077 14.30% 98.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28992875 1.89% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6175 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1535854471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1535673230 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166043738 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1958 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191460391 47.30% 88.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47270881 11.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166036820 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1982 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191468502 47.25% 88.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47685170 11.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138255914 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800916 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138261186 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800987 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -576,88 +568,88 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532080715 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186305355 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532140310 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186318740 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857442950 # Type of FU issued -system.cpu.iq.rate 1.209327 # Inst issue rate -system.cpu.iq.fu_busy_cnt 404776968 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.217922 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5668997271 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232041055 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805706922 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 233 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 216 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262219787 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 131 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17802666 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857521274 # Type of FU issued +system.cpu.iq.rate 1.209521 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405192474 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218136 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5669415557 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2232040499 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805727122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262713615 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17816594 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84267149 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66494 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13286 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24462811 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84267660 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66369 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13310 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24462885 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4478194 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4870766 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4528039 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4867222 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14641784 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25370881 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1332488 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948030384 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643050 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25368203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1322817 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1948030107 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542573483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199309856 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 542573994 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199309930 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159276 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1171811 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13286 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7699902 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704078 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16403980 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827785519 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516901938 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29657431 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 159427 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1161958 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13310 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700527 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8706121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16406648 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827850066 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516960251 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29671208 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 73 # number of nop insts executed -system.cpu.iew.exec_refs 698651224 # number of memory reference insts executed -system.cpu.iew.exec_branches 229542579 # Number of branches executed -system.cpu.iew.exec_stores 181749286 # Number of stores executed -system.cpu.iew.exec_rate 1.190018 # Inst execution rate -system.cpu.iew.wb_sent 1808742163 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805706990 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169201528 # num instructions producing a value -system.cpu.iew.wb_consumers 1689618558 # num instructions consuming a value -system.cpu.iew.wb_rate 1.175643 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691991 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258099025 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 75 # number of nop insts executed +system.cpu.iew.exec_refs 698714373 # number of memory reference insts executed +system.cpu.iew.exec_branches 229541828 # Number of branches executed +system.cpu.iew.exec_stores 181754122 # Number of stores executed +system.cpu.iew.exec_rate 1.190200 # Inst execution rate +system.cpu.iew.wb_sent 1808757098 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805727191 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169214999 # num instructions producing a value +system.cpu.iew.wb_consumers 1689608003 # num instructions consuming a value +system.cpu.iew.wb_rate 1.175795 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692004 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 258092940 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14629375 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1496362804 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.112051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.027734 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14630610 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1496181220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.112186 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.028021 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 916038990 61.22% 61.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250656359 16.75% 77.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110050903 7.35% 85.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55261193 3.69% 89.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29363802 1.96% 90.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34102831 2.28% 93.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24718362 1.65% 94.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18151757 1.21% 96.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58018607 3.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 915888142 61.22% 61.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250644385 16.75% 77.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110066561 7.36% 85.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55290971 3.70% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29288855 1.96% 90.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34073264 2.28% 93.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24725039 1.65% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18121984 1.21% 96.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58082019 3.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1496362804 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1496181220 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -703,76 +695,76 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58018607 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3360475057 # The number of ROB reads -system.cpu.rob.rob_writes 3883759706 # The number of ROB writes -system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 76614 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58082019 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3360223976 # The number of ROB reads +system.cpu.rob.rob_writes 3883747904 # The number of ROB writes +system.cpu.timesIdled 828 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 76767 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.994411 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.994411 # CPI: Total CPI of All Threads -system.cpu.ipc 1.005620 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.005620 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175771978 # number of integer regfile reads -system.cpu.int_regfile_writes 1261585669 # number of integer regfile writes +system.cpu.cpi 0.994294 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.994294 # CPI: Total CPI of All Threads +system.cpu.ipc 1.005739 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.005739 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175836503 # number of integer regfile reads +system.cpu.int_regfile_writes 1261593461 # number of integer regfile writes system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 50 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965626191 # number of cc regfile reads -system.cpu.cc_regfile_writes 551852831 # number of cc regfile writes -system.cpu.misc_regfile_reads 675841321 # number of misc regfile reads +system.cpu.fp_regfile_writes 51 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965846001 # number of cc regfile reads +system.cpu.cc_regfile_writes 551857157 # number of cc regfile writes +system.cpu.misc_regfile_reads 675854889 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17004065 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.964813 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638072070 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17004577 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.523549 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 17003582 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964809 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638071493 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17004094 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.524580 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.964813 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964809 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 416 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335720557 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335720557 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469353506 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469353506 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168718419 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168718419 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335716396 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335716396 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469352988 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469352988 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168718360 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168718360 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638071925 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638071925 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638071925 # number of overall hits -system.cpu.dcache.overall_hits::total 638071925 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17418313 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17418313 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3867628 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3867628 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638071348 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638071348 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638071348 # number of overall hits +system.cpu.dcache.overall_hits::total 638071348 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17416992 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17416992 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3867687 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3867687 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21285941 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21285941 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21285943 # number of overall misses -system.cpu.dcache.overall_misses::total 21285943 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 412331077000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 412331077000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 148962559255 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 148962559255 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 21284679 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21284679 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21284681 # number of overall misses +system.cpu.dcache.overall_misses::total 21284681 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 412160487500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 412160487500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148823410876 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148823410876 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 561293636255 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 561293636255 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 561293636255 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 561293636255 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486771819 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486771819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 560983898376 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 560983898376 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 560983898376 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 560983898376 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486769980 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486769980 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -781,470 +773,469 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659357866 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659357866 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659357868 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659357868 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659356027 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659356027 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659356029 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659356029 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035781 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035781 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032283 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032283 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032283 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032283 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23672.273945 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23672.273945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.224126 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.224126 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.032281 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032281 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032281 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032281 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23664.274951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23664.274951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38478.659435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38478.659435 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26369.218831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26369.218831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26369.216353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26369.216353 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 20544187 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3409553 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 942936 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67231 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.787467 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50.714001 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26356.230149 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26356.230149 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26356.227673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26356.227673 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20486404 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3408907 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 942205 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67188 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.743043 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 50.736843 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 17004065 # number of writebacks -system.cpu.dcache.writebacks::total 17004065 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151291 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151291 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130068 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1130068 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 17003582 # number of writebacks +system.cpu.dcache.writebacks::total 17003582 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150438 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3150438 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130143 # number of WriteReq MSHR hits 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-system.cpu.dcache.demand_mshr_misses::total 17004582 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17004583 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17004583 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331931922000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 331931922000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115721294597 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 115721294597 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17004098 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17004098 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17004099 # number of overall MSHR misses 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# number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 447653284597 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447460105794 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 447460105794 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447460173794 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 447460173794 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025790 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025790 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025790 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23265.676747 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23265.676747 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42271.692528 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42271.692528 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23259.655415 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23259.655415 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42236.755206 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42236.755206 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26325.446671 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26325.446671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26325.449121 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26325.449121 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26314.839270 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26314.839270 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26314.841721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26314.841721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 587 # number of replacements -system.cpu.icache.tags.tagsinuse 444.617750 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656962266 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 612266.790308 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 590 # number of replacements +system.cpu.icache.tags.tagsinuse 444.554720 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656954786 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610552.775093 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 444.617750 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.868394 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.868394 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 444.554720 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.868271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.868271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 440 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313928777 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313928777 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656962266 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656962266 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656962266 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656962266 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656962266 # number of overall hits -system.cpu.icache.overall_hits::total 656962266 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1586 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1586 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1586 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1586 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1586 # number of overall misses -system.cpu.icache.overall_misses::total 1586 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 98890487 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 98890487 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 98890487 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 98890487 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 98890487 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 98890487 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656963852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656963852 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656963852 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656963852 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656963852 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656963852 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313913824 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313913824 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656954786 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656954786 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656954786 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656954786 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656954786 # number of overall hits +system.cpu.icache.overall_hits::total 656954786 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1588 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1588 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1588 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1588 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1588 # number of overall misses +system.cpu.icache.overall_misses::total 1588 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 98682987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 98682987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 98682987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 98682987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 98682987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 98682987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656956374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656956374 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656956374 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656956374 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656956374 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656956374 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62352.135561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62352.135561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62352.135561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62352.135561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62352.135561 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17132 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 145 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62142.938917 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62142.938917 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62142.938917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62142.938917 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17933 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 176 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.309278 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 29 # average number of cycles each access was blocked +system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.438144 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 587 # number of writebacks -system.cpu.icache.writebacks::total 587 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 511 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 511 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 511 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 511 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73172990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73172990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73172990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73172990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73172990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73172990 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 590 # number of writebacks +system.cpu.icache.writebacks::total 590 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 510 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 510 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 510 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 510 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 510 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 510 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74485990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74485990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74485990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74485990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74485990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74485990 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68067.897674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68067.897674 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68067.897674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68067.897674 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69096.465677 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69096.465677 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 11609988 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11638125 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 19145 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 11607933 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11636199 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 19107 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4657211 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4708196 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16099.895635 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 22828795 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4724118 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.832393 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 54830616500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 13098.409047 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 2.246929 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.239659 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.799463 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183059 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.982660 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 830 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15092 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 625 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 476 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2900 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4269 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5555 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1892 # Occupied blocks per task id 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57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520085 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 11520085 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13277197 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13277254 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13277197 # number of overall hits -system.cpu.l2cache.overall_hits::total 13277254 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 980492 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 980492 # number of ReadExReq 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miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65516000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 308096362500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72325395404 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 380487273904 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49046 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49047 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1143496 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975623 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 975623 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1014 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700666 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700666 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3676289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3677303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3676289 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4820799 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72430896209 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92751563000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92751563000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66801500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66801500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215184233000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215184233000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66801500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307935796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 308002597500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66801500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307935796000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 380433493709 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189341 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216333 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216287 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356382 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.940631 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189301 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189301 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216246 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.283659 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63170.642694 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95071.999541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95071.999541 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64420.845624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64420.845624 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79684.970805 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79684.970805 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83765.134633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64420.845624 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83770.483702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63170.642694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78877.066841 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.283490 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63341.626214 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95069.061512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95069.061512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65879.191321 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65879.191321 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79678.210116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79678.210116 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83757.742427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78915.029170 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 34010311 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004668 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2921208 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2902417 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18791 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 14268046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6464245 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12155140 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 5774511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1435676 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266973 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2731 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50991946 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50994677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 105984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2175190848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2175296832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 8846223 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25851874 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.114549 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.320751 # Request fanout histogram +system.cpu.toL2Bus.snoop_filter.tot_requests 34009349 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004186 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2918754 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899783 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18971 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 14267592 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6465120 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12174959 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 5771526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1434255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737578 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266516 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51014533 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176491840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176598464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 8841697 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25846865 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.114483 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.320694 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22909361 88.62% 88.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2923722 11.31% 99.93% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 18791 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22906816 88.63% 88.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2921078 11.30% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 18971 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25851874 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34009808017 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25846865 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34008846525 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 10525 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 13536 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1615497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25506872492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25506147987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3698381 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1636029 # Transaction distribution -system.membus.trans_dist::CleanEvict 3003353 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 976674 # Transaction distribution -system.membus.trans_dist::ReadExResp 976674 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3698382 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13989505 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13989505 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403909376 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 403909376 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3697520 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1635907 # Transaction distribution +system.membus.trans_dist::CleanEvict 3001520 # Transaction distribution +system.membus.trans_dist::UpgradeReq 5 # Transaction distribution +system.membus.trans_dist::ReadExReq 975763 # Transaction distribution +system.membus.trans_dist::ReadExResp 975763 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3697521 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983999 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13983999 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403788160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 403788160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 9314444 # Request fanout histogram +system.membus.snoop_fanout::samples 9310716 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 9314444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 9310716 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 9314444 # Request fanout histogram -system.membus.reqLayer0.occupancy 17663480706 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 9310716 # Request fanout histogram +system.membus.reqLayer0.occupancy 17657125833 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 25423271236 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25413031627 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 02c08f292..232fe8b45 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.377030 # Nu sim_ticks 2377029670500 # Number of ticks simulated final_tick 2377029670500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 970948 # Simulator instruction rate (inst/s) -host_op_rate 1046333 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1499891883 # Simulator tick rate (ticks/s) -host_mem_usage 316204 # Number of bytes of host memory used -host_seconds 1584.80 # Real time elapsed on the host +host_inst_rate 872363 # Simulator instruction rate (inst/s) +host_op_rate 940093 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1347600333 # Simulator tick rate (ticks/s) +host_mem_usage 317216 # Number of bytes of host memory used +host_seconds 1763.90 # Real time elapsed on the host sim_insts 1538759602 # Number of instructions simulated sim_ops 1658228915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -606,14 +606,14 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 4702506 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6326510 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6327661 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 638 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1283 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27340461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27341744 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27341612 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27342895 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 818983360 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 819024640 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index 717d8e764..fae4160aa 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.130773 # Nu sim_ticks 130772642500 # Number of ticks simulated final_tick 130772642500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246902 # Simulator instruction rate (inst/s) -host_op_rate 260275 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 187375043 # Simulator tick rate (ticks/s) -host_mem_usage 321308 # Number of bytes of host memory used -host_seconds 697.92 # Real time elapsed on the host +host_inst_rate 239563 # Simulator instruction rate (inst/s) +host_op_rate 252538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 181805529 # Simulator tick rate (ticks/s) +host_mem_usage 322304 # Number of bytes of host memory used +host_seconds 719.30 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -795,18 +795,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 5396 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2566 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 20 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 4685 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3656 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15591 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 464000 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12257 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15919 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 484608 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 580864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 601472 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 6495 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.071132 # Request fanout histogram diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index b0b3ea10a..403ef08b8 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.085490 # Nu sim_ticks 85490431000 # Number of ticks simulated final_tick 85490431000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129805 # Simulator instruction rate (inst/s) -host_op_rate 136836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64404554 # Simulator tick rate (ticks/s) -host_mem_usage 317332 # Number of bytes of host memory used -host_seconds 1327.40 # Real time elapsed on the host +host_inst_rate 128362 # Simulator instruction rate (inst/s) +host_op_rate 135315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63688458 # Simulator tick rate (ticks/s) +host_mem_usage 319620 # Number of bytes of host memory used +host_seconds 1342.32 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1118,19 +1118,19 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3419 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8522 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 119639 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 64840 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 51941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 62415 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 11001 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 2383 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 8640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 8640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 54914 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 64726 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 155926 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 217414 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 373340 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6464768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9219072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 15683840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 164228 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 219586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 383814 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6996096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9358080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16354176 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 13384 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 141664 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.218517 # Request fanout histogram diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 0223e3f8f..4de03aa93 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.079230 # Number of seconds simulated -sim_ticks 79229645000 # Number of ticks simulated -final_tick 79229645000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.079141 # Number of seconds simulated +sim_ticks 79140979500 # Number of ticks simulated +final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90742 # Simulator instruction rate (inst/s) -host_op_rate 152092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54436376 # Simulator tick rate (ticks/s) -host_mem_usage 350016 # Number of bytes of host memory used -host_seconds 1455.45 # Real time elapsed on the host +host_inst_rate 91812 # Simulator instruction rate (inst/s) +host_op_rate 153885 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55016334 # Simulator tick rate (ticks/s) +host_mem_usage 351180 # Number of bytes of host memory used +host_seconds 1438.50 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 220992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 124928 # Number of bytes read from this memory -system.physmem.bytes_read::total 345920 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1952 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5405 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2789259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1576784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4366043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2789259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2789259 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2789259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1576784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4366043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5405 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125056 # Number of bytes read from this memory +system.physmem.bytes_read::total 346432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1954 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5413 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2797236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1580167 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4377403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2797236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2797236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2797236 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1580167 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4377403 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5413 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5405 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5413 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 345920 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 346432 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 345920 # Total read bytes from the system interface side +system.physmem.bytesReadSys 346432 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 261 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 347 # Per bank write bursts -system.physmem.perBankRdBursts::2 460 # Per bank write bursts -system.physmem.perBankRdBursts::3 350 # Per bank write bursts -system.physmem.perBankRdBursts::4 341 # Per bank write bursts -system.physmem.perBankRdBursts::5 328 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 298 # Per bank write bursts +system.physmem.perBankRdBursts::1 346 # Per bank write bursts +system.physmem.perBankRdBursts::2 461 # Per bank write bursts +system.physmem.perBankRdBursts::3 349 # Per bank write bursts +system.physmem.perBankRdBursts::4 340 # Per bank write bursts +system.physmem.perBankRdBursts::5 326 # Per bank write bursts system.physmem.perBankRdBursts::6 402 # Per bank write bursts -system.physmem.perBankRdBursts::7 383 # Per bank write bursts -system.physmem.perBankRdBursts::8 339 # Per bank write bursts +system.physmem.perBankRdBursts::7 384 # Per bank write bursts +system.physmem.perBankRdBursts::8 341 # Per bank write bursts system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 240 # Per bank write bursts -system.physmem.perBankRdBursts::11 284 # Per bank write bursts -system.physmem.perBankRdBursts::12 217 # Per bank write bursts -system.physmem.perBankRdBursts::13 468 # Per bank write bursts -system.physmem.perBankRdBursts::14 388 # Per bank write bursts -system.physmem.perBankRdBursts::15 282 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 285 # Per bank write bursts +system.physmem.perBankRdBursts::12 220 # Per bank write bursts +system.physmem.perBankRdBursts::13 466 # Per bank write bursts +system.physmem.perBankRdBursts::14 389 # Per bank write bursts +system.physmem.perBankRdBursts::15 286 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 79229612500 # Total gap between requests +system.physmem.totGap 79140890500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5405 # Read request sizes (log2) +system.physmem.readPktSize::6 5413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 904 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,311 +186,311 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1099 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 313.361237 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 181.828976 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.670559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 436 39.67% 39.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 230 20.93% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 99 9.01% 69.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 58 5.28% 74.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 55 5.00% 79.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 56 5.10% 84.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 2.09% 87.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.64% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 124 11.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1099 # Bytes accessed per row activation -system.physmem.totQLat 41940250 # Total ticks spent queuing -system.physmem.totMemAccLat 143284000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27025000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7759.53 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1107 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.790425 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.924163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.273428 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 441 39.84% 39.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 229 20.69% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 106 9.58% 70.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 59 5.33% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 51 4.61% 80.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 54 4.88% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 23 2.08% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.63% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1107 # Bytes accessed per row activation +system.physmem.totQLat 40702000 # Total ticks spent queuing +system.physmem.totMemAccLat 142195750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27065000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7519.31 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26509.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26269.31 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.37 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4297 # Number of row buffer hits during reads +system.physmem.readRowHits 4302 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.50 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 14658577.71 # Average gap between requests -system.physmem.pageHitRate 79.50 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22526400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 14620522.91 # Average gap between requests +system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4898880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2673000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22659000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2444474070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 45390936750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 53040118785 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.484152 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 75508317500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2645500000 # Time in different power states +system.physmem_0.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2477527515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.541483 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1071550000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3386880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1848000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19312800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19406400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5174598000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2297025045 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 45520269750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 53016440475 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.185395 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 75726888000 # Time in different power states -system.physmem_1.memoryStateTime::REF 2645500000 # Time in different power states +system.physmem_1.refreshEnergy 5169003840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2315256210 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 45452899500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 52961929365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.220665 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 75612477000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2642640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 855243500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20592907 # Number of BP lookups -system.cpu.branchPred.condPredicted 20592907 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1327799 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12698364 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12013605 # Number of BTB hits +system.cpu.branchPred.lookups 20604097 # Number of BP lookups +system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.607502 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1441126 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16761 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 158459291 # number of cpu cycles simulated +system.cpu.numCycles 158281960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 25251668 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 227436303 # Number of instructions fetch has processed -system.cpu.fetch.Branches 20592907 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13454731 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 131379126 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3193881 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 2041 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 21671 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 227540230 # Number of instructions fetch has processed +system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24259483 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 266288 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 158251507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.376692 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 95931722 60.62% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4757646 3.01% 63.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3806394 2.41% 66.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4363208 2.76% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4227713 2.67% 71.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4814821 3.04% 74.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4714702 2.98% 77.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3700525 2.34% 79.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 31934776 20.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 95737540 60.56% 60.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 158251507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.129957 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.435298 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15405673 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96363491 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 23242332 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21643071 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1596940 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 336546765 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1596940 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 23300664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31883477 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 30445 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35976653 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 65463328 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328193711 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1319 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 57856617 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7708627 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 165863 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 380358715 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 909771649 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 600461611 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4182617 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 158076676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 23286260 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21616249 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 380441374 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 910027756 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 600617832 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 120929265 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2085 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2059 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 121166066 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 82747977 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 29791267 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 59612118 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20405352 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 317780620 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4165 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 259339471 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 71881 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 96421401 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 197095861 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2920 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 158251507 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.638780 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.522654 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 121011924 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 82787392 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 259397690 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40084558 25.33% 25.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 47634072 30.10% 55.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33122012 20.93% 76.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18013851 11.38% 87.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10936157 6.91% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4740478 3.00% 97.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2457312 1.55% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 875604 0.55% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 387463 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40037946 25.33% 25.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 47502915 30.05% 55.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 158251507 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 234483 7.38% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2555698 80.47% 87.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 385880 12.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2560752 80.62% 87.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 383461 12.07% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1212784 0.47% 0.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 161792342 62.39% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 789140 0.30% 63.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7038106 2.71% 65.87% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1186493 0.46% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 64866325 25.01% 91.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22454281 8.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 161810980 62.38% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 259339471 # Type of FU issued -system.cpu.iq.rate 1.636632 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3176061 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012247 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 675323210 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410805836 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 253605894 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4855181 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 3696441 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2340510 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 258858304 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2444444 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18689568 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 259397690 # Type of FU issued +system.cpu.iq.rate 1.638833 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 675268343 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 258916834 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26098390 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12338 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 302582 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 9275550 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26137805 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50123 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1596940 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12493200 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 494306 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 317784785 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 94743 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 82747977 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 29791267 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1931 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 389039 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 63652 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 302582 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 551479 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 825731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1377210 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 257282682 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 64058012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2056789 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 82787392 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 303242 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 257339860 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2057830 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 86333641 # number of memory reference insts executed -system.cpu.iew.exec_branches 14326229 # Number of branches executed -system.cpu.iew.exec_stores 22275629 # Number of stores executed -system.cpu.iew.exec_rate 1.623652 # Inst execution rate -system.cpu.iew.wb_sent 256637538 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 255946404 # cumulative count of insts written-back -system.cpu.iew.wb_producers 204333247 # num instructions producing a value -system.cpu.iew.wb_consumers 369622334 # num instructions consuming a value -system.cpu.iew.wb_rate 1.615219 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.552816 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 96429188 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 86369701 # number of memory reference insts executed +system.cpu.iew.exec_branches 14330688 # Number of branches executed +system.cpu.iew.exec_stores 22285011 # Number of stores executed +system.cpu.iew.exec_rate 1.625832 # Inst execution rate +system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back +system.cpu.iew.wb_producers 204396158 # num instructions producing a value +system.cpu.iew.wb_consumers 369708067 # num instructions consuming a value +system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1329692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 145106129 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.525527 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.953873 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 45566766 31.40% 31.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57414676 39.57% 70.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14193363 9.78% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 12012309 8.28% 89.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4072580 2.81% 91.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2869750 1.98% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 928162 0.64% 94.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1071171 0.74% 95.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6977352 4.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 145106129 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -536,91 +536,91 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6977352 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 455921349 # The number of ROB reads -system.cpu.rob.rob_writes 648768029 # The number of ROB writes -system.cpu.timesIdled 2647 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 207784 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 455771992 # The number of ROB reads +system.cpu.rob.rob_writes 648913303 # The number of ROB writes +system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.199802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.199802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.833471 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.833471 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 448461429 # number of integer regfile reads -system.cpu.int_regfile_writes 232562681 # number of integer regfile writes -system.cpu.fp_regfile_reads 3213153 # number of floating regfile reads -system.cpu.fp_regfile_writes 1998427 # number of floating regfile writes -system.cpu.cc_regfile_reads 102530427 # number of cc regfile reads -system.cpu.cc_regfile_writes 59507422 # number of cc regfile writes -system.cpu.misc_regfile_reads 132428508 # number of misc regfile reads +system.cpu.cpi 1.198459 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads +system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 448575218 # number of integer regfile reads +system.cpu.int_regfile_writes 232602901 # number of integer regfile writes +system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads +system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes +system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads +system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes +system.cpu.misc_regfile_reads 132474844 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes system.cpu.dcache.tags.replacements 51 # number of replacements -system.cpu.dcache.tags.tagsinuse 1429.692139 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 65755137 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1993 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32993.044155 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1429.692139 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.349046 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.349046 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1942 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.348905 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1944 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.474121 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 131517093 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 131517093 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 45240855 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 45240855 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513928 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513928 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 65754783 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 65754783 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 65754783 # number of overall hits -system.cpu.dcache.overall_hits::total 65754783 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 964 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 964 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1803 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1803 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2767 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2767 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2767 # number of overall misses -system.cpu.dcache.overall_misses::total 2767 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65032500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65032500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 127862500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 127862500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 192895000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 192895000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 192895000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 192895000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 45241819 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 45241819 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits +system.cpu.dcache.overall_hits::total 65746939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses +system.cpu.dcache.overall_misses::total 2800 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 65757550 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 65757550 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 65757550 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 65757550 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000088 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000088 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67461.099585 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 67461.099585 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70916.528009 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70916.528009 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69712.685219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69712.685219 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69712.685219 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -631,250 +631,252 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 10 # number of writebacks system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 526 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 526 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 513 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 513 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 513 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 513 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 453 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1801 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1801 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2254 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2254 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2254 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2254 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36207500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36207500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125915500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125915500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 162123000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162123000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 162123000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 528 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 528 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 528 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses 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+system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000034 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000034 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79928.256071 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79928.256071 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69914.214325 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69914.214325 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71926.796806 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71926.796806 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency 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of references to valid blocks. +system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1637.723048 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.799669 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.799669 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1975 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 869 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 792 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.964355 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 48526174 # Number of tag accesses -system.cpu.icache.tags.data_accesses 48526174 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 24250086 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 24250086 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 24250086 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 24250086 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 24250086 # number of overall hits -system.cpu.icache.overall_hits::total 24250086 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9396 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9396 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9396 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9396 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9396 # number of overall misses -system.cpu.icache.overall_misses::total 9396 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 410761999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 410761999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 410761999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 410761999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 410761999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 410761999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24259482 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24259482 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24259482 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24259482 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24259482 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24259482 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000387 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000387 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000387 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000387 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000387 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000387 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43716.687846 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 43716.687846 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 43716.687846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43716.687846 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 43716.687846 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked +system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses +system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits +system.cpu.icache.overall_hits::total 24258362 # number of overall hits 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409019999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses 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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 69.230769 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 4974 # number of writebacks -system.cpu.icache.writebacks::total 4974 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2184 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2184 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2184 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2184 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2184 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2184 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7212 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7212 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7212 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7212 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7212 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7212 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312005999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 312005999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312005999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 312005999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312005999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 312005999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43262.063089 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43262.063089 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43262.063089 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43262.063089 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 5017 # number of writebacks +system.cpu.icache.writebacks::total 5017 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2159 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2159 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2159 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2583.684571 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8457 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3872 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.184143 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8528 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3879 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.198505 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.785192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2278.815860 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 303.083519 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 1.770890 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2276.984589 # Average occupied blocks per requestor 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blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2610 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118164 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 118500 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 118500 # Number of data accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 999 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.494922 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.922907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.922907 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.602493 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 14491 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5309 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 353 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadResp 7663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4883 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1540 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 453 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4558 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 23600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 757120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 885312 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 263 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 9466 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.067293 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.250543 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 279 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8829 93.27% 93.27% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 637 6.73% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9466 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12229500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10815000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3120998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadResp 3870 # Transaction distribution -system.membus.trans_dist::UpgradeReq 261 # Transaction distribution -system.membus.trans_dist::UpgradeResp 261 # Transaction distribution -system.membus.trans_dist::ReadExReq 1534 # Transaction distribution -system.membus.trans_dist::ReadExResp 1534 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3871 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11331 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11331 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 345856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 345856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 345856 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 3878 # Transaction distribution +system.membus.trans_dist::UpgradeReq 276 # Transaction distribution +system.membus.trans_dist::ReadExReq 1535 # Transaction distribution +system.membus.trans_dist::ReadExResp 1535 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5666 # Request fanout histogram +system.membus.snoop_fanout::samples 5689 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5666 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5666 # Request fanout histogram -system.membus.reqLayer0.occupancy 6923000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5689 # Request fanout histogram +system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 29158989 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index f73eb8157..41f61bd3d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869358498000 # Number of ticks simulated -final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1869357988000 # Number of ticks simulated +final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1016587 # Simulator instruction rate (inst/s) -host_op_rate 1016586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29236138105 # Simulator tick rate (ticks/s) -host_mem_usage 314344 # Number of bytes of host memory used -host_seconds 63.94 # Real time elapsed on the host -sim_insts 65000470 # Number of instructions simulated -sim_ops 65000470 # Number of ops (including micro ops) simulated +host_inst_rate 1993950 # Simulator instruction rate (inst/s) +host_op_rate 1993950 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57344769220 # Simulator tick rate (ticks/s) +host_mem_usage 333724 # Number of bytes of host memory used +host_seconds 32.60 # Real time elapsed on the host +sim_insts 64999904 # Number of instructions simulated +sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 66535616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 105984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 766336 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68167168 # Number of bytes read from this memory +system.physmem.bytes_read::total 68167296 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 105984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864256 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7836224 # Number of bytes written to this memory -system.physmem.bytes_written::total 7836224 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7836352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7836352 # Number of bytes written to this memory system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 1039619 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 11974 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065112 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122441 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122441 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1065114 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 122443 # Number of write requests responded to by this memory +system.physmem.num_writes::total 122443 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35592763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 409946 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465540 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36465619 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56695 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 462328 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4191932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4191932 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4191932 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4192002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4192002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4192002 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35592763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 409946 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40657473 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40657621 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758839 # DTB read hits +system.cpu0.dtb.read_hits 7758808 # DTB read hits system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740268 # DTB write hits +system.cpu0.dtb.write_hits 4740251 # DTB write hits system.cpu0.dtb.write_misses 732 # DTB write misses system.cpu0.dtb.write_acv 102 # DTB write access violations system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499107 # DTB hits +system.cpu0.dtb.data_hits 12499059 # DTB hits system.cpu0.dtb.data_misses 7887 # DTB misses system.cpu0.dtb.data_acv 254 # DTB access violations system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525737 # ITB hits +system.cpu0.itb.fetch_hits 3525726 # ITB hits system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529309 # ITB accesses +system.cpu0.itb.fetch_accesses 3529298 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -83,36 +83,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3738723791 # number of cpu cycles simulated +system.cpu0.numCycles 3738722771 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150436 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.18% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74447 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128509 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222948500 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975609500 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869358290500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678818 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811227 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed @@ -152,7 +152,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # nu system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121669 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed @@ -161,44 +161,44 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.55% # nu system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135930 # number of callpals executed +system.cpu0.kern.callpal::total 135929 # number of callpals executed system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1174 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1173 -system.cpu0.kern.mode_good::user 1174 +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177916 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.302176 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349657500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008632000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.cpu0.committedInsts 49478313 # Number of instructions committed -system.cpu0.committedOps 49478313 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46202260 # Number of integer alu accesses +system.cpu0.committedInsts 49477745 # Number of instructions committed +system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124639 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043708 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46202260 # number of integer instructions +system.cpu0.num_func_calls 1124633 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46201705 # number of integer instructions system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64004164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834852 # number of times the integer registers were written +system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536155 # number of memory refs -system.cpu0.num_load_insts 7783785 # Number of load instructions -system.cpu0.num_store_insts 4752370 # Number of store instructions -system.cpu0.num_idle_cycles 3689240240.665401 # Number of idle cycles -system.cpu0.num_busy_cycles 49483550.334599 # Number of busy cycles +system.cpu0.num_mem_refs 12536107 # number of memory refs +system.cpu0.num_load_insts 7783754 # Number of load instructions +system.cpu0.num_store_insts 4752353 # Number of store instructions +system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530941 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589824 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436514 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50547 0.10% 72.90% # Class of executed instruction +system.cpu0.Branches 7530826 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction @@ -226,18 +226,18 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7945621 16.06% 89.02% # Class of executed instruction -system.cpu0.op_class::MemWrite 4758309 9.62% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675566 1.37% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49486454 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1781373 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187448 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705809 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781885 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008137 # Average number of references to valid blocks. +system.cpu0.op_class::total 49485886 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1781371 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187448 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -245,56 +245,56 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822236 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822236 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068914 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068914 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360098 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360098 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127591 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127591 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132845 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132845 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10429012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10429012 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10429012 # number of overall hits -system.cpu0.dcache.overall_hits::total 10429012 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560067 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560067 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236542 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236542 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12627 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12627 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6925 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6925 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796609 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796609 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796609 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796609 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628981 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628981 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596640 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360085 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360085 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132849 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132849 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10428966 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428966 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428966 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428966 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236538 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236538 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6921 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6921 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796607 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796607 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796607 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796607 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225621 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225621 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225621 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225621 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204492 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204492 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090053 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090053 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049546 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049546 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051459 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051459 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049517 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049517 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,16 +303,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 632988 # number of writebacks -system.cpu0.dcache.writebacks::total 632988 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633127 # number of writebacks +system.cpu0.dcache.writebacks::total 633127 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 618298 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240646 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48867509 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618810 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.970135 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 618292 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240646 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -320,26 +320,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50105399 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50105399 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 48867509 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48867509 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48867509 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48867509 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48867509 # number of overall hits -system.cpu0.icache.overall_hits::total 48867509 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618945 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618945 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618945 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618945 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618945 # number of overall misses -system.cpu0.icache.overall_misses::total 618945 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49486454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49486454 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49486454 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49486454 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49486454 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49486454 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits +system.cpu0.icache.overall_hits::total 48866947 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses +system.cpu0.icache.overall_misses::total 618939 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses @@ -354,14 +354,14 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 618298 # number of writebacks -system.cpu0.icache.writebacks::total 618298 # number of writebacks +system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks +system.cpu0.icache.writebacks::total 618292 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831558 # DTB read hits +system.cpu1.dtb.read_hits 2831559 # DTB read hits system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations system.cpu1.dtb.read_accesses 198160 # DTB read accesses @@ -369,7 +369,7 @@ system.cpu1.dtb.write_hits 2101673 # DT system.cpu1.dtb.write_misses 412 # DTB write misses system.cpu1.dtb.write_acv 55 # DTB write access violations system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933231 # DTB hits +system.cpu1.dtb.data_hits 4933232 # DTB hits system.cpu1.dtb.data_misses 3603 # DTB misses system.cpu1.dtb.data_acv 113 # DTB access violations system.cpu1.dtb.data_accesses 288779 # DTB accesses @@ -389,7 +389,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3738297607 # number of cpu cycles simulated +system.cpu1.numCycles 3738296587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -405,11 +405,11 @@ system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # nu system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856124001500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870742500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869147438500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -461,32 +461,32 @@ system.cpu1.kern.mode_switch_good::kernel 0.434066 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986367000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102855500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.committedInsts 15522157 # Number of instructions committed -system.cpu1.committedOps 15522157 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295542 # Number of integer alu accesses +system.cpu1.committedInsts 15522159 # Number of instructions committed +system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295542 # number of integer instructions +system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295544 # number of integer instructions system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514287 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457599 # number of times the integer registers were written +system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961785 # number of memory refs -system.cpu1.num_load_insts 2849089 # Number of load instructions +system.cpu1.num_mem_refs 4961786 # number of memory refs +system.cpu1.num_load_insts 2849090 # Number of load instructions system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722774671.474094 # Number of idle cycles -system.cpu1.num_busy_cycles 15522935.525906 # Number of busy cycles +system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214162 # Number of branches fetched +system.cpu1.Branches 2214163 # Number of branches fetched system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156765 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction @@ -515,68 +515,68 @@ system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2937015 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525873 # Class of executed instruction -system.cpu1.dcache.tags.replacements 201756 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.613037 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718402 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202064 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.351027 # Average number of references to valid blocks. +system.cpu1.op_class::total 15525875 # Class of executed instruction +system.cpu1.dcache.tags.replacements 201757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.613037 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971900 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971900 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020602 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020602 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632689 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632689 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61099 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61099 # number of LoadLockedReq hits +system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1954643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1954643 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits system.cpu1.dcache.demand_hits::cpu1.data 4587331 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 4587331 # number of demand (read+write) hits system.cpu1.dcache.overall_hits::cpu1.data 4587331 # number of overall hits system.cpu1.dcache.overall_hits::total 4587331 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140883 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140883 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10999 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10999 # number of LoadLockedReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 78317 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 78317 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219201 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219201 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219201 # number of overall misses -system.cpu1.dcache.overall_misses::total 219201 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773572 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773572 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_misses::cpu1.data 219202 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219202 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219202 # number of overall misses +system.cpu1.dcache.overall_misses::total 219202 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806532 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806532 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806532 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806532 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152556 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152556 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses @@ -591,48 +591,48 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144531 # number of writebacks -system.cpu1.dcache.writebacks::total 144531 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144536 # number of writebacks +system.cpu1.dcache.writebacks::total 144536 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 380671 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133725 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144661 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381183 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.730683 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859779767500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133725 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 380647 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907085 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907085 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144661 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144661 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144661 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144661 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144661 # number of overall hits -system.cpu1.icache.overall_hits::total 15144661 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381212 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381212 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381212 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381212 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381212 # number of overall misses -system.cpu1.icache.overall_misses::total 381212 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525873 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525873 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525873 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525873 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024553 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024553 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024553 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024553 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024553 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024553 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits +system.cpu1.icache.overall_hits::total 15144687 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses +system.cpu1.icache.overall_misses::total 381188 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -641,8 +641,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 380671 # number of writebacks -system.cpu1.icache.writebacks::total 380671 # number of writebacks +system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks +system.cpu1.icache.writebacks::total 380647 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -687,12 +687,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 26616 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434101 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434101 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -735,140 +735,140 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 999918 # number of replacements -system.l2c.tags.tagsinuse 65320.982415 # Cycle average of tags in use -system.l2c.tags.total_refs 4249962 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1064968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.990695 # Average number of references to valid blocks. +system.l2c.tags.replacements 999922 # number of replacements +system.l2c.tags.tagsinuse 65337.856722 # Cycle average of tags in use +system.l2c.tags.total_refs 4259784 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064972 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.999902 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55992.770808 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4860.291584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4178.146657 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.172078 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 114.601288 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.854382 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 55997.404251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4860.296117 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4190.275222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 175.171528 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.709605 # Average occupied blocks per requestor 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6123 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5943 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48945 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5933 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49031 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46365909 # Number of tag accesses -system.l2c.tags.data_accesses 46365909 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 777519 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 777519 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 719211 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 719211 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.tags.tag_accesses 46377222 # Number of tag accesses +system.l2c.tags.data_accesses 46377222 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 777663 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 777663 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 721478 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 721478 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 130 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 604 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 734 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits system.l2c.ReadExReq_hits::cpu0.data 111475 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168078 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 607076 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379556 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986632 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626681 # number of ReadSharedReq hits +system.l2c.ReadExReq_hits::cpu1.data 56605 # number of ReadExReq hits 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ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 927650 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1040489 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1656 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12104 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066097 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040486 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066093 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses -system.l2c.overall_misses::cpu0.data 1040489 # number of overall misses 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# number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 1553334 # number of ReadSharedReq accesses(hits+misses) system.l2c.ReadSharedReq_accesses::cpu1.data 130046 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1683342 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618924 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778645 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381212 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197718 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2976499 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618924 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778645 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381212 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197718 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2976499 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790258 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.882002 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.505323 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163568 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.426396 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_accesses::total 1683380 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778680 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976503 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778680 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976503 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.958320 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780443 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.874957 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.963606 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975067 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.969125 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505316 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163526 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426381 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004344 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013502 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596548 # miss rate for ReadSharedReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596533 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007959 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551076 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551064 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584990 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004344 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061219 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358171 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584976 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358170 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584990 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004344 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061219 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358171 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584976 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358170 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,91 +877,91 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 80921 # number of writebacks -system.l2c.writebacks::total 80921 # number of writebacks +system.l2c.writebacks::writebacks 80923 # number of writebacks +system.l2c.writebacks::total 80923 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948782 # Transaction distribution +system.membus.trans_dist::ReadResp 948784 # Transaction distribution system.membus.trans_dist::WriteReq 14588 # Transaction distribution system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122441 # Transaction distribution -system.membus.trans_dist::CleanEvict 917844 # Transaction distribution -system.membus.trans_dist::UpgradeReq 19642 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 14180 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8186 # Transaction distribution -system.membus.trans_dist::ReadExReq 126447 # Transaction distribution +system.membus.trans_dist::WritebackDirty 122443 # Transaction distribution +system.membus.trans_dist::CleanEvict 918012 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19594 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14154 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8111 # Transaction distribution +system.membus.trans_dist::ReadExReq 125245 # Transaction distribution system.membus.trans_dist::ReadExResp 124222 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941333 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 941335 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3173737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3217811 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124995 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3342806 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3172394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3216468 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3341629 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73449170 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73363264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73449426 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76117906 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76118162 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2205642 # Request fanout histogram +system.membus.snoop_fanout::samples 2204372 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2205642 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2204372 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2205642 # Request fanout histogram -system.toL2Bus.snoop_filter.tot_requests 6035921 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018741 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 376832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 2204372 # Request fanout histogram +system.toL2Bus.snoop_filter.tot_requests 6035855 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 3018704 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 374458 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1611 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1521 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 777519 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 719211 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1143412 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19614 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14230 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33844 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295246 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295246 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1000157 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1705094 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5410979 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1014431 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 661358 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8791862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69513536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155758011 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40526016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 289155538 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1083512 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 7141306 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106198 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.308338 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 777663 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1205465 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19613 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14226 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33839 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1724580 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450139 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 9133717 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155766779 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23358423 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 307065426 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1083516 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7141244 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.105534 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.307488 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6383457 89.39% 89.39% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 757309 10.60% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 6388144 89.45% 89.45% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 752560 10.54% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7141306 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 7141244 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index be6733354..25be00c51 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332273500 # Number of ticks simulated -final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829331993500 # Number of ticks simulated +final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 996309 # Simulator instruction rate (inst/s) -host_op_rate 996308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30356892493 # Simulator tick rate (ticks/s) -host_mem_usage 311076 # Number of bytes of host memory used -host_seconds 60.26 # Real time elapsed on the host -sim_insts 60038341 # Number of instructions simulated -sim_ops 60038341 # Number of ops (including micro ops) simulated +host_inst_rate 1828258 # Simulator instruction rate (inst/s) +host_op_rate 1828257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 55705727715 # Simulator tick rate (ticks/s) +host_mem_usage 331420 # Number of bytes of host memory used +host_seconds 32.84 # Real time elapsed on the host +sim_insts 60038469 # Number of instructions simulated +sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66835456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67686912 # Number of bytes read from this memory +system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7416128 # Number of bytes written to this memory -system.physmem.bytes_written::total 7416128 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory +system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044304 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057608 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115877 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115877 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37000884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4054008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4054008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4054008 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41054893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710422 # DTB read hits +system.cpu.dtb.read_hits 9710423 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses @@ -53,14 +53,14 @@ system.cpu.dtb.write_hits 6352496 # DT system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062918 # DTB hits +system.cpu.dtb.data_hits 16062919 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974648 # ITB hits +system.cpu.itb.fetch_hits 4974637 # ITB hits system.cpu.itb.fetch_misses 5006 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979654 # ITB accesses +system.cpu.itb.fetch_accesses 4979643 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -73,32 +73,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658670905 # number of cpu cycles simulated +system.cpu.numCycles 3658670345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed +system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -137,7 +137,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed +system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed @@ -146,43 +146,43 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192180 # number of callpals executed +system.cpu.kern.callpal::total 192179 # number of callpals executed system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches +system.cpu.kern.mode_switch::user 1737 # number of protection mode switches system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1909 -system.cpu.kern.mode_good::user 1738 +system.cpu.kern.mode_good::kernel 1908 +system.cpu.kern.mode_good::user 1737 system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.committedInsts 60038341 # Number of instructions committed -system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses +system.cpu.committedInsts 60038469 # Number of instructions committed +system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913563 # number of integer instructions +system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913692 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115702 # number of memory refs -system.cpu.num_load_insts 9747508 # Number of load instructions +system.cpu.num_mem_refs 16115703 # number of memory refs +system.cpu.num_load_insts 9747509 # Number of load instructions system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles -system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles +system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064400 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction +system.cpu.Branches 9064428 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction @@ -211,16 +211,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050179 # Class of executed instruction -system.cpu.dcache.tags.replacements 2042728 # number of replacements +system.cpu.op_class::total 60050307 # Class of executed instruction +system.cpu.dcache.tags.replacements 2042707 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -230,52 +230,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits -system.cpu.dcache.overall_hits::total 13655960 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses -system.cpu.dcache.overall_misses::total 2026094 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits +system.cpu.dcache.overall_hits::total 13655981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -284,16 +284,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833492 # number of writebacks -system.cpu.dcache.writebacks::total 833492 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks +system.cpu.dcache.writebacks::total 833475 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 919605 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 919603 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,26 +301,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits -system.cpu.icache.overall_hits::total 59129947 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses -system.cpu.icache.overall_misses::total 920232 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits +system.cpu.icache.overall_hits::total 59130077 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses +system.cpu.icache.overall_misses::total 920230 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -335,18 +335,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 919605 # number of writebacks -system.cpu.icache.writebacks::total 919605 # number of writebacks +system.cpu.icache.writebacks::writebacks 919603 # number of writebacks +system.cpu.icache.writebacks::total 919603 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992425 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374115 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4560164 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057588 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.311853 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992419 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56331.555575 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.320500 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.498040 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy @@ -355,75 +355,75 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48754034 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48754034 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 833492 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 833492 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 919353 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 919353 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906925 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906925 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811243 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811243 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906925 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998531 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905456 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906925 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998531 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905456 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905439 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044710 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1057999 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044710 # number of overall misses -system.cpu.l2cache.overall_misses::total 1057999 # number of overall misses -system.cpu.l2cache.WritebackDirty_accesses::writebacks 833492 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 833492 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 919353 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 919353 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses +system.cpu.l2cache.overall_misses::total 1057993 # number of overall misses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533470 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533470 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357015 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357015 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -432,46 +432,46 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74365 # number of writebacks -system.cpu.l2cache.writebacks::total 74365 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks +system.cpu.l2cache.writebacks::total 74359 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5925822 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962455 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 833492 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 919353 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1207667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2759817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6161717 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8921534 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117733440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157038 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 301890478 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1075994 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 7018681 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1075988 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7013458 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7018681 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -515,12 +515,12 @@ system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 26616 system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -567,39 +567,39 @@ system.membus.trans_dist::ReadReq 7184 # Tr system.membus.trans_dist::ReadResp 948291 # Transaction distribution system.membus.trans_dist::WriteReq 9838 # Transaction distribution system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115877 # Transaction distribution -system.membus.trans_dist::CleanEvict 917027 # Transaction distribution +system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution +system.membus.trans_dist::CleanEvict 917188 # Transaction distribution system.membus.trans_dist::UpgradeReq 147 # Transaction distribution system.membus.trans_dist::UpgradeResp 147 # Transaction distribution -system.membus.trans_dist::ReadExReq 116931 # Transaction distribution -system.membus.trans_dist::ReadExResp 116931 # Transaction distribution +system.membus.trans_dist::ReadExReq 116925 # Transaction distribution +system.membus.trans_dist::ReadExResp 116925 # Transaction distribution system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107401 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124977 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266422 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72462656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508782 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75176686 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2149824 # Request fanout histogram +system.membus.snoop_fanout::samples 2149812 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2149824 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2149824 # Request fanout histogram +system.membus.snoop_fanout::total 2149812 # Request fanout histogram system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index a1e8c67e3..965d378dd 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.982594 # Number of seconds simulated -sim_ticks 1982594146000 # Number of ticks simulated -final_tick 1982594146000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982593 # Number of seconds simulated +sim_ticks 1982593132000 # Number of ticks simulated +final_tick 1982593132000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 452083 # Simulator instruction rate (inst/s) -host_op_rate 452083 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14696000274 # Simulator tick rate (ticks/s) -host_mem_usage 314492 # Number of bytes of host memory used -host_seconds 134.91 # Real time elapsed on the host -sim_insts 60989111 # Number of instructions simulated -sim_ops 60989111 # Number of ops (including micro ops) simulated +host_inst_rate 1109655 # Simulator instruction rate (inst/s) +host_op_rate 1109654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36063876778 # Simulator tick rate (ticks/s) +host_mem_usage 333984 # Number of bytes of host memory used +host_seconds 54.97 # Real time elapsed on the host +sim_insts 61002651 # Number of instructions simulated +sim_ops 61002651 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 800320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24686528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 60096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 523456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 800256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24686464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 59392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 523264 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26071360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 800320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 60096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 860416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7740160 # Number of bytes written to this memory -system.physmem.bytes_written::total 7740160 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12505 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 385727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 939 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8179 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26070336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 800256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 59392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 859648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7739904 # Number of bytes written to this memory +system.physmem.bytes_written::total 7739904 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12504 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385726 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 928 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8176 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407365 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120940 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120940 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 403673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12451630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 30312 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 264026 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 407349 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120936 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120936 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 403641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12451604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 29957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 263929 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13150125 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 403673 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 30312 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3904057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3904057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3904057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 403673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12451630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 30312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 264026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13149615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 403641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 29957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3903930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3903930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3903930 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 403641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12451604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 29957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 263929 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17054181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407365 # Number of read requests accepted -system.physmem.writeReqs 120940 # Number of write requests accepted -system.physmem.readBursts 407365 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120940 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26063552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue -system.physmem.bytesWritten 7739008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26071360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7740160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17053544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407349 # Number of read requests accepted +system.physmem.writeReqs 120936 # Number of write requests accepted +system.physmem.readBursts 407349 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120936 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26062656 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue +system.physmem.bytesWritten 7738112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26070336 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7739904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 310700 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25226 # Per bank write bursts system.physmem.perBankRdBursts::1 25379 # Per bank write bursts -system.physmem.perBankRdBursts::2 25426 # Per bank write bursts -system.physmem.perBankRdBursts::3 24856 # Per bank write bursts +system.physmem.perBankRdBursts::2 25428 # Per bank write bursts +system.physmem.perBankRdBursts::3 24855 # Per bank write bursts system.physmem.perBankRdBursts::4 25157 # Per bank write bursts system.physmem.perBankRdBursts::5 25423 # Per bank write bursts -system.physmem.perBankRdBursts::6 25497 # Per bank write bursts -system.physmem.perBankRdBursts::7 25344 # Per bank write bursts +system.physmem.perBankRdBursts::6 25496 # Per bank write bursts +system.physmem.perBankRdBursts::7 25345 # Per bank write bursts system.physmem.perBankRdBursts::8 25239 # Per bank write bursts system.physmem.perBankRdBursts::9 25589 # Per bank write bursts -system.physmem.perBankRdBursts::10 25746 # Per bank write bursts -system.physmem.perBankRdBursts::11 25918 # Per bank write bursts +system.physmem.perBankRdBursts::10 25733 # Per bank write bursts +system.physmem.perBankRdBursts::11 25919 # Per bank write bursts system.physmem.perBankRdBursts::12 25947 # Per bank write bursts system.physmem.perBankRdBursts::13 25572 # Per bank write bursts system.physmem.perBankRdBursts::14 25277 # Per bank write bursts -system.physmem.perBankRdBursts::15 25647 # Per bank write bursts -system.physmem.perBankWrBursts::0 7851 # Per bank write bursts +system.physmem.perBankRdBursts::15 25644 # Per bank write bursts +system.physmem.perBankWrBursts::0 7850 # Per bank write bursts system.physmem.perBankWrBursts::1 7778 # Per bank write bursts system.physmem.perBankWrBursts::2 7471 # Per bank write bursts -system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::3 6886 # Per bank write bursts system.physmem.perBankWrBursts::4 7104 # Per bank write bursts system.physmem.perBankWrBursts::5 7345 # Per bank write bursts -system.physmem.perBankWrBursts::6 7441 # Per bank write bursts -system.physmem.perBankWrBursts::7 7150 # Per bank write bursts +system.physmem.perBankWrBursts::6 7430 # Per bank write bursts +system.physmem.perBankWrBursts::7 7151 # Per bank write bursts system.physmem.perBankWrBursts::8 7161 # Per bank write bursts system.physmem.perBankWrBursts::9 7315 # Per bank write bursts system.physmem.perBankWrBursts::10 7729 # Per bank write bursts -system.physmem.perBankWrBursts::11 8151 # Per bank write bursts +system.physmem.perBankWrBursts::11 8152 # Per bank write bursts system.physmem.perBankWrBursts::12 8256 # Per bank write bursts system.physmem.perBankWrBursts::13 7924 # Per bank write bursts system.physmem.perBankWrBursts::14 7541 # Per bank write bursts -system.physmem.perBankWrBursts::15 7818 # Per bank write bursts +system.physmem.perBankWrBursts::15 7815 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1982586778500 # Total gap between requests +system.physmem.numWrRetry 11 # Number of times write queue was full causing retry +system.physmem.totGap 1982585764500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407365 # Read request sizes (log2) +system.physmem.readPktSize::6 407349 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120940 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120936 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,125 +158,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8528 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5703 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 76 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67594 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 500.082256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 302.770491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 404.772373 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16306 24.12% 24.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12315 18.22% 42.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5219 7.72% 50.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3345 4.95% 55.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2482 3.67% 58.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4236 6.27% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1519 2.25% 67.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2145 3.17% 70.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20027 29.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67594 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5426 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.053815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2863.944316 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5423 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.144536 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.732498 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 404.890859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16271 24.08% 24.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12393 18.34% 42.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5170 7.65% 50.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3294 4.87% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2518 3.73% 58.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4277 6.33% 64.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1487 2.20% 67.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2102 3.11% 70.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20070 29.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67582 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5413 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.229078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2867.379606 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5410 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5426 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5426 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.285662 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.994987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.002081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4792 88.32% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 23 0.42% 88.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.29% 89.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 184 3.39% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1 0.02% 92.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 19 0.35% 92.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 45 0.83% 93.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.13% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 30 0.55% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.13% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.07% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 5 0.09% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 20 0.37% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.48% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 28 0.52% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 96.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.07% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 168 3.10% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 5 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 10 0.18% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5426 # Writes before turning the bus around for reads -system.physmem.totQLat 2787487250 # Total ticks spent queuing -system.physmem.totMemAccLat 10423293500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6844.78 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5413 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.336597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.167195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.176387 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4808 88.82% 88.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.54% 89.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 21 0.39% 89.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 46 0.85% 90.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 212 3.92% 94.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 15 0.28% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 14 0.26% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 26 0.48% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 189 3.49% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.09% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.09% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.09% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 2 0.04% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 4 0.07% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 1 0.02% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 8 0.15% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 3 0.06% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 8 0.15% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5413 # Writes before turning the bus around for reads +system.physmem.totQLat 2790032750 # Total ticks spent queuing +system.physmem.totMemAccLat 10425576500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6851.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25594.78 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25601.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s @@ -286,62 +273,62 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing -system.physmem.readRowHits 363847 # Number of row buffer hits during reads -system.physmem.writeRowHits 96724 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 363813 # Number of row buffer hits during reads +system.physmem.writeRowHits 96742 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.98 # Row buffer hit rate for writes -system.physmem.avgGap 3752731.43 # Average gap between requests +system.physmem.writeRowHitRate 79.99 # Row buffer hit rate for writes +system.physmem.avgGap 3752871.58 # Average gap between requests system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243930960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 133097250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578002400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 382494960 # Energy for write commands per rank (pJ) +system.physmem_0.actEnergy 244006560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133138500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578010200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382417200 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72912858435 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1125595195500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1330338686625 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.010578 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1872246434250 # Time in different power states +system.physmem_0.actBackEnergy 72939489120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125571835250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330342003950 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.012251 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872206783000 # Time in different power states system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 44140298250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44179949500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 267079680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145728000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1598493000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 401079600 # Energy for write commands per rank (pJ) +system.physmem_1.actEnergy 266913360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145637250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598376000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401066640 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73974222945 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124664165750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1330543876095 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.114078 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1870697169250 # Time in different power states +system.physmem_1.actBackEnergy 73838725110 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124783023500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330526848980 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.105490 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870895185000 # Time in different power states system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45689549500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45491533750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7416215 # DTB read hits +system.cpu0.dtb.read_hits 7416541 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 5004240 # DTB write hits +system.cpu0.dtb.write_hits 5004457 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 12420455 # DTB hits +system.cpu0.dtb.data_hits 12420998 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3482237 # ITB hits +system.cpu0.itb.fetch_hits 3482402 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3486108 # ITB accesses +system.cpu0.itb.fetch_accesses 3486273 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -354,36 +341,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3964851893 # number of cpu cycles simulated +system.cpu0.numCycles 3964851877 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6804 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 162792 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162801 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 133 0.10% 40.21% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 80934 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139403 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80941 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139412 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 133 0.12% 49.18% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54982 48.68% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 112942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1904792162000 96.08% 96.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93245000 0.00% 96.09% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790775500 0.04% 96.13% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 326471500 0.02% 96.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 76423262500 3.86% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1982425916500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_good::31 54983 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112945 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904793300500 96.08% 96.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93813000 0.00% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790638500 0.04% 96.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 326474000 0.02% 96.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76421682500 3.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425908500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.679344 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810183 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679297 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810153 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -422,54 +409,54 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # nu system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132535 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132542 89.80% 92.24% # number of callpals executed system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed -system.cpu0.kern.callpal::rti 4324 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::rti 4325 2.93% 99.65% # number of callpals executed system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 147594 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6862 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches +system.cpu0.kern.callpal::total 147602 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6863 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1281 -system.cpu0.kern.mode_good::user 1281 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.186680 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186799 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.314626 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1977686351500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3896829000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314794 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977682087000 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3901070000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3025 # number of times the context was actually changed -system.cpu0.committedInsts 47311851 # Number of instructions committed -system.cpu0.committedOps 47311851 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 43882265 # Number of integer alu accesses +system.cpu0.committedInsts 47316172 # Number of instructions committed +system.cpu0.committedOps 47316172 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43886449 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses -system.cpu0.num_func_calls 1185568 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5564719 # number of instructions that are conditional controls -system.cpu0.num_int_insts 43882265 # number of integer instructions +system.cpu0.num_func_calls 1185652 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5565345 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43886449 # number of integer instructions system.cpu0.num_fp_insts 206939 # number of float instructions -system.cpu0.num_int_register_reads 60327433 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32715156 # number of times the integer registers were written +system.cpu0.num_int_register_reads 60334275 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32718467 # number of times the integer registers were written system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written -system.cpu0.num_mem_refs 12460349 # number of memory refs -system.cpu0.num_load_insts 7443153 # Number of load instructions -system.cpu0.num_store_insts 5017196 # Number of store instructions -system.cpu0.num_idle_cycles 3699958327.970898 # Number of idle cycles -system.cpu0.num_busy_cycles 264893565.029101 # Number of busy cycles -system.cpu0.not_idle_fraction 0.066810 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.933190 # Percentage of idle cycles -system.cpu0.Branches 7132898 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2702955 5.71% 5.71% # Class of executed instruction -system.cpu0.op_class::IntAlu 31171442 65.87% 71.59% # Class of executed instruction -system.cpu0.op_class::IntMult 51645 0.11% 71.69% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.num_mem_refs 12460893 # number of memory refs +system.cpu0.num_load_insts 7443480 # Number of load instructions +system.cpu0.num_store_insts 5017413 # Number of store instructions +system.cpu0.num_idle_cycles 3699956428.707181 # Number of idle cycles +system.cpu0.num_busy_cycles 264895448.292820 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066811 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933189 # Percentage of idle cycles +system.cpu0.Branches 7133641 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2703037 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31175022 65.87% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51696 0.11% 71.70% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.70% # Class of executed instruction system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction @@ -496,98 +483,98 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction -system.cpu0.op_class::MemRead 7616230 16.10% 87.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 5023298 10.62% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 727657 1.54% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7616572 16.09% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023515 10.61% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727706 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47320449 # Class of executed instruction -system.cpu0.dcache.tags.replacements 1172797 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.333348 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11236424 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1173216 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.577455 # Average number of references to valid blocks. +system.cpu0.op_class::total 47324770 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1172753 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.332741 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11237004 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173173 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.578301 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333348 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986979 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986979 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.332741 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986978 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986978 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 50906675 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 50906675 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6342506 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6342506 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4600881 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4600881 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138108 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138108 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145430 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 145430 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10943387 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10943387 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10943387 # number of overall hits -system.cpu0.dcache.overall_hits::total 10943387 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 934212 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 934212 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 249094 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 249094 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13595 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13595 # number of LoadLockedReq misses +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 372 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.820312 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50908772 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50908772 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6342827 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6342827 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4601104 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4601104 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138127 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138127 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145435 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145435 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10943931 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10943931 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10943931 # number of overall hits +system.cpu0.dcache.overall_hits::total 10943931 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 934208 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 934208 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249079 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249079 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13580 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13580 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1183306 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1183306 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1183306 # number of overall misses -system.cpu0.dcache.overall_misses::total 1183306 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42884699000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 42884699000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16803448000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 16803448000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151690000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 151690000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 97426500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 97426500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 59688147000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 59688147000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 59688147000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 59688147000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276718 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7276718 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4849975 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4849975 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151703 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 151703 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 151169 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12126693 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12126693 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12126693 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12126693 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128384 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.128384 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051360 # miss rate for WriteReq accesses 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45904.675812 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67458.260737 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 67458.260737 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11157.778595 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11157.778595 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16976.215369 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16976.215369 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50441.852741 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 50441.852741 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50441.852741 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 50441.852741 # average overall miss latency +system.cpu0.dcache.demand_misses::cpu0.data 1183287 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183287 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183287 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183287 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42886334500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42886334500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16793569500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16793569500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 151760500 # number of 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45906.623043 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45906.623043 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67422.663091 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67422.663091 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11175.294551 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11175.294551 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16514.288204 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16514.288204 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50435.696496 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50435.696496 # average overall miss latency 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-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49441.852741 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221208.757062 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221208.757062 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227372.773655 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227372.773655 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224929.255319 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224929.255319 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183287 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 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58496617000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58496617000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1567540500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1567540500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2452068500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2452068500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4019609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4019609000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128378 # mshr miss rate for ReadReq accesses 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mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097573 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44906.623043 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44906.623043 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66422.663091 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66422.663091 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10175.294551 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10175.294551 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15514.288204 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15514.288204 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49435.696496 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221216.553768 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221216.553768 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227380.239243 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227380.239243 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224936.149972 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224936.149972 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 686460 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.490701 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 46633355 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 686972 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.882468 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 686592 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.490691 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46637544 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 687104 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.875524 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490691 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48007543 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48007543 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 46633355 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 46633355 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 46633355 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 46633355 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 46633355 # number of overall hits -system.cpu0.icache.overall_hits::total 46633355 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 687094 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 687094 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 687094 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 687094 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 687094 # number of overall misses -system.cpu0.icache.overall_misses::total 687094 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10621840000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10621840000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10621840000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10621840000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10621840000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10621840000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47320449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47320449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47320449 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47320449 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47320449 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47320449 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15459.078379 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15459.078379 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15459.078379 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15459.078379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15459.078379 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15459.078379 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48011996 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48011996 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46637544 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46637544 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46637544 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46637544 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46637544 # number of overall hits +system.cpu0.icache.overall_hits::total 46637544 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687226 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687226 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687226 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687226 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687226 # number of overall misses +system.cpu0.icache.overall_misses::total 687226 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10626395500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10626395500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10626395500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10626395500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10626395500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10626395500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47324770 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47324770 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47324770 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47324770 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47324770 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47324770 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15462.737877 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15462.737877 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15462.737877 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15462.737877 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15462.737877 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -724,53 +711,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 686460 # number of writebacks -system.cpu0.icache.writebacks::total 686460 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687094 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 687094 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 687094 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 687094 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 687094 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 687094 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9934746000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9934746000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9934746000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9934746000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9934746000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9934746000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14459.078379 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14459.078379 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14459.078379 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 686592 # number of writebacks +system.cpu0.icache.writebacks::total 686592 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687226 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687226 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687226 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687226 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687226 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687226 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9939169500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9939169500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9939169500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9939169500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9939169500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9939169500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14462.737877 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14462.737877 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14462.737877 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2510685 # DTB read hits +system.cpu1.dtb.read_hits 2511145 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 1829711 # DTB write hits +system.cpu1.dtb.write_hits 1829996 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 4340396 # DTB hits +system.cpu1.dtb.data_hits 4341141 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 1990327 # ITB hits +system.cpu1.itb.fetch_hits 1990273 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1991543 # ITB accesses +system.cpu1.itb.fetch_accesses 1991489 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -783,32 +770,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3965188292 # number of cpu cycles simulated +system.cpu1.numCycles 3965186264 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2870 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 81053 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27549 38.53% 38.53% # number of times we switched to this ipl +system.cpu1.kern.inst.quiesce 2869 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81047 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27546 38.52% 38.52% # number of times we switched to this ipl system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41464 57.99% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 71508 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26681 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 41461 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71502 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26678 48.22% 48.22% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 26157 47.27% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 55333 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1912242644500 96.45% 96.45% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731132000 0.04% 96.49% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 374834500 0.02% 96.51% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 69244798000 3.49% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1982593409000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968493 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 26154 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55327 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912240588500 96.45% 96.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731240000 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 374509500 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69246057000 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982592395000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968489 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.630836 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.773802 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630810 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773783 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -827,10 +814,10 @@ system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2066 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2066 2.79% 3.39% # number of callpals executed system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed -system.cpu1.kern.callpal::swpipl 65186 88.12% 91.52% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65180 88.12% 91.52% # number of callpals executed system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed @@ -839,164 +826,164 @@ system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # nu system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73976 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2114 # number of protection mode switches +system.cpu1.kern.callpal::total 73970 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2115 # number of protection mode switches system.cpu1.kern.mode_switch::user 464 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2921 # number of protection mode switches system.cpu1.kern.mode_good::kernel 912 system.cpu1.kern.mode_good::user 464 system.cpu1.kern.mode_good::idle 448 -system.cpu1.kern.mode_switch_good::kernel 0.431410 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.431206 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153320 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::idle 0.153372 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 19465916000 0.98% 0.98% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1729420000 0.09% 1.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1961398071000 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 19470103000 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1729907500 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961392382500 98.93% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2067 # number of times the context was actually changed -system.cpu1.committedInsts 13677260 # Number of instructions committed -system.cpu1.committedOps 13677260 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12615003 # Number of integer alu accesses +system.cpu1.committedInsts 13686479 # Number of instructions committed +system.cpu1.committedOps 13686479 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12624111 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses -system.cpu1.num_func_calls 430048 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1358006 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12615003 # number of integer instructions +system.cpu1.num_func_calls 430158 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1359705 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12624111 # number of integer instructions system.cpu1.num_fp_insts 178612 # number of float instructions -system.cpu1.num_int_register_reads 17367613 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9253143 # number of times the integer registers were written +system.cpu1.num_int_register_reads 17383206 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9260208 # number of times the integer registers were written system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written -system.cpu1.num_mem_refs 4364552 # number of memory refs -system.cpu1.num_load_insts 2525340 # Number of load instructions -system.cpu1.num_store_insts 1839212 # Number of store instructions -system.cpu1.num_idle_cycles 3912229588.998027 # Number of idle cycles -system.cpu1.num_busy_cycles 52958703.001973 # Number of busy cycles -system.cpu1.not_idle_fraction 0.013356 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.986644 # Percentage of idle cycles -system.cpu1.Branches 1948315 # Number of branches fetched -system.cpu1.op_class::No_OpClass 733682 5.36% 5.36% # Class of executed instruction -system.cpu1.op_class::IntAlu 8093046 59.16% 64.52% # Class of executed instruction -system.cpu1.op_class::IntMult 23046 0.17% 64.69% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.69% # Class of executed instruction -system.cpu1.op_class::FloatAdd 14372 0.11% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 64.81% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction -system.cpu1.op_class::MemRead 2600021 19.01% 83.81% # Class of executed instruction -system.cpu1.op_class::MemWrite 1840236 13.45% 97.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 374235 2.74% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 4365297 # number of memory refs +system.cpu1.num_load_insts 2525800 # Number of load instructions +system.cpu1.num_store_insts 1839497 # Number of store instructions +system.cpu1.num_idle_cycles 3912233484.998027 # Number of idle cycles +system.cpu1.num_busy_cycles 52952779.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013354 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986646 # Percentage of idle cycles +system.cpu1.Branches 1950120 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733810 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 8101284 59.18% 64.54% # Class of executed instruction +system.cpu1.op_class::IntMult 23184 0.17% 64.71% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14372 0.10% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.83% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu1.op_class::MemRead 2600475 19.00% 83.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 1840521 13.44% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 374211 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13680624 # Class of executed instruction -system.cpu1.dcache.tags.replacements 173715 # number of replacements -system.cpu1.dcache.tags.tagsinuse 481.481115 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4164110 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 174227 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.900486 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90323581500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.481115 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940393 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.940393 # Average percentage of cache occupancy +system.cpu1.op_class::total 13689843 # Class of executed instruction +system.cpu1.dcache.tags.replacements 173686 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.983606 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4164884 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174198 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.908908 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90321767000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.983606 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.941374 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.941374 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 17605365 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 17605365 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2339052 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2339052 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1706902 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1706902 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50404 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 50404 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53074 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 53074 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4045954 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4045954 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4045954 # number of overall hits -system.cpu1.dcache.overall_hits::total 4045954 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 123499 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 123499 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 65580 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 65580 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9274 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9274 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6110 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6110 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 189079 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 189079 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 189079 # number of overall misses -system.cpu1.dcache.overall_misses::total 189079 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1557395000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1557395000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1879104500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1879104500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85318500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 85318500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 99555000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 99555000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 3436499500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 3436499500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 3436499500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 3436499500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2462551 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2462551 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772482 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1772482 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59678 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 59678 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59184 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 59184 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4235033 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4235033 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4235033 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4235033 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050151 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050151 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036999 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.036999 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155401 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155401 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103237 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103237 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044646 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044646 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044646 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044646 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12610.587940 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12610.587940 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28653.621531 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28653.621531 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9199.751995 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9199.751995 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16293.780687 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16293.780687 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18174.940104 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18174.940104 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18174.940104 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18174.940104 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17608316 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17608316 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2339523 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2339523 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1707175 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1707175 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50425 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50425 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53078 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 53078 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4046698 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4046698 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4046698 # number of overall hits +system.cpu1.dcache.overall_hits::total 4046698 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123485 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123485 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 65589 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 65589 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9256 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9256 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6109 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6109 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 189074 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 189074 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 189074 # number of overall misses +system.cpu1.dcache.overall_misses::total 189074 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1555964500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1555964500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1870805000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1870805000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85075000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 85075000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 96955500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 96955500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3426769500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3426769500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3426769500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3426769500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2463008 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2463008 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772764 # number of WriteReq accesses(hits+misses) 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for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12600.433251 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12600.433251 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28523.151748 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28523.151748 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9191.335350 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9191.335350 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15870.928139 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15870.928139 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18123.959402 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18123.959402 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18123.959402 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18123.959402 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1005,128 +992,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 119750 # number of writebacks -system.cpu1.dcache.writebacks::total 119750 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123499 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 123499 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65580 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65580 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9274 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6110 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6110 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 189079 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 189079 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 189079 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 189079 # number of overall MSHR misses +system.cpu1.dcache.writebacks::writebacks 119736 # number of writebacks +system.cpu1.dcache.writebacks::total 119736 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123485 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123485 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65589 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65589 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9256 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9256 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6109 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6109 # number of StoreCondReq MSHR misses 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-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1433896000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1433896000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1813524500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1813524500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 76044500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 76044500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 93445000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 93445000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3247420500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3247420500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3247420500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3247420500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1432479500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1432479500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1805216000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1805216000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 75819000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 75819000 # number of LoadLockedReq MSHR miss cycles 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cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789483500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814534500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814534500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050151 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050151 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036999 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036999 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155401 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155401 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103237 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044646 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.044646 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044646 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.044646 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11610.587940 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11610.587940 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27653.621531 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27653.621531 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.751995 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.751995 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15293.780687 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15293.780687 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17174.940104 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17174.940104 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17174.940104 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17174.940104 # average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789482000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789482000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814533000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050136 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050136 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036998 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036998 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155091 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155091 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103215 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103215 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044637 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044637 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044637 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11600.433251 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11600.433251 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27523.151748 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27523.151748 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8191.335350 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.335350 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14870.928139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14870.928139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17123.959402 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17123.959402 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.497013 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.497013 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235007.068667 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235007.068667 # average overall mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.048984 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.048984 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235006.635892 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235006.635892 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 331421 # number of replacements -system.cpu1.icache.tags.tagsinuse 442.918144 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13348652 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 331933 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.214899 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1976561020500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.918144 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865074 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.865074 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331505 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.932847 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13357787 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 332017 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.232238 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1975288394500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.932847 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865103 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865103 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14012598 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14012598 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13348652 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13348652 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13348652 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13348652 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13348652 # number of overall hits -system.cpu1.icache.overall_hits::total 13348652 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 331973 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 331973 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 331973 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 331973 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 331973 # number of overall misses -system.cpu1.icache.overall_misses::total 331973 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541836000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4541836000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4541836000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4541836000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4541836000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4541836000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13680625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13680625 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13680625 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13680625 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13680625 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13680625 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024266 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024266 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024266 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024266 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024266 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024266 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13681.341555 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13681.341555 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13681.341555 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13681.341555 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13681.341555 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13681.341555 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14021901 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14021901 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13357787 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13357787 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13357787 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13357787 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13357787 # number of overall hits +system.cpu1.icache.overall_hits::total 13357787 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 332057 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 332057 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 332057 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 332057 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 332057 # number of overall misses +system.cpu1.icache.overall_misses::total 332057 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541544500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4541544500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4541544500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4541544500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4541544500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4541544500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13689844 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13689844 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13689844 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13689844 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13689844 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13689844 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024256 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024256 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024256 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024256 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024256 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024256 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13677.002744 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13677.002744 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13677.002744 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13677.002744 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13677.002744 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1135,32 +1122,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 331421 # number of writebacks -system.cpu1.icache.writebacks::total 331421 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331973 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 331973 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 331973 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 331973 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 331973 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 331973 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209863000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209863000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4209863000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209863000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4209863000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024266 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024266 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024266 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.341555 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.341555 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.341555 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 331505 # number of writebacks +system.cpu1.icache.writebacks::total 331505 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 332057 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 332057 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 332057 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 332057 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 332057 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 332057 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209487500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209487500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209487500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4209487500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209487500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4209487500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024256 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024256 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024256 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024256 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12677.002744 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12677.002744 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12677.002744 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1174,37 +1161,37 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55680 # Transaction distribution -system.iobus.trans_dist::WriteResp 55680 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14048 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7379 # Transaction distribution +system.iobus.trans_dist::ReadResp 7379 # Transaction distribution +system.iobus.trans_dist::WriteReq 55684 # Transaction distribution +system.iobus.trans_dist::WriteResp 55684 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42672 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126106 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 126126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56264 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82434 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 82507 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15110500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2744131 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15127500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1214,29 +1201,29 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15842500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15843000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6039500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6055000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215050235 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215669663 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28524000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28540000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.566864 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.566874 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1775104150000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.566864 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775103309000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566874 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035430 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035430 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1252,8 +1239,8 @@ system.iocache.overall_misses::tsunami.ide 175 # system.iocache.overall_misses::total 175 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428160352 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428160352 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5245212780 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5245212780 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles @@ -1276,17 +1263,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130635.356950 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130635.356950 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126232.498556 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126232.498556 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1302,8 +1289,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 175 system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350560352 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3350560352 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165805993 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165805993 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number 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0.767857 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867538 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959585 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967205 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480860 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139642 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.415708 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018201 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002829 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013193 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291658 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002953 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260136 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018201 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.330320 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002829 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.048182 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.172978 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018201 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.330320 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002829 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.048182 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.172978 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71657.478992 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71685.769657 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71668.165656 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71322.894168 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71535.407725 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71429.494080 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.551649 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122041.814721 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117463.339492 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121224.486760 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113986.583879 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118393.175074 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113992.046006 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114927.472601 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121892.174760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115275.081644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114927.472601 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121892.174760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115275.081644 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208703.460452 # average ReadReq mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941102 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767698 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866957 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.958592 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975866 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967170 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480886 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139579 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415710 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013178 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291657 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002954 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260147 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330323 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172959 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330323 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002795 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048176 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172959 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68753.701211 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68858.917725 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68793.539619 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68479.481641 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68922.043011 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68701.239224 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117141.871853 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121624.666751 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117429.294121 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121465.120682 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113994.501670 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118394.658754 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113999.955862 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121368.002239 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114930.755419 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122773.707974 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121492.147553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115277.837125 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208711.191081 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208557.377049 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215865.074212 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.614098 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217864.807475 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213026.091825 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223469.128679 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 214723.342399 # average overall mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208565.102721 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215871.939911 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.166069 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217869.374469 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213032.484611 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223468.695903 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214727.830896 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292693 # Transaction distribution -system.membus.trans_dist::WriteReq 14128 # Transaction distribution -system.membus.trans_dist::WriteResp 14128 # Transaction distribution -system.membus.trans_dist::WritebackDirty 120940 # Transaction distribution -system.membus.trans_dist::CleanEvict 261948 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16888 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11786 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7203 # Transaction distribution -system.membus.trans_dist::ReadExReq 123166 # Transaction distribution -system.membus.trans_dist::ReadExResp 122293 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285495 # Transaction distribution +system.membus.trans_dist::ReadReq 7204 # Transaction distribution +system.membus.trans_dist::ReadResp 292685 # Transaction distribution +system.membus.trans_dist::WriteReq 14132 # Transaction distribution +system.membus.trans_dist::WriteResp 14132 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120936 # Transaction distribution +system.membus.trans_dist::CleanEvict 262098 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16894 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11785 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 123162 # Transaction distribution +system.membus.trans_dist::ReadExResp 122291 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42652 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193065 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1235717 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1360544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82434 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31153280 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31235714 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1185820 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1228492 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83437 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1311929 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82507 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31152000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31234507 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33893954 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22770 # Total snoops (count) -system.membus.snoop_fanout::samples 883282 # Request fanout histogram +system.membus.pkt_size::total 33892747 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22774 # Total snoops (count) +system.membus.snoop_fanout::samples 883255 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 883282 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883255 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 883282 # Request fanout histogram -system.membus.reqLayer0.occupancy 40488000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883255 # Request fanout histogram +system.membus.reqLayer0.occupancy 40521000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1327709899 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1327609723 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2192713302 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2178253250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69791959 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 898617 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4790563 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2395444 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 362000 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1241 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1181 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 4790864 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395593 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 361656 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1242 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1182 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2107005 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14128 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14128 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 913531 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 746399 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 756600 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17054 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11849 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28903 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297620 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297620 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019067 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1080755 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7204 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107176 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14132 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14132 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 913504 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1018097 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 816785 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17065 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11848 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28913 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297603 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297603 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019283 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080704 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1917007 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544626 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867499 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539645 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6868777 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 78714432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118015028 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34273664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604942 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 249608066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 484792 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2873097 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.137110 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.344206 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2061018 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3585479 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 995618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 558881 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7200996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 87922688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118013949 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 42467904 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18601358 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 267005899 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484765 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2873241 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.136986 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.344076 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2479406 86.30% 86.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393455 13.69% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2479885 86.31% 86.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393120 13.68% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2873097 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223463995 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2873241 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223821996 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1030900979 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1031213250 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1802313287 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1802267282 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 499097220 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 499176813 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 293862892 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293823888 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index bc2bfd41e..04e45bbeb 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,13 +4,13 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 450874 # Simulator instruction rate (inst/s) -host_op_rate 450874 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15578984909 # Simulator tick rate (ticks/s) -host_mem_usage 311244 # Number of bytes of host memory used -host_seconds 124.61 # Real time elapsed on the host -sim_insts 56182743 # Number of instructions simulated -sim_ops 56182743 # Number of ops (including micro ops) simulated +host_inst_rate 1255554 # Simulator instruction rate (inst/s) +host_op_rate 1255553 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43383023327 # Simulator tick rate (ticks/s) +host_mem_usage 332188 # Number of bytes of host memory used +host_seconds 44.75 # Real time elapsed on the host +sim_insts 56182685 # Number of instructions simulated +sim_ops 56182685 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 844800 # Number of bytes read from this memory @@ -51,7 +51,7 @@ system.physmem.bytesReadSys 25702272 # To system.physmem.bytesWrittenSys 7410752 # Total written bytes from the system interface side system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 303100 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25225 # Per bank write bursts system.physmem.perBankRdBursts::1 25628 # Per bank write bursts system.physmem.perBankRdBursts::2 25541 # Per bank write bursts @@ -85,7 +85,7 @@ system.physmem.perBankWrBursts::13 7822 # Pe system.physmem.perBankWrBursts::14 7863 # Per bank write bursts system.physmem.perBankWrBursts::15 7687 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 16 # Number of times write queue was full causing retry +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry system.physmem.totGap 1941264122500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) @@ -148,123 +148,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64945 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.715729 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.174215 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.042967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15358 23.65% 23.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11454 17.64% 41.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4958 7.63% 48.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3153 4.85% 53.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4205 6.47% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1430 2.20% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19871 30.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64945 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2951.127633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64912 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.974858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.431433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.117715 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15298 23.57% 23.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11509 17.73% 41.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4967 7.65% 48.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3096 4.77% 53.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2467 3.80% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4201 6.47% 63.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1427 2.20% 66.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2061 3.18% 69.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19886 30.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64912 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5093 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.826036 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2956.913485 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5090 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5113 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5113 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.640524 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.158069 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.669047 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4483 87.68% 87.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 26 0.51% 88.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 11 0.22% 88.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 181 3.54% 91.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 5 0.10% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.39% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 39 0.76% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.12% 93.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 12 0.23% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 31 0.61% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.06% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.18% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.02% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 22 0.43% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.53% 95.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.04% 95.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 26 0.51% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.06% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 161 3.15% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.10% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.04% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.06% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.08% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 4 0.08% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 11 0.22% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.10% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads -system.physmem.totQLat 2718840250 # Total ticks spent queuing -system.physmem.totMemAccLat 10246609000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 5093 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5093 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.729433 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.333640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.082746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 4499 88.34% 88.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 29 0.57% 88.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 20 0.39% 89.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 41 0.81% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 209 4.10% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 11 0.22% 94.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 11 0.22% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 30 0.59% 95.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 184 3.61% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.12% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 5 0.10% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 4 0.08% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.02% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 8 0.16% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.10% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 5 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.10% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-199 2 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 7 0.14% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-247 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 4 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5093 # Writes before turning the bus around for reads +system.physmem.totQLat 2720413750 # Total ticks spent queuing +system.physmem.totMemAccLat 10248182500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6772.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6775.95 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25522.03 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25525.95 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -274,55 +263,55 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing -system.physmem.readRowHits 358828 # Number of row buffer hits during reads -system.physmem.writeRowHits 93469 # Number of row buffer hits during writes +system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing +system.physmem.readRowHits 358846 # Number of row buffer hits during reads +system.physmem.writeRowHits 93484 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes +system.physmem.writeRowHitRate 80.73 # Row buffer hit rate for writes system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240377760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131158500 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 240264360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131096625 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71534855790 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1102015656000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302656006370 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.030850 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1833021874000 # Time in different power states +system.physmem_0.actBackEnergy 71567841690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1101986721000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302659881995 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.032847 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1832974788000 # Time in different power states system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43430562250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43477648250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250606440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136739625 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 250470360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136665375 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72705843270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1100988474000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302818763615 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.114691 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831312114000 # Time in different power states +system.physmem_1.actBackEnergy 72629101890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1101055791000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302809128905 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.109728 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831423384000 # Time in different power states system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45140322250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45029052250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9064657 # DTB read hits +system.cpu.dtb.read_hits 9064642 # DTB read hits system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6356207 # DTB write hits +system.cpu.dtb.write_hits 6356200 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15420864 # DTB hits +system.cpu.dtb.data_hits 15420842 # DTB hits system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020784 # DTB accesses @@ -358,10 +347,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860509805500 95.84% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79900901000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1860509936500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 94066500 0.00% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 770529000 0.04% 95.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79900730000 4.12% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -426,32 +415,32 @@ system.cpu.kern.mode_switch_good::kernel 0.323121 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391952 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 48611852500 2.50% 2.50% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5602941000 0.29% 2.79% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1887060466500 97.21% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 48613441500 2.50% 2.50% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5603081000 0.29% 2.79% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1887058737500 97.21% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.committedInsts 56182743 # Number of instructions committed -system.cpu.committedOps 56182743 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52054633 # Number of integer alu accesses +system.cpu.committedInsts 56182685 # Number of instructions committed +system.cpu.committedOps 56182685 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52054580 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483394 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6468678 # number of instructions that are conditional controls -system.cpu.num_int_insts 52054633 # number of integer instructions +system.cpu.num_func_calls 1483390 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6468674 # number of instructions that are conditional controls +system.cpu.num_int_insts 52054580 # number of integer instructions system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71322499 # number of times the integer registers were read -system.cpu.num_int_register_writes 38520900 # number of times the integer registers were written +system.cpu.num_int_register_reads 71322431 # number of times the integer registers were read +system.cpu.num_int_register_writes 38520860 # number of times the integer registers were written system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15473474 # number of memory refs -system.cpu.num_load_insts 9101503 # Number of load instructions -system.cpu.num_store_insts 6371971 # Number of store instructions -system.cpu.num_idle_cycles 3583834697.998154 # Number of idle cycles -system.cpu.num_busy_cycles 298717294.001846 # Number of busy cycles -system.cpu.not_idle_fraction 0.076938 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.923062 # Percentage of idle cycles -system.cpu.Branches 8422724 # Number of branches fetched -system.cpu.op_class::No_OpClass 3200638 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36231019 64.47% 70.17% # Class of executed instruction +system.cpu.num_mem_refs 15473452 # number of memory refs +system.cpu.num_load_insts 9101488 # Number of load instructions +system.cpu.num_store_insts 6371964 # Number of store instructions +system.cpu.num_idle_cycles 3583831790.000154 # Number of idle cycles +system.cpu.num_busy_cycles 298720201.999846 # Number of busy cycles +system.cpu.not_idle_fraction 0.076939 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.923061 # Percentage of idle cycles +system.cpu.Branches 8422715 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200634 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36230987 64.47% 70.17% # Class of executed instruction system.cpu.op_class::IntMult 61043 0.11% 70.28% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction system.cpu.op_class::FloatAdd 38085 0.07% 70.35% # Class of executed instruction @@ -480,16 +469,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9328633 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6378052 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::MemRead 9328618 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6378045 11.35% 98.30% # Class of executed instruction system.cpu.op_class::IprAccess 953470 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56194576 # Class of executed instruction -system.cpu.dcache.tags.replacements 1390387 # number of replacements +system.cpu.op_class::total 56194518 # Class of executed instruction +system.cpu.dcache.tags.replacements 1390402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.973391 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14048998 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390899 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.100660 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14048961 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.100525 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 145150500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.973391 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999948 # Average percentage of cache occupancy @@ -499,72 +488,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63150492 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63150492 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5852271 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5852271 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183035 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183035 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 63150419 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63150419 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7814383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7814383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5852265 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5852265 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183036 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183036 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199260 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199260 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13666686 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13666686 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13666686 # number of overall hits -system.cpu.dcache.overall_hits::total 13666686 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069342 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069342 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304328 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304328 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17247 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17247 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373670 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses -system.cpu.dcache.overall_misses::total 1373670 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44771016500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44771016500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634519000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17634519000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232810500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232810500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62405535500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62405535500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62405535500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62405535500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6156599 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13666648 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13666648 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13666648 # number of overall hits +system.cpu.dcache.overall_hits::total 13666648 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069359 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069359 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304327 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304327 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17246 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17246 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1373686 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373686 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373686 # number of overall misses +system.cpu.dcache.overall_misses::total 1373686 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44772641000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44772641000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17635172000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232797500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232797500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62407813000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62407813000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62407813000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62407813000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8883742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8883742 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6156592 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6156592 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200282 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200282 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199260 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199260 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15040356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15040356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15040356 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15040356 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120370 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120370 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 15040334 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15040334 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15040334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15040334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120373 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120373 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049431 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.049431 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086114 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086114 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45429.786994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45429.786994 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086109 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086109 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41868.671793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41868.671793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57948.101877 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57948.101877 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.637365 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.637365 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45430.915799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45430.915799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45430.915799 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,74 +562,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834936 # number of writebacks -system.cpu.dcache.writebacks::total 834936 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069342 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069342 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304328 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304328 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17247 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373670 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373670 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373670 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373670 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 834944 # number of writebacks +system.cpu.dcache.writebacks::total 834944 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069359 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069359 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304327 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304327 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17246 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17246 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373686 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373686 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373686 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373686 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701674500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330191000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215563500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215563500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031865500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61031865500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031865500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61031865500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43703282000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43703282000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215551500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215551500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61034127000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61034127000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61034127000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61034127000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699445500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699445500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699465000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120373 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120373 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049431 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086114 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086114 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086109 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086109 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40868.671793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40868.671793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56948.101877 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.637365 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.637365 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44430.915799 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44430.915799 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857 # average overall mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225058.168445 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225058.168445 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223087.800760 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223087.800760 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 928920 # number of replacements -system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55264986 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929431 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.461096 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 928931 # number of replacements +system.cpu.icache.tags.tagsinuse 506.355616 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55264917 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929442 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.460318 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 58592056500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 506.355618 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 506.355616 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.988976 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -649,44 +638,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57124168 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57124168 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55264986 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55264986 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55264986 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55264986 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55264986 # number of overall hits -system.cpu.icache.overall_hits::total 55264986 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929591 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929591 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929591 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses -system.cpu.icache.overall_misses::total 929591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686841500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13686841500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13686841500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13686841500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13686841500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13686841500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56194577 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56194577 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56194577 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016542 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.509049 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14723.509049 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14723.509049 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14723.509049 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57124121 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57124121 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55264917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55264917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55264917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55264917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55264917 # number of overall hits +system.cpu.icache.overall_hits::total 55264917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929602 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929602 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929602 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929602 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929602 # number of overall misses +system.cpu.icache.overall_misses::total 929602 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686117000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686117000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686117000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686117000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686117000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686117000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56194519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56194519 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56194519 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56194519 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56194519 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56194519 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016543 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016543 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016543 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016543 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016543 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016543 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14722.555459 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14722.555459 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14722.555459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14722.555459 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14722.555459 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -695,44 +684,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 928920 # number of writebacks -system.cpu.icache.writebacks::total 928920 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929591 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929591 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929591 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12757250500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12757250500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12757250500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12757250500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12757250500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12757250500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 928931 # number of writebacks +system.cpu.icache.writebacks::total 928931 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929602 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929602 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929602 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929602 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929602 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929602 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756515000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12756515000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756515000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12756515000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12756515000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13722.555459 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13722.555459 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13722.555459 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13722.555459 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 336393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65234.360010 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65234.360001 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3930403 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. 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+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071505 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.995397 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id @@ -742,26 +731,26 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5220 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3221 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55822 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37812565 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37812565 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 834936 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 834936 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928699 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928699 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 37812972 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 37812972 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 834944 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 928709 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 928709 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187491 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187491 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916371 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916371 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 814618 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 814618 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916371 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002109 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918480 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916371 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002109 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918480 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187490 # number of ReadExReq hits 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system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 116820 # number of ReadExReq misses @@ -776,66 +765,66 @@ system.cpu.l2cache.demand_misses::total 401991 # nu system.cpu.l2cache.overall_misses::cpu.inst 13200 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses system.cpu.l2cache.overall_misses::total 401991 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14900653000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727668500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727668500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719834000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1727668500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48620487000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50348155500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1727668500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48620487000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50348155500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 928699 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 315000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 315000 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14901349500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14901349500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1726796000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1726796000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33721236500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33721236500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1726796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48622586000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50349382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1726796000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48622586000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50349382000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 834944 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 928709 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 928709 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304311 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929571 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929571 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1086589 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929571 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390900 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320471 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929571 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390900 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320471 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304310 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929582 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 929582 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1086605 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 929582 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390915 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320497 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 929582 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390915 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320497 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383884 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383884 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014200 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014200 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250298 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250298 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250294 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250294 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014200 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173237 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279522 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173235 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014200 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279522 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173235 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24230.769231 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24230.769231 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127558.204931 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127558.204931 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130817.878788 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130817.878788 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123988.353538 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123988.353538 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125250.023010 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130817.878788 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125060.986494 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125250.023010 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,106 +855,106 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9653 system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732453000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732453000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595668500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595668500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000124000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000124000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595668500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732577000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46328245500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595668500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732577000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46328245500 # number of overall MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 893500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 893500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13733149500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13733149500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1594796000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1594796000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31001526500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31001526500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1594796000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44734676000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46329472000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1594796000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44734676000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46329472000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501699500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501699500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061396500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501719000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501719000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383884 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014200 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250298 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250298 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250294 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250294 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173237 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173235 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014200 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279522 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173235 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68730.769231 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68730.769231 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117558.204931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117558.204931 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120817.878788 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120817.878788 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113988.353538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113988.353538 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120817.878788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115060.986494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115250.023010 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256 # average overall mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213549.829069 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213549.829069 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211163.179159 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211163.179159 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4639867 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319499 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1136 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1136 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023267 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023294 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9653 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 950745 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 816471 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 928931 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 817743 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929591 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304310 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 929602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1086778 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787861 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4204279 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6992140 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118929280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142508140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261437420 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 419996 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2756910 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2788115 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4205589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6993704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118944832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142509612 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 261454444 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 419988 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2756928 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031841 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.031847 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2754112 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2798 0.10% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2754129 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2799 0.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2756910 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4096881500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2756928 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4096926500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394386500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1394403000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098115000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2098137500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1019,15 +1008,15 @@ system.iobus.reqLayer6.occupancy 10000 # La system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15817000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15817500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6038000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 215014002 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215662167 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -1038,7 +1027,7 @@ system.iocache.tags.tagsinuse 1.339384 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1774106672000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 1774106669000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::tsunami.ide 1.339384 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.083712 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.083712 # Average percentage of cache occupancy @@ -1057,8 +1046,8 @@ system.iocache.overall_misses::tsunami.ide 173 # system.iocache.overall_misses::total 173 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21742883 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21742883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428926119 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5428926119 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5244713284 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5244713284 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::tsunami.ide 21742883 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 21742883 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::tsunami.ide 21742883 # number of overall miss cycles @@ -1081,17 +1070,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125681.404624 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 125681.404624 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130653.786075 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130653.786075 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 126220.477570 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126220.477570 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency system.iocache.demand_avg_miss_latency::total 125681.404624 # average overall miss latency system.iocache.overall_avg_miss_latency::tsunami.ide 125681.404624 # average overall miss latency system.iocache.overall_avg_miss_latency::total 125681.404624 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 14.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1107,8 +1096,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13092883 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 13092883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351326119 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351326119 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3165314984 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3165314984 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 13092883 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 13092883 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 13092883 # number of overall MSHR miss cycles @@ -1123,8 +1112,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 75681.404624 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80653.786075 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80653.786075 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 76177.199268 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76177.199268 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 75681.404624 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75681.404624 # average overall mshr miss latency @@ -1135,20 +1124,19 @@ system.membus.trans_dist::ReadResp 292274 # Tr system.membus.trans_dist::WriteReq 9653 # Transaction distribution system.membus.trans_dist::WriteResp 9653 # Transaction distribution system.membus.trans_dist::WritebackDirty 115793 # Transaction distribution -system.membus.trans_dist::CleanEvict 261400 # Transaction distribution +system.membus.trans_dist::CleanEvict 261560 # Transaction distribution system.membus.trans_dist::UpgradeReq 150 # Transaction distribution -system.membus.trans_dist::UpgradeResp 150 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 116683 # Transaction distribution system.membus.trans_dist::ReadExResp 116683 # Transaction distribution system.membus.trans_dist::ReadSharedReq 285344 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33166 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172569 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1297386 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172421 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1255846 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44588 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455296 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499884 # Cumulative packet size per connected master and slave (bytes) @@ -1156,24 +1144,24 @@ system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 33157612 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 837681 # Request fanout histogram +system.membus.snoop_fanout::samples 837673 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 837681 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 837673 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 837681 # Request fanout histogram -system.membus.reqLayer0.occupancy 30116000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 837673 # Request fanout histogram +system.membus.reqLayer0.occupancy 30122500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1287200967 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143289352 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143013000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index e4317ec15..f7d0d7b39 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 624684 # Simulator instruction rate (inst/s) -host_op_rate 760453 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12180447765 # Simulator tick rate (ticks/s) -host_mem_usage 563036 # Number of bytes of host memory used -host_seconds 228.55 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1852974 # Simulator instruction rate (inst/s) +host_op_rate 2255698 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36130480826 # Simulator tick rate (ticks/s) +host_mem_usage 581484 # Number of bytes of host memory used +host_seconds 77.05 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 10029 # Table walker walks requested -system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 10028 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526223 # DTB read hits -system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124452 # DTB write hits +system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_misses 8580 # DTB read misses +system.cpu.dtb.write_hits 23124104 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534804 # DTB read accesses -system.cpu.dtb.write_accesses 23125900 # DTB write accesses +system.cpu.dtb.read_accesses 31534529 # DTB read accesses +system.cpu.dtb.write_accesses 23125552 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650675 # DTB hits -system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660704 # DTB accesses +system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.misses 10028 # DTB misses +system.cpu.dtb.accesses 54660081 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039346 # ITB inst hits +system.cpu.itb.inst_hits 147038166 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044108 # ITB inst accesses -system.cpu.itb.hits 147039346 # DTB hits +system.cpu.itb.inst_accesses 147042928 # ITB inst accesses +system.cpu.itb.hits 147038166 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044108 # DTB accesses -system.cpu.numCycles 5567737188 # number of cpu cycles simulated +system.cpu.itb.accesses 147042928 # DTB accesses +system.cpu.numCycles 5567712151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.committedInsts 142772879 # Number of instructions committed -system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses +system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.committedInsts 142771651 # Number of instructions committed +system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873899 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162683 # number of integer instructions +system.cpu.num_func_calls 16873962 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written +system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written -system.cpu.num_mem_refs 55939276 # number of memory refs -system.cpu.num_load_insts 31855884 # Number of load instructions -system.cpu.num_store_insts 24083392 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles -system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles +system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written +system.cpu.num_mem_refs 55938616 # number of memory refs +system.cpu.num_load_insts 31855585 # Number of load instructions +system.cpu.num_store_insts 24083031 # Number of store instructions +system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles +system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396981 # Number of branches fetched +system.cpu.Branches 36396978 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.op_class::total 177218432 # Class of executed instruction +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits -system.cpu.dcache.overall_hits::total 52864242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits +system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses -system.cpu.dcache.overall_misses::total 814074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks -system.cpu.dcache.writebacks::total 682040 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks +system.cpu.dcache.writebacks::total 682017 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699214 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1698998 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits -system.cpu.icache.overall_hits::total 145342721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses -system.cpu.icache.overall_misses::total 1699732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits +system.cpu.icache.overall_hits::total 145341757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses +system.cpu.icache.overall_misses::total 1699516 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu.icache.writebacks::total 1699214 # number of writebacks +system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu.icache.writebacks::total 1698998 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses system.cpu.l2cache.overall_misses::total 181651 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks -system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks +system.cpu.l2cache.writebacks::total 101950 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182974 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182975 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index c3e49583c..df10533fc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.802895 # Number of seconds simulated -sim_ticks 2802894699500 # Number of ticks simulated -final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.802883 # Number of seconds simulated +sim_ticks 2802882879000 # Number of ticks simulated +final_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 526774 # Simulator instruction rate (inst/s) -host_op_rate 641866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10055912327 # Simulator tick rate (ticks/s) -host_mem_usage 575028 # Number of bytes of host memory used -host_seconds 278.73 # Real time elapsed on the host -sim_insts 146828240 # Number of instructions simulated -sim_ops 178908039 # Number of ops (including micro ops) simulated +host_inst_rate 1272297 # Simulator instruction rate (inst/s) +host_op_rate 1550275 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24287502010 # Simulator tick rate (ticks/s) +host_mem_usage 596572 # Number of bytes of host memory used +host_seconds 115.40 # Real time elapsed on the host +sim_insts 146828562 # Number of instructions simulated +sim_ops 178908371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1108644 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9410404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1109732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9413156 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152660 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1082192 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11757100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1108644 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1262520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8452288 # Number of bytes written to this memory +system.physmem.bytes_read::total 11759340 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1109732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152660 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1262392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8477312 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8469852 # Number of bytes written to this memory +system.physmem.bytes_written::total 8494876 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25776 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 147557 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 147600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2540 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16929 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192852 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 132067 # Number of write requests responded to by this memory +system.physmem.num_reads::total 192887 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 132458 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136458 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136849 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 395535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3357388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 395925 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3358384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 386100 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4194628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 395535 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 450434 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3015557 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4195445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 395925 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54465 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 450391 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3024497 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3021823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3015557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3030764 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3024497 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 395535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3363640 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 395925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3364636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 386114 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7216451 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7226208 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -118,29 +118,29 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7967 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 7964 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339720 # DTB read hits -system.cpu0.dtb.read_misses 6874 # DTB read misses -system.cpu0.dtb.write_hits 16391078 # DTB write hits +system.cpu0.dtb.read_hits 20339777 # DTB read hits +system.cpu0.dtb.read_misses 6871 # DTB read misses +system.cpu0.dtb.write_hits 16391027 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -151,12 +151,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346594 # DTB read accesses -system.cpu0.dtb.write_accesses 16392171 # DTB write accesses +system.cpu0.dtb.read_accesses 20346648 # DTB read accesses +system.cpu0.dtb.write_accesses 16392120 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36730798 # DTB hits -system.cpu0.dtb.misses 7967 # DTB misses -system.cpu0.dtb.accesses 36738765 # DTB accesses +system.cpu0.dtb.hits 36730804 # DTB hits +system.cpu0.dtb.misses 7964 # DTB misses +system.cpu0.dtb.accesses 36738768 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -204,7 +204,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97439331 # ITB inst hits +system.cpu0.itb.inst_hits 97439598 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -221,40 +221,40 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses -system.cpu0.itb.hits 97439331 # DTB hits +system.cpu0.itb.inst_accesses 97442956 # ITB inst accesses +system.cpu0.itb.hits 97439598 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97442689 # DTB accesses -system.cpu0.numCycles 5605791368 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442956 # DTB accesses +system.cpu0.numCycles 5605767724 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed -system.cpu0.committedInsts 95426926 # Number of instructions committed -system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed +system.cpu0.committedInsts 95427136 # Number of instructions committed +system.cpu0.committedOps 115560651 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762921 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000180 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100762696 # number of integer instructions +system.cpu0.num_func_calls 8000357 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204240 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762921 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457857 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135716 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written -system.cpu0.num_mem_refs 37873810 # number of memory refs -system.cpu0.num_load_insts 20597310 # Number of load instructions -system.cpu0.num_store_insts 17276500 # Number of store instructions -system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles -system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles +system.cpu0.num_cc_register_reads 349972220 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907498 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873797 # number of memory refs +system.cpu0.num_load_insts 20597358 # Number of load instructions +system.cpu0.num_store_insts 17276439 # Number of store instructions +system.cpu0.num_idle_cycles 5488182951.223861 # Number of idle cycles +system.cpu0.num_busy_cycles 117584772.776139 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941499 # Number of branches fetched +system.cpu0.Branches 21941714 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction -system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887557 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction @@ -282,18 +282,18 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597358 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276439 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116882065 # Class of executed instruction -system.cpu0.dcache.tags.replacements 693486 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. +system.cpu0.op_class::total 116882349 # Class of executed instruction +system.cpu0.dcache.tags.replacements 693475 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853481 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932424 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776797 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853481 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -301,60 +301,60 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690389 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690389 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363050 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363050 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34798930 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34798930 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145023 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145023 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295796 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295796 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18435 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18435 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses -system.cpu0.dcache.overall_misses::total 769220 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses +system.cpu0.dcache.tags.tag_accesses 74113882 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113882 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108626 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108626 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690357 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690357 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798983 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798983 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145063 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145063 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373096 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373096 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295789 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295789 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 668885 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 668885 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 769207 # number of overall misses +system.cpu0.dcache.overall_misses::total 769207 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481722 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986146 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986146 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 35467868 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467868 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914270 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914270 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048324 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048324 # miss rate for StoreCondReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses @@ -367,16 +367,16 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 693486 # number of writebacks -system.cpu0.dcache.writebacks::total 693486 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks +system.cpu0.dcache.writebacks::total 693475 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1109735 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1109624 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110136 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.774769 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -384,32 +384,32 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits -system.cpu0.icache.overall_hits::total 96331417 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses -system.cpu0.icache.overall_misses::total 1110256 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 195994025 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195994025 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331795 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331795 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331795 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331795 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331795 # number of overall hits +system.cpu0.icache.overall_hits::total 96331795 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110145 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110145 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110145 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110145 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110145 # number of overall misses +system.cpu0.icache.overall_misses::total 1110145 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441940 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441940 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441940 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441940 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441940 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441940 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,8 +418,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1109735 # number of writebacks -system.cpu0.icache.writebacks::total 1109735 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks 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of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.282500 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 249486 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16123.886747 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2730668 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 265599 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.281168 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 16127.358870 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.556147 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076637 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.984336 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000156 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984497 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16112 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.758477 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070793 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.984012 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000107 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984124 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16108 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5452 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7536 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2638 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983398 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 59699237 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 59699237 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10182 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4496 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 14678 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 510201 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 510201 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1265145 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1265145 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94344 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94344 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068613 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1068613 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352244 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 352244 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10182 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4496 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1068613 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446588 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1529879 # number of demand (read+write) hits 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of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1265145 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26273 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18435 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18435 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) 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accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1874967 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.028102 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.022900 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5529 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7406 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2667 # Occupied blocks per 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10175 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4509 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1068362 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446590 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1529636 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 118 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26269 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26269 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175160 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175160 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41783 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 41783 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127928 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 127928 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 118 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 41783 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303088 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 345205 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 118 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 41783 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303088 # number of overall misses +system.cpu0.l2cache.overall_misses::total 345205 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 510631 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 510631 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1264603 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1264603 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26269 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26269 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110145 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1110145 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480158 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 480158 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110145 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1874841 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110145 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1874841 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025502 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.022240 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649959 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649959 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037508 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037508 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266412 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266412 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.028102 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037508 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404302 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.184050 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020585 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.028102 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037508 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404302 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.184050 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649896 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649896 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037637 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037637 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266429 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266429 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025502 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037637 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404291 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.184125 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025502 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037637 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404291 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.184125 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,50 +557,50 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192911 # number of writebacks -system.cpu0.l2cache.writebacks::total 192911 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks +system.cpu0.l2cache.writebacks::total 193020 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3720245 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860324 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27875 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 218142 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215248 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2894 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution +system.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 218277 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215192 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3085 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651713 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 510201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1265145 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26273 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18435 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3327246 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2395284 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.trans_dist::WritebackDirty 510631 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1292468 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26269 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480158 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347958 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402091 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5764166 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 140768632 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92116612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5791673 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142101304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552324 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 232968516 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 623122 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4318148 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.066969 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.252635 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 234736876 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 623160 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4317939 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.067042 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.252935 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 4031861 93.37% 93.37% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 283393 6.56% 99.93% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 2894 0.07% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 4031542 93.37% 93.37% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 283312 6.56% 99.93% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3085 0.07% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4318148 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4317939 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -630,29 +630,29 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3358 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 3359 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173916 # DTB read hits -system.cpu1.dtb.read_misses 2852 # DTB read misses -system.cpu1.dtb.write_hits 7587209 # DTB write hits +system.cpu1.dtb.read_hits 12173929 # DTB read hits +system.cpu1.dtb.read_misses 2853 # DTB read misses +system.cpu1.dtb.write_hits 7587213 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -663,12 +663,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176768 # DTB read accesses -system.cpu1.dtb.write_accesses 7587715 # DTB write accesses +system.cpu1.dtb.read_accesses 12176782 # DTB read accesses +system.cpu1.dtb.write_accesses 7587719 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761125 # DTB hits -system.cpu1.dtb.misses 3358 # DTB misses -system.cpu1.dtb.accesses 19764483 # DTB accesses +system.cpu1.dtb.hits 19761142 # DTB hits +system.cpu1.dtb.misses 3359 # DTB misses +system.cpu1.dtb.accesses 19764501 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -716,7 +716,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671575 # ITB inst hits +system.cpu1.itb.inst_hits 53671686 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -733,40 +733,40 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses -system.cpu1.itb.hits 53671575 # DTB hits +system.cpu1.itb.inst_accesses 53673420 # ITB inst accesses +system.cpu1.itb.hits 53671686 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673309 # DTB accesses -system.cpu1.numCycles 5605320274 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673420 # DTB accesses +system.cpu1.numCycles 5605296633 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed -system.cpu1.committedInsts 51401314 # Number of instructions committed -system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses +system.cpu1.committedInsts 51401426 # Number of instructions committed +system.cpu1.committedOps 63347720 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984340 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170855 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984241 # number of integer instructions +system.cpu1.num_func_calls 9170857 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967107 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984340 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674879 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298438 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026381 # number of memory refs -system.cpu1.num_load_insts 12289537 # Number of load instructions -system.cpu1.num_store_insts 7736844 # Number of store instructions -system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles -system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268976 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894428 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026400 # number of memory refs +system.cpu1.num_load_insts 12289552 # Number of load instructions +system.cpu1.num_store_insts 7736848 # Number of store instructions +system.cpu1.num_idle_cycles 5539683011.597479 # Number of idle cycles +system.cpu1.num_busy_cycles 65613621.402521 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217493 # Number of branches fetched +system.cpu1.Branches 15217504 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction -system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401392 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction @@ -794,80 +794,80 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289552 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736848 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459464 # Class of executed instruction -system.cpu1.dcache.tags.replacements 191938 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. +system.cpu1.op_class::total 65459571 # Class of executed instruction +system.cpu1.dcache.tags.replacements 191946 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503521 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.422366 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397500 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397500 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits +system.cpu1.dcache.tags.tag_accesses 39752021 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39752021 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858700 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858700 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397505 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397505 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256194 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256194 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306293 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306293 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92462 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92462 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72417 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72417 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256205 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256205 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306305 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306305 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92461 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92461 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259811 # number of overall misses -system.cpu1.dcache.overall_misses::total 259811 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22562 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22562 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229099 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229099 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses +system.cpu1.dcache.overall_misses::total 259817 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995338 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995338 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489966 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489966 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485304 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485304 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566122 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566122 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237547 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237547 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -878,42 +878,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 191938 # number of writebacks -system.cpu1.dcache.writebacks::total 191938 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks +system.cpu1.dcache.writebacks::total 191946 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 523373 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 523401 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.445971 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits -system.cpu1.icache.overall_hits::total 53148780 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses -system.cpu1.icache.overall_misses::total 523885 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses +system.cpu1.icache.tags.tag_accesses 107869465 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869465 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148863 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148863 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148863 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148863 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148863 # number of overall hits +system.cpu1.icache.overall_hits::total 53148863 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses +system.cpu1.icache.overall_misses::total 523913 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672776 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672776 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672776 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672776 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672776 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672776 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -928,8 +928,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 523373 # number of writebacks -system.cpu1.icache.writebacks::total 523373 # number of writebacks +system.cpu1.icache.writebacks::writebacks 523401 # number of writebacks +system.cpu1.icache.writebacks::total 523401 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified @@ -937,127 +937,127 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47555 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15235.297156 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1184961 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62593 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 18.931206 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 47378 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15226.816500 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1184475 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 62425 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.974369 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 15230.950549 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.335617 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010990 # Average occupied blocks per requestor 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# number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 118856 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634736 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 271 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 607 # number of ReadReq misses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9441 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5060 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917175 # Percentage of cache occupancy per task id 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of overall hits +system.cpu1.l2cache.overall_hits::total 634980 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 268 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43853 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43853 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13539 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13539 # number of 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WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 583081 # number of WritebackClean accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) 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accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 766309 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124084 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.098844 # miss rate for ReadReq accesses +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22562 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22562 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) 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accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.122319 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.098441 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689339 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689339 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025843 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025843 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.426103 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.426103 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124084 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025843 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496976 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171697 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084913 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124084 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025843 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496976 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171697 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687778 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.687778 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025708 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025708 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425947 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425947 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.122319 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025708 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496439 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171432 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.122319 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025708 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496439 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171432 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,50 +1066,50 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32818 # number of writebacks -system.cpu1.l2cache.writebacks::total 32818 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks +system.cpu1.l2cache.writebacks::total 32706 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1533421 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773256 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 165978 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164041 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_snoops 166217 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2071 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 121109 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 583044 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 121108 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 594239 # Transaction distribution system.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1562572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 776509 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22562 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51408 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778800 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2357775 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66454020 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27282414 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2369077 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 93773822 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 347349 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1819817 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.108136 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313960 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347790 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1820349 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.108308 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.314409 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1624967 89.29% 89.29% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 192913 10.60% 99.89% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1937 0.11% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1625261 89.28% 89.28% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 193017 10.60% 99.89% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2071 0.11% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1819817 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1820349 # Request fanout histogram system.iobus.trans_dist::ReadReq 30995 # Transaction distribution system.iobus.trans_dist::ReadResp 30995 # Transaction distribution system.iobus.trans_dist::WriteReq 59419 # Transaction distribution @@ -1161,14 +1161,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1209,175 +1209,175 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107037 # number of replacements -system.l2c.tags.tagsinuse 62176.956554 # Cycle average of tags in use -system.l2c.tags.total_refs 241620 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 167464 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.442818 # Average number of references to valid blocks. +system.l2c.tags.replacements 107729 # number of replacements +system.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use +system.l2c.tags.total_refs 243914 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168410 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.448334 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 47954.224141 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010653 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030815 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7778.474758 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4056.241083 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1664.556464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 718.418639 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.731723 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48132.772899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010469 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7764.318269 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4071.663088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1666.007629 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 770.829870 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.734448 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.118690 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.061893 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010962 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.948745 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.118474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.062129 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.025421 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011762 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.952311 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60421 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60675 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1839 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45269 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1869 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13225 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45497 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921951 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5183068 # Number of tag accesses -system.l2c.tags.data_accesses 5183068 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 225729 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 225729 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 511 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 64 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 575 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 72 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13894 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3132 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17026 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 74 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 68 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 24882 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 76059 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 27 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 11145 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 11759 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 124050 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 74 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 24882 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89953 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 27 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11145 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14891 # number of demand (read+write) hits -system.l2c.demand_hits::total 141076 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 74 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu0.inst 24882 # number of overall hits -system.l2c.overall_hits::cpu0.data 89953 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 27 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11145 # number of overall hits -system.l2c.overall_hits::cpu1.data 14891 # number of overall hits -system.l2c.overall_hits::total 141076 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 10043 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3295 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13338 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 754 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1932 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136525 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15837 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152362 # number of ReadExReq misses +system.l2c.tags.occ_task_id_percent::1024 0.925827 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5179303 # Number of tag accesses +system.l2c.tags.data_accesses 5179303 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 225726 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 225726 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 564 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 115 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 679 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 81 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13900 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3040 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16940 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 58 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 25005 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 76077 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 34 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 11094 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11733 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 124113 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 58 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 25005 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 89977 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11094 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14773 # number of demand (read+write) hits +system.l2c.demand_hits::total 141053 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 58 # number of overall hits +system.l2c.overall_hits::cpu0.inst 25005 # number of overall hits +system.l2c.overall_hits::cpu0.data 89977 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11094 # number of overall hits +system.l2c.overall_hits::cpu1.data 14773 # number of overall hits +system.l2c.overall_hits::total 141053 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3255 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13225 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1885 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136548 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152370 # number of ReadExReq misses system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 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(read+write) accesses -system.l2c.demand_accesses::total 324902 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 82 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 70 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 41643 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 237651 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31854 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 324902 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951582 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980947 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958672 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920635 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994093 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964072 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907631 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.834889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899485 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028571 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402493 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128084 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176823 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087388 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.202323 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.402493 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.621491 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.176823 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.532523 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.565789 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.097561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.402493 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.621491 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.176823 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.532523 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.565789 # miss rate for overall accesses +system.l2c.ReadExReq_accesses::cpu0.data 150448 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18862 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169310 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 85 # number of ReadSharedReq accesses(hits+misses) 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+system.l2c.ReadExReq_miss_rate::cpu0.data 0.907609 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.838829 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899947 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.033333 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.401551 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128207 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176331 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087494 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.202302 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.033333 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.401551 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.621489 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.176331 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.534269 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.565856 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.033333 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.401551 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.621489 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.176331 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.534269 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.565856 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1386,51 +1386,51 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95877 # number of writebacks -system.l2c.writebacks::total 95877 # number of writebacks +system.l2c.writebacks::writebacks 96268 # number of writebacks +system.l2c.writebacks::total 96268 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 43996 # Transaction distribution -system.membus.trans_dist::ReadResp 75712 # Transaction distribution +system.membus.trans_dist::ReadResp 75724 # Transaction distribution system.membus.trans_dist::WriteReq 30846 # Transaction distribution system.membus.trans_dist::WriteResp 30846 # Transaction distribution -system.membus.trans_dist::WritebackDirty 132067 # Transaction distribution -system.membus.trans_dist::CleanEvict 8465 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60519 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15741 # Transaction distribution -system.membus.trans_dist::ReadExReq 196031 # Transaction distribution -system.membus.trans_dist::ReadExResp 151891 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution +system.membus.trans_dist::WritebackDirty 132458 # Transaction distribution +system.membus.trans_dist::CleanEvict 8718 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60357 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40887 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15566 # Transaction distribution +system.membus.trans_dist::ReadExReq 152312 # Transaction distribution +system.membus.trans_dist::ReadExResp 151914 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 31728 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 660645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782029 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109155 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 891184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 738406 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 847800 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17927560 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18117342 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17954824 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18144606 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20449630 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20476894 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 581009 # Request fanout histogram +system.membus.snoop_fanout::samples 537526 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581009 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 537526 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581009 # Request fanout histogram +system.membus.snoop_fanout::total 537526 # Request fanout histogram system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks @@ -1472,41 +1472,41 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 863003 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 444472 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 128485 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 9552 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 9071 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 481 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 862694 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 444199 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 128774 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 9376 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 486 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 301629 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 301670 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 225729 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 38612 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60623 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40978 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101601 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213528 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213528 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 257629 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1143706 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 415843 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1559549 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34428348 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10418866 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 44847214 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 180208 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1117804 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.282168 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.451010 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 225726 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 64248 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60580 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41006 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213448 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213448 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 257670 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1161849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423225 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1585074 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34444668 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10399858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44844526 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 180900 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1118187 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.282688 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.451270 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 802876 71.83% 71.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 314447 28.13% 99.96% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 481 0.04% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 802575 71.77% 71.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 315126 28.18% 99.96% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 486 0.04% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1117804 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1118187 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 4c4524faa..ef75cc834 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540254 # Simulator instruction rate (inst/s) -host_op_rate 657673 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10534181577 # Simulator tick rate (ticks/s) -host_mem_usage 560556 # Number of bytes of host memory used -host_seconds 264.27 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1173204 # Simulator instruction rate (inst/s) +host_op_rate 1428188 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 22875895912 # Simulator tick rate (ticks/s) +host_mem_usage 581200 # Number of bytes of host memory used +host_seconds 121.69 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory @@ -21,36 +21,36 @@ system.physmem.bytes_read::realview.ide 960 # Nu system.physmem.bytes_read::total 11533384 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840960 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858420 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858484 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161845 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189182 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138140 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142520 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142521 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 433574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3708811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3708827 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142955 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175798 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3182056 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3182093 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 433574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3715106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3715122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7325048 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -99,29 +99,29 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 10029 # Table walker walks requested -system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 10028 # Table walker walks requested +system.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526223 # DTB read hits -system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124452 # DTB write hits +system.cpu.dtb.read_hits 31525949 # DTB read hits +system.cpu.dtb.read_misses 8580 # DTB read misses +system.cpu.dtb.write_hits 23124104 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534804 # DTB read accesses -system.cpu.dtb.write_accesses 23125900 # DTB write accesses +system.cpu.dtb.read_accesses 31534529 # DTB read accesses +system.cpu.dtb.write_accesses 23125552 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650675 # DTB hits -system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660704 # DTB accesses +system.cpu.dtb.hits 54650053 # DTB hits +system.cpu.dtb.misses 10028 # DTB misses +system.cpu.dtb.accesses 54660081 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039346 # ITB inst hits +system.cpu.itb.inst_hits 147038166 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,40 +202,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044108 # ITB inst accesses -system.cpu.itb.hits 147039346 # DTB hits +system.cpu.itb.inst_accesses 147042928 # ITB inst accesses +system.cpu.itb.hits 147038166 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044108 # DTB accesses -system.cpu.numCycles 5567737188 # number of cpu cycles simulated +system.cpu.itb.accesses 147042928 # DTB accesses +system.cpu.numCycles 5567712151 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.committedInsts 142772879 # Number of instructions committed -system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses +system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu.committedInsts 142771651 # Number of instructions committed +system.cpu.committedOps 173801592 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153161279 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873899 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162683 # number of integer instructions +system.cpu.num_func_calls 16873962 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730275 # number of instructions that are conditional controls +system.cpu.num_int_insts 153161279 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written +system.cpu.num_int_register_reads 285057575 # number of times the integer registers were read +system.cpu.num_int_register_writes 107178464 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written -system.cpu.num_mem_refs 55939276 # number of memory refs -system.cpu.num_load_insts 31855884 # Number of load instructions -system.cpu.num_store_insts 24083392 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles -system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles +system.cpu.num_cc_register_reads 530849543 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62363904 # number of times the CC registers were written +system.cpu.num_mem_refs 55938616 # number of memory refs +system.cpu.num_load_insts 31855585 # Number of load instructions +system.cpu.num_store_insts 24083031 # Number of store instructions +system.cpu.num_idle_cycles 5389630193.939007 # Number of idle cycles +system.cpu.num_busy_cycles 178081957.060993 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36396981 # Number of branches fetched +system.cpu.Branches 36396978 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction -system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction +system.cpu.op_class::IntAlu 121152037 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction @@ -263,16 +263,16 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855585 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083031 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177219912 # Class of executed instruction -system.cpu.dcache.tags.replacements 819402 # number of replacements +system.cpu.op_class::total 177218432 # Class of executed instruction +system.cpu.dcache.tags.replacements 819392 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53783870 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597765 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,58 +282,58 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits -system.cpu.dcache.overall_hits::total 52864242 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 219235080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219235080 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30128800 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30128800 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22339791 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 52468591 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52468591 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52863656 # number of overall hits +system.cpu.dcache.overall_hits::total 52863656 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396281 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396281 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses -system.cpu.dcache.overall_misses::total 814074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses +system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses +system.cpu.dcache.overall_misses::total 814065 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 53166535 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53677721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53677721 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses @@ -348,16 +348,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682040 # number of writebacks -system.cpu.dcache.writebacks::total 682040 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682017 # number of writebacks +system.cpu.dcache.writebacks::total 682017 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699214 # number of replacements -system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1698998 # number of replacements +system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -366,32 +366,32 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits -system.cpu.icache.overall_hits::total 145342721 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses -system.cpu.icache.overall_misses::total 1699732 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145341757 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145341757 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145341757 # number of overall hits +system.cpu.icache.overall_hits::total 145341757 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699516 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699516 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699516 # number of overall misses +system.cpu.icache.overall_misses::total 1699516 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147041273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147041273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -400,20 +400,20 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu.icache.writebacks::total 1699214 # number of writebacks +system.cpu.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu.icache.writebacks::total 1698998 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109913 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4525282 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4524855 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 175194 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.830120 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.827682 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48764.035583 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.708883 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.628332 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48764.050695 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9168.704513 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7219.623437 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.744080 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -430,33 +430,33 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10699 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40582495 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40582495 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40578944 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40578944 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11222 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 682040 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1667206 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1667206 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11218 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 682017 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1666999 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 505445 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 505445 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681416 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656586 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349224 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1681201 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656576 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2348995 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681416 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656586 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349224 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681201 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656576 # number of overall hits +system.cpu.l2cache.overall_hits::total 2348995 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -480,56 +480,56 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 2 system.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163344 # number of overall misses system.cpu.l2cache.overall_misses::total 181651 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11231 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 682040 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1667206 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1667206 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 682017 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1666999 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1666999 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1699714 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1699499 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 521013 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699499 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530646 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699499 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530646 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000802 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029880 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010765 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.199217 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.071774 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.199219 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.071780 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010765 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.199217 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.071774 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.199219 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.071780 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,51 +538,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks -system.cpu.l2cache.writebacks::total 101949 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101950 # number of writebacks +system.cpu.l2cache.writebacks::total 101950 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5060356 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540713 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5059903 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2540486 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 67802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288329 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 682040 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 130096 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 682017 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 137375 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574734 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581970 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7714878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308833 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7753470 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96306721 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311939813 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182974 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5319191 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.018482 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.134685 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313958557 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 182975 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5318737 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.018478 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.134674 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5220884 98.15% 98.15% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 98307 1.85% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5220455 98.15% 98.15% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98282 1.85% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5319191 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5318737 # Request fanout histogram system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -634,14 +634,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -686,8 +686,8 @@ system.membus.trans_dist::ReadReq 40087 # Tr system.membus.trans_dist::ReadResp 74202 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138139 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138140 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -701,17 +701,17 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 506581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 613941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092412 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255385 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586905 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434821 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 35b76497a..13b640b18 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871850 # Number of seconds simulated -sim_ticks 2871850306000 # Number of ticks simulated -final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871782 # Number of seconds simulated +sim_ticks 2871782342000 # Number of ticks simulated +final_tick 2871782342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 312956 # Simulator instruction rate (inst/s) -host_op_rate 378531 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6832247646 # Simulator tick rate (ticks/s) -host_mem_usage 599868 # Number of bytes of host memory used -host_seconds 420.34 # Real time elapsed on the host -sim_insts 131546959 # Number of instructions simulated -sim_ops 159110973 # Number of ops (including micro ops) simulated +host_inst_rate 937604 # Simulator instruction rate (inst/s) +host_op_rate 1134083 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20478123685 # Simulator tick rate (ticks/s) +host_mem_usage 614632 # Number of bytes of host memory used +host_seconds 140.24 # Real time elapsed on the host +sim_insts 131486349 # Number of instructions simulated +sim_ops 159039994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1178404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1267556 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8608576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1156004 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1264932 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602496 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 129300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 549908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 341632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 151508 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 548500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 349120 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12076912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1178404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 129300 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1307704 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8530240 # Number of bytes written to this memory +system.physmem.bytes_read::total 12074032 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1156004 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 151508 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1307512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8524352 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8547804 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8541916 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26866 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20284 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134414 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2175 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2522 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8591 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5455 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197850 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133285 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133193 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 137676 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137584 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 111 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 410329 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 441373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2997571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 402539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 440469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2995525 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 191482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 118959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52757 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 190996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 121569 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4205272 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 410329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45023 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455352 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2970294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4204369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 402539 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52757 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2968314 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2976410 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2970294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2974430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2968314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 410329 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 447475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2997571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 402539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 446571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2995525 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 191496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 118959 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 191010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 121569 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7181682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197850 # Number of read requests accepted -system.physmem.writeReqs 137676 # Number of write requests accepted -system.physmem.readBursts 197850 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 137676 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12652352 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue -system.physmem.bytesWritten 8560960 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12076912 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8547804 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7178799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197805 # Number of read requests accepted +system.physmem.writeReqs 137584 # Number of write requests accepted +system.physmem.readBursts 197805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137584 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12650304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesWritten 8554240 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12074032 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8541916 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 64578 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11583 # Per bank write bursts -system.physmem.perBankRdBursts::1 11800 # Per bank write bursts -system.physmem.perBankRdBursts::2 11971 # Per bank write bursts -system.physmem.perBankRdBursts::3 11847 # Per bank write bursts -system.physmem.perBankRdBursts::4 20098 # Per bank write bursts -system.physmem.perBankRdBursts::5 11961 # Per bank write bursts -system.physmem.perBankRdBursts::6 12460 # Per bank write bursts -system.physmem.perBankRdBursts::7 12487 # Per bank write bursts -system.physmem.perBankRdBursts::8 11821 # Per bank write bursts -system.physmem.perBankRdBursts::9 12495 # Per bank write bursts -system.physmem.perBankRdBursts::10 11828 # Per bank write bursts -system.physmem.perBankRdBursts::11 11338 # Per bank write bursts -system.physmem.perBankRdBursts::12 11476 # Per bank write bursts -system.physmem.perBankRdBursts::13 11922 # Per bank write bursts -system.physmem.perBankRdBursts::14 11270 # Per bank write bursts -system.physmem.perBankRdBursts::15 11336 # Per bank write bursts -system.physmem.perBankWrBursts::0 8288 # Per bank write bursts -system.physmem.perBankWrBursts::1 8566 # Per bank write bursts -system.physmem.perBankWrBursts::2 8821 # Per bank write bursts -system.physmem.perBankWrBursts::3 8522 # Per bank write bursts -system.physmem.perBankWrBursts::4 7854 # Per bank write bursts -system.physmem.perBankWrBursts::5 8398 # Per bank write bursts -system.physmem.perBankWrBursts::6 8910 # Per bank write bursts -system.physmem.perBankWrBursts::7 8793 # Per bank write bursts -system.physmem.perBankWrBursts::8 8333 # Per bank write bursts -system.physmem.perBankWrBursts::9 8912 # Per bank write bursts -system.physmem.perBankWrBursts::10 8495 # Per bank write bursts -system.physmem.perBankWrBursts::11 8357 # Per bank write bursts -system.physmem.perBankWrBursts::12 8083 # Per bank write bursts -system.physmem.perBankWrBursts::13 7998 # Per bank write bursts -system.physmem.perBankWrBursts::14 7822 # Per bank write bursts -system.physmem.perBankWrBursts::15 7613 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11699 # Per bank write bursts +system.physmem.perBankRdBursts::1 11843 # Per bank write bursts +system.physmem.perBankRdBursts::2 11790 # Per bank write bursts +system.physmem.perBankRdBursts::3 11735 # Per bank write bursts +system.physmem.perBankRdBursts::4 20524 # Per bank write bursts +system.physmem.perBankRdBursts::5 11797 # Per bank write bursts +system.physmem.perBankRdBursts::6 12442 # Per bank write bursts +system.physmem.perBankRdBursts::7 12572 # Per bank write bursts +system.physmem.perBankRdBursts::8 12187 # Per bank write bursts +system.physmem.perBankRdBursts::9 12631 # Per bank write bursts +system.physmem.perBankRdBursts::10 11774 # Per bank write bursts +system.physmem.perBankRdBursts::11 11306 # Per bank write bursts +system.physmem.perBankRdBursts::12 11587 # Per bank write bursts +system.physmem.perBankRdBursts::13 11723 # Per bank write bursts +system.physmem.perBankRdBursts::14 11020 # Per bank write bursts +system.physmem.perBankRdBursts::15 11031 # Per bank write bursts +system.physmem.perBankWrBursts::0 8350 # Per bank write bursts +system.physmem.perBankWrBursts::1 8610 # Per bank write bursts +system.physmem.perBankWrBursts::2 8670 # Per bank write bursts +system.physmem.perBankWrBursts::3 8312 # Per bank write bursts +system.physmem.perBankWrBursts::4 8160 # Per bank write bursts +system.physmem.perBankWrBursts::5 8304 # Per bank write bursts +system.physmem.perBankWrBursts::6 8940 # Per bank write bursts +system.physmem.perBankWrBursts::7 8786 # Per bank write bursts +system.physmem.perBankWrBursts::8 8636 # Per bank write bursts +system.physmem.perBankWrBursts::9 9040 # Per bank write bursts +system.physmem.perBankWrBursts::10 8341 # Per bank write bursts +system.physmem.perBankWrBursts::11 8261 # Per bank write bursts +system.physmem.perBankWrBursts::12 8330 # Per bank write bursts +system.physmem.perBankWrBursts::13 7860 # Per bank write bursts +system.physmem.perBankWrBursts::14 7712 # Per bank write bursts +system.physmem.perBankWrBursts::15 7348 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 27 # Number of times write queue was full causing retry -system.physmem.totGap 2871849883000 # Total gap between requests +system.physmem.totGap 2871781902000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188090 # Read request sizes (log2) +system.physmem.readPktSize::6 188045 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133285 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138613 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10206 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 81 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133193 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6977 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,161 +184,163 @@ system.physmem.wrQLenPdf::11 1 # Wh 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-system.physmem.bytesPerActivate::256-383 5908 6.74% 79.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3515 4.01% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2504 2.86% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1565 1.78% 88.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 855 0.98% 89.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 945 1.08% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8347 9.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87676 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6535 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.251262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 585.438505 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6533 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7802 # What write queue length does an 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see 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incoming req see +system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 107 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87582 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.110023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.595388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 304.444001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46635 53.25% 53.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17297 19.75% 73.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6011 6.86% 79.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3421 3.91% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2493 2.85% 86.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1531 1.75% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 857 0.98% 89.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 971 1.11% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8366 9.55% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87582 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6415 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.812159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.882305 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6413 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6535 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.469013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.883832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.598321 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5330 81.56% 81.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 483 7.39% 88.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 73 1.12% 90.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 153 2.34% 92.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 0.50% 92.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 123 1.88% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.55% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.40% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.38% 96.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.23% 96.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 6 0.09% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.09% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 152 2.33% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.40% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.11% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6535 # Writes before turning the bus around for reads -system.physmem.totQLat 4503336233 # Total ticks spent queuing -system.physmem.totMemAccLat 8210079983 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 988465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22779.44 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6415 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6415 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.835542 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.951972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.109397 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5337 83.20% 83.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 463 7.22% 90.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 65 1.01% 91.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 41 0.64% 92.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 43 0.67% 92.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.23% 92.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 61 0.95% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.19% 94.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 120 1.87% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.19% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.19% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 75 1.17% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.14% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.39% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 75 1.17% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.05% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.17% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 5 0.08% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6415 # Writes before turning the bus around for reads +system.physmem.totQLat 4510532456 # Total ticks spent queuing +system.physmem.totMemAccLat 8216676206 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988305000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22819.54 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41529.44 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41569.54 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.35 # Average write queue length when enqueuing -system.physmem.readRowHits 165103 # Number of row buffer hits during reads -system.physmem.writeRowHits 78678 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.88 # Average write queue length when enqueuing +system.physmem.readRowHits 165067 # Number of row buffer hits during reads +system.physmem.writeRowHits 78671 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.81 # Row buffer hit rate for writes -system.physmem.avgGap 8559246.92 # Average gap between requests -system.physmem.pageHitRate 73.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341250840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186198375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 812814600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441624960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85820448015 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647828636000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1923006208950 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.605484 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2741162536487 # Time in different power states -system.physmem_0.memoryStateTime::REF 95897360000 # Time in different power states +system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes +system.physmem.avgGap 8562540.52 # Average gap between requests +system.physmem.pageHitRate 73.56 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341273520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186210750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 814335600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441495360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86023351485 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647608604750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1922985930585 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.614762 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2740794855198 # Time in different power states +system.physmem_0.memoryStateTime::REF 95895020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34789668513 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35089613552 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 321579720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175465125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 729183000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 425172240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84866434740 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648665489750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922758560735 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.519251 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742561244982 # Time in different power states -system.physmem_1.memoryStateTime::REF 95897360000 # Time in different power states +system.physmem_1.actEnergy 320846400 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 175065000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 727412400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 424621440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187570659120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84787415640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648692759000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922698779000 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.514771 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742610583350 # Time in different power states +system.physmem_1.memoryStateTime::REF 95895020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33391555518 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33276576650 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -394,56 +396,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 8830 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 8830 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1617 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7213 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 8830 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 8830 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 8830 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7312 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6252.045789 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7284 99.62% 99.62% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 24 0.33% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7312 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8793 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8793 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1631 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7162 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8793 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8793 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7275 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12044.604811 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11100.960867 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5725.376750 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6764 92.98% 92.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 475 6.53% 99.51% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 28 0.38% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 4 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7275 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5742 78.53% 78.53% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1570 21.47% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7312 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8830 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5691 78.23% 78.23% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1584 21.77% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7275 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8793 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8830 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7312 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8793 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7275 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7312 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 16142 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7275 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 16068 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25809403 # DTB read hits -system.cpu0.dtb.read_misses 7606 # DTB read misses -system.cpu0.dtb.write_hits 19327142 # DTB write hits -system.cpu0.dtb.write_misses 1224 # DTB write misses +system.cpu0.dtb.read_hits 25747110 # DTB read hits +system.cpu0.dtb.read_misses 7587 # DTB read misses +system.cpu0.dtb.write_hits 19248161 # DTB write hits +system.cpu0.dtb.write_misses 1206 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3761 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3752 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1861 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1822 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25817009 # DTB read accesses -system.cpu0.dtb.write_accesses 19328366 # DTB write accesses +system.cpu0.dtb.read_accesses 25754697 # DTB read accesses +system.cpu0.dtb.write_accesses 19249367 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 45136545 # DTB hits -system.cpu0.dtb.misses 8830 # DTB misses -system.cpu0.dtb.accesses 45145375 # DTB accesses +system.cpu0.dtb.hits 44995271 # DTB hits +system.cpu0.dtb.misses 8793 # DTB misses +system.cpu0.dtb.accesses 45004064 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,15 +486,13 @@ system.cpu0.itb.walker.walkWaitTime::samples 3674 system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6240.244766 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2261 87.77% 87.77% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 282 10.95% 98.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 30 1.16% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12540.566770 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11604.890292 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7309.377161 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 2541 98.64% 98.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 33 1.28% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution @@ -504,7 +507,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 121850168 # ITB inst hits +system.cpu0.itb.inst_hits 121581439 # ITB inst hits system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -521,172 +524,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 121853842 # ITB inst accesses -system.cpu0.itb.hits 121850168 # DTB hits +system.cpu0.itb.inst_accesses 121585113 # ITB inst accesses +system.cpu0.itb.hits 121581439 # DTB hits system.cpu0.itb.misses 3674 # DTB misses -system.cpu0.itb.accesses 121853842 # DTB accesses -system.cpu0.numCycles 5743700612 # number of cpu cycles simulated +system.cpu0.itb.accesses 121585113 # DTB accesses +system.cpu0.numCycles 5743564684 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed -system.cpu0.committedInsts 118029542 # Number of instructions committed -system.cpu0.committedOps 142673635 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 126253590 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1899 # number of quiesce instructions executed +system.cpu0.committedInsts 117764996 # Number of instructions committed +system.cpu0.committedOps 142323546 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 125936873 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses -system.cpu0.num_func_calls 12792333 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16043976 # number of instructions that are conditional controls -system.cpu0.num_int_insts 126253590 # number of integer instructions +system.cpu0.num_func_calls 12772448 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16008688 # number of instructions that are conditional controls +system.cpu0.num_int_insts 125936873 # number of integer instructions system.cpu0.num_fp_insts 11483 # number of float instructions -system.cpu0.num_int_register_reads 232324144 # number of times the integer registers were read -system.cpu0.num_int_register_writes 87654298 # number of times the integer registers were written +system.cpu0.num_int_register_reads 231719006 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87450436 # number of times the integer registers were written system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 516734560 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 53610723 # number of times the CC registers were written -system.cpu0.num_mem_refs 46299073 # number of memory refs -system.cpu0.num_load_insts 26069844 # Number of load instructions -system.cpu0.num_store_insts 20229229 # Number of store instructions -system.cpu0.num_idle_cycles 5455076908.366100 # Number of idle cycles -system.cpu0.num_busy_cycles 288623703.633900 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050250 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949750 # Percentage of idle cycles -system.cpu0.Branches 29603215 # Number of branches fetched +system.cpu0.num_cc_register_reads 515468589 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53496392 # number of times the CC registers were written +system.cpu0.num_mem_refs 46152180 # number of memory refs +system.cpu0.num_load_insts 26006060 # Number of load instructions +system.cpu0.num_store_insts 20146120 # Number of store instructions +system.cpu0.num_idle_cycles 5455990176.452100 # Number of idle cycles +system.cpu0.num_busy_cycles 287574507.547900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050069 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949931 # Percentage of idle cycles +system.cpu0.Branches 29546529 # Number of branches fetched system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 100054313 68.31% 68.31% # Class of executed instruction -system.cpu0.op_class::IntMult 112340 0.08% 68.39% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8369 0.01% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.39% # Class of executed instruction -system.cpu0.op_class::MemRead 26069844 17.80% 86.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 20229229 13.81% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 99842345 68.33% 68.33% # Class of executed instruction +system.cpu0.op_class::IntMult 112141 0.08% 68.41% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8311 0.01% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 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Class of executed instruction +system.cpu0.dcache.tags.replacements 732778 # number of replacements +system.cpu0.dcache.tags.tagsinuse 487.345221 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44083181 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 733290 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 60.116981 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.760528 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954610 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.954610 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.345221 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951846 # Average 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# number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 44290989 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016995 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016995 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017993 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017993 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290058 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290058 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056709 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056709 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050589 # miss rate for StoreCondReq accesses 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13552.537840 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13552.537840 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20512.937302 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20512.937302 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15377.333572 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15377.333572 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25380.199919 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25380.199919 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 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demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25304 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25304 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 398198 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 398198 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 340254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 340254 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106613 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106613 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6683 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6683 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19849 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19849 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 738452 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 738452 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 845065 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 845065 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31860 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60413 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4887280000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4887280000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6648929500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6648929500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1745313500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1745313500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102495000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102495000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 491343000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 491343000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1414500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1414500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11536209500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11536209500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13281523000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13281523000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6641550500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6641550500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5414724500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5414724500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12056275000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12056275000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015979 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015979 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017993 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017993 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231273 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231273 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016818 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016818 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050589 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050589 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016848 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016848 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019080 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019080 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 732778 # number of writebacks +system.cpu0.dcache.writebacks::total 732778 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25286 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25286 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15664 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15664 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25288 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25288 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25288 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25288 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392727 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 392727 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337665 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 337665 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106338 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 106338 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6673 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6673 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19808 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19808 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 730392 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 730392 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 836730 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 836730 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31820 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31820 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60319 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60319 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4843447000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4843447000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6588824500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6588824500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1737105000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1737105000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102846500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102846500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 482970000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 482970000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1793500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1793500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11432271500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11432271500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13169376500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13169376500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629050000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629050000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400878000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400878000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12029928000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12029928000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015798 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015798 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017930 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017930 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231335 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231335 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016833 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016833 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050600 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050600 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016717 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018951 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018951 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12332.859722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12332.859722 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19512.903321 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19512.903321 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16335.693731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16335.693731 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15412.333283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15412.333283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24382.572698 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24382.572698 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15652.240851 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15652.240851 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15739.099232 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15739.099232 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208329.666876 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208329.666876 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189511.140742 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189511.140742 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199438.452229 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199438.452229 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1154605 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.321447 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 120695042 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1155117 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 104.487287 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1147265 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.321425 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 120433653 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1147777 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 104.927746 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321447 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321425 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 244855462 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 244855462 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 120695042 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 120695042 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 120695042 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 120695042 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 120695042 # number of overall hits -system.cpu0.icache.overall_hits::total 120695042 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1155126 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1155126 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1155126 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1155126 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1155126 # number of overall misses -system.cpu0.icache.overall_misses::total 1155126 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12352499000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12352499000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12352499000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12352499000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12352499000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12352499000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 121850168 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 121850168 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 121850168 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 121850168 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 121850168 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 121850168 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009480 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009480 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009480 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10693.637750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10693.637750 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244310664 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244310664 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120433653 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120433653 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 120433653 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 120433653 # number of demand (read+write) hits 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12247651500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12247651500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12247651500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 121581439 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 121581439 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 121581439 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 121581439 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 121581439 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 121581439 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009440 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009440 # miss rate for ReadReq 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uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1946486 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1946511 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935691 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1935756 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 57 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 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+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561091000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12747302500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015749 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1176,117 +1182,117 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147232 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147232 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040254 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184753 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184753 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093075 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148467 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148467 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040262 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186102 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186102 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093508 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.015671 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015925 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040262 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172612 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227483 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229255 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20744.047619 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76983.742104 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25547.990342 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25547.990342 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16904.969948 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16904.969948 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 159944.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 159944.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56121.645135 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56121.645135 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65202.631351 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28331.038366 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28331.038366 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44042.511929 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20232.758621 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 21884.615385 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65202.631351 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36899.432657 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76983.742104 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63547.816252 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200316.687618 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185110.633661 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.877434 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.877434 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191665.826688 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183834.996611 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3935499 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1983981 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 29039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 320941 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317478 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 63971 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1779248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28553 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 740475 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1358751 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 190136 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 311790 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85728 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41989 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112642 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 304006 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 300714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1155126 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 580591 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3461069 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2699694 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12104 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27735 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6200602 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146461624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 102248167 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20304 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 248776863 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 987005 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2997932 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.122336 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.331180 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3905249 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1969182 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28911 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 320342 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 316677 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3665 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63843 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1765873 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 732965 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1379104 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 189043 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 312150 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41941 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112560 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 301555 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 298207 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147786 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 575214 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3299 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3460881 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2681738 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11926 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27058 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6181603 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146919352 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101652834 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44412 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 248636190 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 986669 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2981108 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.123159 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.332339 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2634639 87.88% 87.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 359830 12.00% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 3463 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2617624 87.81% 87.81% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 359819 12.07% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3665 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2997932 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3917122496 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2981108 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3885976496 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115533329 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115188451 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1741711000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1730701000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1278424980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1266054481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 16050485 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 15961487 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1317,57 +1323,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 2352 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2352 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 487 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1865 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2352 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2352 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2352 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1706 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5645.878722 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1558 91.32% 91.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 139 8.15% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 2346 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2346 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 473 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1873 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2346 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2346 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2346 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11761.764706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11073.675458 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5957.546231 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1554 91.41% 91.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.94% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.65% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.29% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1700 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1219 71.45% 71.45% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 487 28.55% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1706 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1227 72.18% 72.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 473 27.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1700 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2346 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2352 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2346 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1700 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1706 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 4058 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1700 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4046 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3283088 # DTB read hits -system.cpu1.dtb.read_misses 1969 # DTB read misses -system.cpu1.dtb.write_hits 2849660 # DTB write hits -system.cpu1.dtb.write_misses 383 # DTB write misses +system.cpu1.dtb.read_hits 3334779 # DTB read hits +system.cpu1.dtb.read_misses 1954 # DTB read misses +system.cpu1.dtb.write_hits 2915242 # DTB write hits +system.cpu1.dtb.write_misses 392 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1653 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 218 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3285057 # DTB read accesses -system.cpu1.dtb.write_accesses 2850043 # DTB write accesses +system.cpu1.dtb.read_accesses 3336733 # DTB read accesses +system.cpu1.dtb.write_accesses 2915634 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6132748 # DTB hits -system.cpu1.dtb.misses 2352 # DTB misses -system.cpu1.dtb.accesses 6135100 # DTB accesses +system.cpu1.dtb.hits 6250021 # DTB hits +system.cpu1.dtb.misses 2346 # DTB misses +system.cpu1.dtb.accesses 6252367 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1405,21 +1411,20 @@ system.cpu1.itb.walker.walkWaitTime::samples 1376 system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5216.232861 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 112 13.68% 13.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 592 72.28% 85.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 66 8.06% 94.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 94.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11933.455433 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11288.127256 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5150.797327 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 577 70.45% 84.62% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 76 9.28% 93.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 94.87% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 24 2.93% 98.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 5 0.61% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.73% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 8 0.98% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 2 0.24% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution @@ -1434,7 +1439,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 13713445 # ITB inst hits +system.cpu1.itb.inst_hits 13920333 # ITB inst hits system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1451,171 +1456,171 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 13714821 # ITB inst accesses -system.cpu1.itb.hits 13713445 # DTB hits +system.cpu1.itb.inst_accesses 13921709 # ITB inst accesses +system.cpu1.itb.hits 13920333 # DTB hits system.cpu1.itb.misses 1376 # DTB misses -system.cpu1.itb.accesses 13714821 # DTB accesses -system.cpu1.numCycles 5742759797 # number of cpu cycles simulated +system.cpu1.itb.accesses 13921709 # DTB accesses +system.cpu1.numCycles 5742623362 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2753 # number of quiesce instructions executed -system.cpu1.committedInsts 13517417 # Number of instructions committed -system.cpu1.committedOps 16437338 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14911378 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2722 # number of quiesce instructions executed +system.cpu1.committedInsts 13721353 # Number of instructions committed +system.cpu1.committedOps 16716448 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 15155011 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 901174 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1468136 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14911378 # number of integer instructions +system.cpu1.num_func_calls 915079 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1497955 # number of instructions that are conditional controls +system.cpu1.num_int_insts 15155011 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 27063131 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10536793 # number of times the integer registers were written +system.cpu1.num_int_register_reads 27537464 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10698089 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 60344215 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 5099594 # number of times the CC registers were written -system.cpu1.num_mem_refs 6349896 # number of memory refs -system.cpu1.num_load_insts 3389045 # Number of load instructions -system.cpu1.num_store_insts 2960851 # Number of store instructions -system.cpu1.num_idle_cycles 5696813538.222876 # Number of idle cycles -system.cpu1.num_busy_cycles 45946258.777124 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008001 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991999 # Percentage of idle cycles -system.cpu1.Branches 2418797 # Number of branches fetched +system.cpu1.num_cc_register_reads 61338598 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5194112 # number of times the CC registers were written +system.cpu1.num_mem_refs 6464162 # number of memory refs +system.cpu1.num_load_insts 3439477 # Number of load instructions +system.cpu1.num_store_insts 3024685 # Number of store instructions +system.cpu1.num_idle_cycles 5696031009.438875 # Number of idle cycles +system.cpu1.num_busy_cycles 46592352.561125 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008113 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991887 # Percentage of idle cycles +system.cpu1.Branches 2464329 # Number of branches fetched system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 10377527 61.94% 61.94% # Class of executed instruction -system.cpu1.op_class::IntMult 24492 0.15% 62.08% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3134 0.02% 62.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.10% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.10% # Class of executed instruction -system.cpu1.op_class::MemRead 3389045 20.23% 82.33% # Class of executed instruction -system.cpu1.op_class::MemWrite 2960851 17.67% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 10543721 61.89% 61.89% # Class of executed instruction +system.cpu1.op_class::IntMult 24250 0.14% 62.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.05% # Class of executed instruction +system.cpu1.op_class::MemRead 3439477 20.19% 82.24% # Class of executed instruction +system.cpu1.op_class::MemWrite 3024685 17.76% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 16755073 # Class of executed instruction -system.cpu1.dcache.tags.replacements 144073 # number of replacements -system.cpu1.dcache.tags.tagsinuse 473.219627 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5912733 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 144418 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.941801 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106295131000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.219627 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924257 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.924257 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id +system.cpu1.op_class::total 17035345 # Class of executed instruction +system.cpu1.dcache.tags.replacements 148314 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.091453 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6019898 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 148666 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.492769 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106291978000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.091453 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916194 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.916194 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 352 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 26 # Occupied blocks per task id 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-system.cpu1.dcache.StoreCondReq_hits::total 61182 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5703361 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5703361 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5744606 # number of overall hits -system.cpu1.dcache.overall_hits::total 5744606 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 110713 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 110713 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 77621 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 77621 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23905 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 23905 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16417 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16417 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23076 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23076 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 188334 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 188334 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 212239 # number of overall misses -system.cpu1.dcache.overall_misses::total 212239 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1730591500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1730591500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2713528000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2713528000 # number of WriteReq miss cycles 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of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3128878 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3128878 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2762817 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2762817 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65150 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 65150 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85980 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 85980 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84258 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84258 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5891695 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5891695 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5956845 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5956845 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035384 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035384 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028095 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028095 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366922 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366922 # miss rate for SoftPFReq accesses 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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19253.065641 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27207.358801 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27207.358801 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23251.377636 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23251.377636 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20626.021289 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20626.021289 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1624,147 +1629,147 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 144073 # number of writebacks -system.cpu1.dcache.writebacks::total 144073 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11530 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11530 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 168 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 168 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 168 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110545 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 110545 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77621 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 77621 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23508 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23508 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4887 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4887 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23076 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23076 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 188166 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 188166 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 211674 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 211674 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3107 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5537 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1611627000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1611627000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2635907000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2635907000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 421753500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 421753500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88480500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88480500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 609718000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 609718000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3277000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3277000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4247534000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4247534000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4669287500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4669287500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 430617000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 430617000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 292641500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 292641500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 723258500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 723258500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035331 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035331 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028095 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028095 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360829 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360829 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056839 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273873 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273873 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031937 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031937 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035535 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035535 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 148314 # number of writebacks +system.cpu1.dcache.writebacks::total 148314 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 199 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11732 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11732 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 199 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 199 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 199 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 199 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112601 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 112601 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79377 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79377 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24003 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 24003 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4904 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4904 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23088 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 191978 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 191978 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 215981 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 215981 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3083 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2425 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2425 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5508 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5508 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1635811500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1635811500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2630907000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2630907000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 431572500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 431572500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89921000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89921000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 605110500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 605110500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3813000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3813000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4266718500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4266718500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4698291000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4698291000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439541500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439541500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303268000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303268000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742809500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742809500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035421 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035421 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028069 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028069 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.362020 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.362020 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056702 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056702 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272592 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272592 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031960 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031960 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035563 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035563 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14527.504196 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14527.504196 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33144.449904 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33144.449904 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17979.940007 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17979.940007 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18336.256117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18336.256117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26208.874740 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26208.874740 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22225.038807 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22225.038807 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21753.260703 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21753.260703 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142569.412910 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142569.412910 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125058.969072 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125058.969072 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134860.112564 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134860.112564 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 461792 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.311266 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13251136 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 462304 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 28.663252 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 106195905000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311266 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 463432 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.310833 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13456384 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463944 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.004328 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 106360036500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.310833 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973263 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973263 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 27889184 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 27889184 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13251136 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13251136 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13251136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13251136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13251136 # number of overall hits -system.cpu1.icache.overall_hits::total 13251136 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 462304 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 462304 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 462304 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 462304 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 462304 # number of overall misses -system.cpu1.icache.overall_misses::total 462304 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4149723500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4149723500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4149723500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4149723500 # number of demand (read+write) miss cycles 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overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9083.580130 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9083.580130 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9083.580130 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1773,437 +1778,448 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 461792 # number of writebacks -system.cpu1.icache.writebacks::total 461792 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 462304 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 462304 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 462304 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 462304 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 462304 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 462304 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 463432 # number of writebacks +system.cpu1.icache.writebacks::total 463432 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463944 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463944 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463944 # number of demand (read+write) MSHR misses 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-system.cpu1.icache.demand_mshr_miss_latency::total 3918571500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3918571500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3918571500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3982300500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3982300500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3982300500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3982300500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3982300500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3982300500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033712 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.033712 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.033712 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8476.179094 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033329 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033329 # mshr miss rate for demand accesses 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133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 106104 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 106112 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118303 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118321 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 16 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 50448 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 30131 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14949.290291 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1034569 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 45193 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 22.892240 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 50079 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 31154 # number of replacements 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-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000141 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026273 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.912432 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 971 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14059 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 54 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 913 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14446.292104 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.202140 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.081939 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 484.280848 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.881732 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.029558 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.911612 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 981 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14113 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 47 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 926 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1365 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12304 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059265 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858093 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 20957142 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 20957142 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2443 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1453 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 3896 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 89055 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 89055 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 506752 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 506752 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16650 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 16650 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 453968 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 453968 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 75407 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 75407 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2443 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1453 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 453968 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 92057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 549921 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2443 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1453 # number of overall hits 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ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699601000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721820000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.141577 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.656419 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.656419 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018031 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457269 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457269 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159641 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637826 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637826 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.019198 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.451423 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.451423 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159871 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.124153 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.169109 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.019198 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.500380 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.188321 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191827 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14162.808642 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44272.218526 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19901.166603 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19901.166603 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18706.436523 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18706.436523 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3550000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3550000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44810.382905 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44810.382905 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53553.834063 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16480.612085 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16480.612085 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28219.919685 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14395.114943 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13893.333333 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53553.834063 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25964.974122 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44272.218526 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30894.056879 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134456.373662 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133971.779141 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117555.463918 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117555.463918 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127015.432099 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126969.217238 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1312846 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 662941 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 166384 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164278 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 10119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 648543 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2430 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2430 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 115438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 506752 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 85166 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 22864 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70245 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84598 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 55915 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 53326 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 462304 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 211564 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 31 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1378500 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707096 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4372 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7009 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2096977 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58614596 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 23813135 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82445915 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 350196 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 987919 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.185835 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.394416 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1324645 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668824 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10099 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 169409 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166956 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2453 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10097 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 652790 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2425 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2425 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 119017 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 519745 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 86537 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 25449 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70337 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40896 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57665 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55147 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 463944 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215084 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1391674 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 722021 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4392 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7022 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2125109 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59352772 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24485096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7096 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11212 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 83856176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 356096 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 999531 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.187033 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.396182 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 806435 81.63% 81.63% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 179378 18.16% 99.79% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2106 0.21% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 815039 81.54% 81.54% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 182039 18.21% 99.75% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2453 0.25% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 987919 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1267256999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 999531 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1279051999 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79126203 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79434008 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 693633000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 696093000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 311803500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 318231000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 4217000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 4219000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31009 # Transaction distribution -system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::ReadReq 31021 # Transaction distribution +system.iobus.trans_dist::ReadResp 31021 # Transaction distribution system.iobus.trans_dist::WriteReq 59425 # Transaction distribution system.iobus.trans_dist::WriteResp 59425 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) @@ -2226,9 +2242,9 @@ system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) @@ -2249,14 +2265,14 @@ system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48738000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48746500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -2264,7 +2280,7 @@ system.iobus.reqLayer4.occupancy 16000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 609000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2274,7 +2290,7 @@ system.iobus.reqLayer14.occupancy 11500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) @@ -2286,54 +2302,54 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6150500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6162500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186301036 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187117449 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36433 # number of replacements -system.iocache.tags.tagsinuse 1.018273 # Cycle average of tags in use +system.iocache.tags.replacements 36461 # number of replacements +system.iocache.tags.tagsinuse 14.380044 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290654223000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.018273 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.063642 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.063642 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290746348000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.380044 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.898753 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.898753 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31405376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31405376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4738596660 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4738596660 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31405376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31405376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31405376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31405376 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32874877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32874877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4582462572 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4582462572 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32874877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32874877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32874877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32874877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2342,40 +2358,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129240.230453 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129240.230453 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129240.230453 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 816 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128921.086275 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128921.086275 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126503.494148 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126503.494148 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128921.086275 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128921.086275 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128921.086275 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 19 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.329114 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36190 # number of writebacks -system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36206 # number of writebacks +system.iocache.writebacks::total 36206 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19255376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19255376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927396660 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2927396660 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19255376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19255376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19255376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19255376 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20124877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20124877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2769551646 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2769551646 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20124877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20124877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20124877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20124877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2384,304 +2400,303 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78921.086275 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78921.086275 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76456.262312 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76456.262312 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78921.086275 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78921.086275 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 123618 # number of replacements -system.l2c.tags.tagsinuse 63093.840837 # Cycle average of tags in use -system.l2c.tags.total_refs 421259 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 187589 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.245649 # Average number of references to valid blocks. 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occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954483 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1120.568935 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 367.321258 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1502.766604 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.202089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.117970 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.553468 # Average percentage of cache occupancy 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Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.112320 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545176 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017099 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.005605 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022930 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.962736 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32107 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31859 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4716 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 27259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2381 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29068 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.489914 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.486130 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5836461 # Number of tag accesses -system.l2c.tags.data_accesses 5836461 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 257531 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 257531 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32441 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1723 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34164 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2115 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.022026 # Average percentage of cache occupancy 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# number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2044 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4177 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5519 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 92 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 28642 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 47295 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47544 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 6315 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 4707 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3005 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 137714 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 92 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28642 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47544 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 15 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6315 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6049 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3005 # number of demand (read+write) hits -system.l2c.demand_hits::total 143233 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 92 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28642 # number of overall hits -system.l2c.overall_hits::cpu0.data 51472 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47544 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 15 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6315 # number of overall hits -system.l2c.overall_hits::cpu1.data 6049 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3005 # number of overall hits -system.l2c.overall_hits::total 143233 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11910 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1322 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1977 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11124 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7851 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18975 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses +system.l2c.SCUpgradeReq_hits::total 2943 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4115 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1385 # number of 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123026.368159 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225360 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.538941 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.253917 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.223109 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592660 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.391691 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.729792 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.848832 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774507 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.159471 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136991 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.550811 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.567233 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.050000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027027 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.378711 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281994 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738873 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.047619 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.264623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.570887 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614717 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.567233 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72729.970168 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72293.908404 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72645.681135 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74539.182283 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73949.923547 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74132.453826 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135769.705956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120850.135785 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129627.654333 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126244.086300 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130687.195274 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133669.083481 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121526.656134 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131540.121161 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135401.073738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122783.415359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121771.822748 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 147115.837947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133263.982012 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182316.341923 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116572.727273 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163341.515681 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.368645 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100538.350928 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159950.911945 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174137.875296 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109509.446140 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161943.930541 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44163 # Transaction distribution -system.membus.trans_dist::ReadResp 213934 # Transaction distribution -system.membus.trans_dist::WriteReq 30983 # Transaction distribution -system.membus.trans_dist::WriteResp 30983 # Transaction distribution -system.membus.trans_dist::WritebackDirty 133285 # Transaction distribution -system.membus.trans_dist::CleanEvict 14406 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73490 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39839 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13966 # Transaction distribution +system.membus.trans_dist::ReadReq 44099 # Transaction distribution +system.membus.trans_dist::ReadResp 213926 # Transaction distribution +system.membus.trans_dist::WriteReq 30924 # Transaction distribution +system.membus.trans_dist::WriteResp 30924 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133193 # Transaction distribution +system.membus.trans_dist::CleanEvict 14771 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73670 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39871 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 39499 # Transaction distribution -system.membus.trans_dist::ReadExResp 18896 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169771 # Transaction distribution +system.membus.trans_dist::ReadExReq 39385 # Transaction distribution +system.membus.trans_dist::ReadExResp 18791 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169827 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14022 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 786162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 895071 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 650336 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 772080 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 845035 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18307596 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18498522 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20815642 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120564 # Total snoops (count) -system.membus.snoop_fanout::samples 581920 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18297804 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18488238 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20806382 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 121083 # Total snoops (count) +system.membus.snoop_fanout::samples 581994 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 581920 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581994 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 581920 # Request fanout histogram -system.membus.reqLayer0.occupancy 88268000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 581994 # Request fanout histogram +system.membus.reqLayer0.occupancy 88286500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11611500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11391000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 967762037 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 968108262 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1134685490 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1106274782 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64105002 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1388877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3000,52 +3011,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 959770 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 518663 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 138023 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20272 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44166 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 467162 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30983 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30983 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 390842 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 84262 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107575 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 150428 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50605 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50605 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 423011 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 960339 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 518534 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 139328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20435 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19626 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 809 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44102 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 468032 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30924 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30924 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 390589 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105128 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107757 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42814 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150571 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50426 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 423945 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1226424 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 245800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1472224 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34332563 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3643847 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37976410 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 437847 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 895583 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.335708 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474219 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240075 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 253445 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1493520 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34222158 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3776032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37998190 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 438746 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 896439 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.337268 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474682 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 595769 66.52% 66.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 298974 33.38% 99.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 840 0.09% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 594908 66.36% 66.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 300722 33.55% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 809 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 895583 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 863469481 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 896439 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 863728414 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 647119226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 645946273 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 200312901 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 202615858 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b6b1f5126..913ae877a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,83 +1,83 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909596 # Number of seconds simulated -sim_ticks 2909596171500 # Number of ticks simulated -final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909587 # Number of seconds simulated +sim_ticks 2909586837500 # Number of ticks simulated +final_tick 2909586837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 322522 # Simulator instruction rate (inst/s) -host_op_rate 388861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8344730622 # Simulator tick rate (ticks/s) -host_mem_usage 560756 # Number of bytes of host memory used -host_seconds 348.67 # Real time elapsed on the host -sim_insts 112455206 # Number of instructions simulated -sim_ops 135585876 # Number of ops (including micro ops) simulated +host_inst_rate 929184 # Simulator instruction rate (inst/s) +host_op_rate 1120306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24040663881 # Simulator tick rate (ticks/s) +host_mem_usage 581600 # Number of bytes of host memory used +host_seconds 121.03 # Real time elapsed on the host +sim_insts 112457033 # Number of instructions simulated +sim_ops 135588117 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901796 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901860 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186532 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186532 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139611 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166628 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059493 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581810 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587833 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581810 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166625 # Number of read requests accepted -system.physmem.writeReqs 121754 # Number of write requests accepted -system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 7541952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166628 # Number of read requests accepted +system.physmem.writeReqs 121756 # Number of write requests accepted +system.physmem.readBursts 166628 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10657408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 7542016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10077 # Per bank write bursts system.physmem.perBankRdBursts::1 9979 # Per bank write bursts system.physmem.perBankRdBursts::2 10695 # Per bank write bursts -system.physmem.perBankRdBursts::3 10661 # Per bank write bursts +system.physmem.perBankRdBursts::3 10660 # Per bank write bursts system.physmem.perBankRdBursts::4 18797 # Per bank write bursts -system.physmem.perBankRdBursts::5 9659 # Per bank write bursts -system.physmem.perBankRdBursts::6 9663 # Per bank write bursts -system.physmem.perBankRdBursts::7 10485 # Per bank write bursts +system.physmem.perBankRdBursts::5 9664 # Per bank write bursts +system.physmem.perBankRdBursts::6 9666 # Per bank write bursts +system.physmem.perBankRdBursts::7 10487 # Per bank write bursts system.physmem.perBankRdBursts::8 9276 # Per bank write bursts system.physmem.perBankRdBursts::9 9973 # Per bank write bursts system.physmem.perBankRdBursts::10 9232 # Per bank write bursts system.physmem.perBankRdBursts::11 8679 # Per bank write bursts -system.physmem.perBankRdBursts::12 9817 # Per bank write bursts +system.physmem.perBankRdBursts::12 9822 # Per bank write bursts system.physmem.perBankRdBursts::13 10379 # Per bank write bursts -system.physmem.perBankRdBursts::14 9722 # Per bank write bursts +system.physmem.perBankRdBursts::14 9723 # Per bank write bursts system.physmem.perBankRdBursts::15 9413 # Per bank write bursts system.physmem.perBankWrBursts::0 7393 # Per bank write bursts system.physmem.perBankWrBursts::1 7263 # Per bank write bursts @@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::3 8171 # Pe system.physmem.perBankWrBursts::4 7489 # Per bank write bursts system.physmem.perBankWrBursts::5 7265 # Per bank write bursts system.physmem.perBankWrBursts::6 7108 # Per bank write bursts -system.physmem.perBankWrBursts::7 7659 # Per bank write bursts +system.physmem.perBankWrBursts::7 7661 # Per bank write bursts system.physmem.perBankWrBursts::8 7080 # Per bank write bursts system.physmem.perBankWrBursts::9 7523 # Per bank write bursts system.physmem.perBankWrBursts::10 6695 # Per bank write bursts system.physmem.perBankWrBursts::11 6470 # Per bank write bursts -system.physmem.perBankWrBursts::12 7534 # Per bank write bursts +system.physmem.perBankWrBursts::12 7533 # Per bank write bursts system.physmem.perBankWrBursts::13 7859 # Per bank write bursts system.physmem.perBankWrBursts::14 7264 # Per bank write bursts system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2909595814500 # Total gap between requests +system.physmem.numWrRetry 10 # Number of times write queue was full causing retry +system.physmem.totGap 2909586480500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157053 # Read request sizes (log2) +system.physmem.readPktSize::6 157056 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117373 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117375 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,117 +159,114 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5950 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.611351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.749688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.493771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21450 36.49% 36.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14701 25.01% 61.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6086 10.35% 71.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 5.47% 77.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2550 4.34% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1476 2.51% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1054 1.79% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1089 1.85% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7158 12.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58778 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5758 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.915596 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.311059 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5757 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 36 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58742 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.818528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.858167 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.750191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21399 36.43% 36.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14737 25.09% 61.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6061 10.32% 71.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3228 5.50% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2535 4.32% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1458 2.48% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1057 1.80% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1079 1.84% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7188 12.24% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58742 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5615 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.654497 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 597.763680 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5614 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5758 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.465960 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.711564 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.116644 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4961 86.16% 86.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 87 1.51% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.57% 88.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 172 2.99% 91.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 23 0.40% 91.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 160 2.78% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 50 0.87% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.10% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 7 0.12% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 22 0.38% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.03% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 2.83% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.05% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.17% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.35% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 16 0.28% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5758 # Writes before turning the bus around for reads -system.physmem.totQLat 1616458000 # Total ticks spent queuing -system.physmem.totMemAccLat 4738464250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9708.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5615 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5615 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.987355 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.791633 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.100649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4949 88.14% 88.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 78 1.39% 89.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.57% 90.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 46 0.82% 90.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 24 0.43% 91.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.36% 91.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 46 0.82% 92.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 92.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 153 2.72% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.20% 95.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.12% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.23% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 63 1.12% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.46% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 103 1.83% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.14% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5615 # Writes before turning the bus around for reads +system.physmem.totQLat 1624802000 # Total ticks spent queuing +system.physmem.totMemAccLat 4747089500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9757.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28458.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28507.28 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -280,39 +277,39 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing -system.physmem.readRowHits 136072 # Number of row buffer hits during reads -system.physmem.writeRowHits 89499 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes -system.physmem.avgGap 10089485.76 # Average gap between requests -system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230958000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126018750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702124800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90366604425 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666484751750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948343566605 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.628332 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772164122000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97157580000 # Time in different power states +system.physmem.readRowHits 136095 # Number of row buffer hits during reads +system.physmem.writeRowHits 89528 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.96 # Row buffer hit rate for writes +system.physmem.avgGap 10089278.46 # Average gap between requests +system.physmem.pageHitRate 79.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230829480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125948625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702195000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90325761075 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666515907500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948333254960 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.626580 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772215900000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40267816750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40208512500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213403680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116440500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596622000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370740240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88072375230 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668497233500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947907041630 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.478302 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775541834250 # Time in different power states -system.physmem_1.memoryStateTime::REF 97157580000 # Time in different power states +system.physmem_1.actEnergy 213260040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116362125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596668800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190039717920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88049301345 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668512802000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947898845990 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.477277 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775567504000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36896609250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36861865500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -370,9 +367,9 @@ system.cpu.dtb.walker.walkWaitTime::samples 9546 # system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8540.848722 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13159.035492 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10920.963738 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8541.710442 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency @@ -392,9 +389,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520178 # DTB read hits +system.cpu.dtb.read_hits 24520655 # DTB read hits system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606457 # DTB write hits +system.cpu.dtb.write_hits 19606816 # DTB write hits system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -405,12 +402,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528302 # DTB read accesses -system.cpu.dtb.write_accesses 19607879 # DTB write accesses +system.cpu.dtb.read_accesses 24528779 # DTB read accesses +system.cpu.dtb.write_accesses 19608238 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44126635 # DTB hits +system.cpu.dtb.hits 44127471 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44136181 # DTB accesses +system.cpu.dtb.accesses 44137017 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,7 +465,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115552414 # ITB inst hits +system.cpu.itb.inst_hits 115554258 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -485,40 +482,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115557177 # ITB inst accesses -system.cpu.itb.hits 115552414 # DTB hits +system.cpu.itb.inst_accesses 115559021 # ITB inst accesses +system.cpu.itb.hits 115554258 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115557177 # DTB accesses -system.cpu.numCycles 5819192343 # number of cpu cycles simulated +system.cpu.itb.accesses 115559021 # DTB accesses +system.cpu.numCycles 5819173675 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112455206 # Number of instructions committed -system.cpu.committedOps 135585876 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119891340 # Number of integer alu accesses +system.cpu.committedInsts 112457033 # Number of instructions committed +system.cpu.committedOps 135588117 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119893391 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9892021 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15230391 # number of instructions that are conditional controls -system.cpu.num_int_insts 119891340 # number of integer instructions +system.cpu.num_func_calls 9892146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230571 # number of instructions that are conditional controls +system.cpu.num_int_insts 119893391 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218059811 # number of times the integer registers were read -system.cpu.num_int_register_writes 82644916 # number of times the integer registers were written +system.cpu.num_int_register_reads 218063465 # number of times the integer registers were read +system.cpu.num_int_register_writes 82646448 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489735153 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51893214 # number of times the CC registers were written -system.cpu.num_mem_refs 45407055 # number of memory refs -system.cpu.num_load_insts 24842618 # Number of load instructions -system.cpu.num_store_insts 20564437 # Number of store instructions -system.cpu.num_idle_cycles 5379072985.844151 # Number of idle cycles -system.cpu.num_busy_cycles 440119357.155849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075632 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924368 # Percentage of idle cycles -system.cpu.Branches 25916470 # Number of branches fetched +system.cpu.num_cc_register_reads 489743456 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51893999 # number of times the CC registers were written +system.cpu.num_mem_refs 45407924 # number of memory refs +system.cpu.num_load_insts 24843119 # Number of load instructions +system.cpu.num_store_insts 20564805 # Number of store instructions +system.cpu.num_idle_cycles 5379054575.844151 # Number of idle cycles +system.cpu.num_busy_cycles 440119099.155849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075633 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924367 # Percentage of idle cycles +system.cpu.Branches 25916787 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93173703 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114388 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93175095 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114406 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -546,18 +543,18 @@ system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24842618 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24843119 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20564805 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138705936 # Class of executed instruction -system.cpu.dcache.tags.replacements 819217 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235406 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819729 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.743536 # Average number of references to valid blocks. +system.cpu.op_class::total 138708215 # Class of executed instruction +system.cpu.dcache.tags.replacements 819223 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.702328 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43236235 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819735 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.744161 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.702328 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -566,152 +563,152 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177109321 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177109321 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112521 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112521 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18823879 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18823879 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392783 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392783 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443242 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443242 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460216 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460216 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329183 # number of overall hits -system.cpu.dcache.overall_hits::total 42329183 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 399911 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 399911 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298704 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298704 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118377 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118377 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177112671 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177112671 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112983 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112983 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18824226 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18824226 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392786 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392786 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443250 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443250 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460223 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460223 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41937209 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41937209 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329995 # number of overall hits +system.cpu.dcache.overall_hits::total 42329995 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 399912 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 399912 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298709 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298709 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118381 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118381 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22756 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 698615 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 698615 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 816992 # number of overall misses -system.cpu.dcache.overall_misses::total 816992 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6486417000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6486417000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19109109000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19109109000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294489000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 294489000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 698621 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 698621 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 817002 # number of overall misses +system.cpu.dcache.overall_misses::total 817002 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6488404500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6488404500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19100944000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19100944000 # number of WriteReq miss cycles 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-system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511160 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511160 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465999 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465999 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460218 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460218 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43146175 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43146175 # number of overall (read+write) accesses +system.cpu.dcache.demand_miss_latency::cpu.data 25589348500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25589348500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25589348500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25589348500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512895 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19122935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511167 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511167 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466006 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466006 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635830 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635830 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146997 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146997 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231585 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231585 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048835 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048835 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231590 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231590 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048832 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048832 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709 # average LoadLockedReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16224.580658 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16224.580658 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63944.989940 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63944.989940 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12915.099314 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12915.099314 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36637.527107 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31328.979966 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36628.370032 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36628.370032 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31321.035322 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31321.035322 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 683842 # number of writebacks -system.cpu.dcache.writebacks::total 683842 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 930 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 930 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14247 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14247 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 930 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 930 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 930 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 930 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398981 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 398981 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298704 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298704 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116321 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116321 # number of SoftPFReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683846 # number of writebacks +system.cpu.dcache.writebacks::total 683846 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 929 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 929 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14246 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14246 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 929 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 929 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 929 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 929 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398983 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 398983 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298709 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298709 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116322 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116322 # number of SoftPFReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 697685 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 697685 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 814006 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 814006 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 697692 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 697692 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 814014 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 814014 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of 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uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368149500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24860984500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24860984500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26477503500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26477503500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278149500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278149500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089976500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089976500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368126000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368126000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227563 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227563 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227562 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227562 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses @@ -720,34 +717,34 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908 # average SoftPFReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15185.482840 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15185.482840 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62944.989940 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62944.989940 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13896.932652 # average SoftPFReq mshr miss latency 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-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35633.179827 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35633.179827 # average overall mshr miss latency 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misses that were no-allocate -system.cpu.icache.tags.replacements 1695565 # number of replacements -system.cpu.icache.tags.tagsinuse 510.436866 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113856331 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696077 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.129223 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1695721 # number of replacements +system.cpu.icache.tags.tagsinuse 510.436852 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113858019 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696233 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.124044 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.436866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.436852 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -756,44 +753,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117248497 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117248497 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113856331 # 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for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.383289 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14309.383289 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14309.383289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.383289 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14309.383289 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,218 +799,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles 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+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172107 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68032.275711 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68032.275711 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117082.280298 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117082.280298 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120787.323395 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122705.372546 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122705.372546 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120787.323395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117567.444679 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117931.820611 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189119.532404 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.149402 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.238066 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.238066 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.309789 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.536023 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5052537 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536723 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052863 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536887 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38132 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2287321 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287480 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801217 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1664795 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 134627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1695721 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 141985 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696083 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 524040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295944 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295944 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 524043 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574565 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5106210 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581942 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25654 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7688448 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215130168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96426845 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25651 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7727060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217119416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96427485 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31268 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311604445 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175875 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2773837 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.020867 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.142939 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313594321 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175889 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2774012 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020868 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142944 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2715955 97.91% 97.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 57882 2.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2716123 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57889 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2773837 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4957294000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2774012 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957617000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2553146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553380500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1275944500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275954500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1246,7 +1243,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46338000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46336500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1280,25 +1277,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186221548 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187058527 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084130 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084082 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313812613000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084130 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313812610000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084082 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067755 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067755 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1312,14 +1309,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28228376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28228376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4717653172 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4717653172 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28228376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28228376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28228376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28228376 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4549133150 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4549133150 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1336,19 +1333,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123808.666667 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123808.666667 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123808.666667 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 910 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125583.401888 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125583.401888 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.234568 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1362,14 +1359,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16828376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16828376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906453172 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2906453172 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16828376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16828376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16828376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16828376 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736521626 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736521626 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1378,68 +1375,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75544.435347 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75544.435347 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70545 # Transaction distribution +system.membus.trans_dist::ReadResp 70548 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution -system.membus.trans_dist::CleanEvict 6392 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::CleanEvict 6608 # Transaction distribution system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 127158 # Transaction distribution system.membus.trans_dist::ReadExResp 127158 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438817 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 434329 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 541921 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 614806 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302332 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465685 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782805 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389997 # Request fanout histogram +system.membus.snoop_fanout::samples 390011 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389997 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390011 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389997 # Request fanout histogram -system.membus.reqLayer0.occupancy 90470000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390011 # Request fanout histogram +system.membus.reqLayer0.occupancy 90460500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1730500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823068661 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823136860 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952238748 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943248500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64113741 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1186623 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index db18bd84f..e0084d588 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867052000 # Number of ticks simulated -final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.783855 # Number of seconds simulated +sim_ticks 2783854535000 # Number of ticks simulated +final_tick 2783854535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540105 # Simulator instruction rate (inst/s) -host_op_rate 657491 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10531274508 # Simulator tick rate (ticks/s) -host_mem_usage 560892 # Number of bytes of host memory used -host_seconds 264.34 # Real time elapsed on the host -sim_insts 142772879 # Number of instructions simulated -sim_ops 173803124 # Number of ops (including micro ops) simulated +host_inst_rate 1278958 # Simulator instruction rate (inst/s) +host_op_rate 1556926 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24937950041 # Simulator tick rate (ticks/s) +host_mem_usage 579412 # Number of bytes of host memory used +host_seconds 111.63 # Real time elapsed on the host +sim_insts 142771651 # Number of instructions simulated +sim_ops 173801592 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 725796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4660896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 724196 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660000 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 481216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5663620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 482816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5664516 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 11533000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 725796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 481216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724196 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 482816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8840512 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 8840576 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8858036 # Number of bytes written to this memory +system.physmem.bytes_written::total 8858100 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19769 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73331 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 88495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7544 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 88509 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 189176 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138133 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 138134 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142514 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142515 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 260715 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1674252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 260141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1673938 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 172859 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2034443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 173434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034774 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4142798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260715 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 172859 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 433574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3175623 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4142817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 260141 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 173434 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3175660 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3181918 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3175623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3181955 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3175660 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260715 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1680544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 260141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1680230 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 172859 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2034446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 173434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2034777 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7324716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7324772 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5683 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5683 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5683 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5683 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5703 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5703 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5703 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5703 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5703 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.40% 65.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1613 34.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4662 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3075 65.68% 65.68% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1607 34.32% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4682 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5703 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5683 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4662 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5703 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4682 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4662 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10345 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10385 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15994593 # DTB read hits -system.cpu0.dtb.read_misses 4788 # DTB read misses -system.cpu0.dtb.write_hits 11285810 # DTB write hits -system.cpu0.dtb.write_misses 895 # DTB write misses +system.cpu0.dtb.read_hits 15997085 # DTB read hits +system.cpu0.dtb.read_misses 4809 # DTB read misses +system.cpu0.dtb.write_hits 11281852 # DTB write hits +system.cpu0.dtb.write_misses 894 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 773 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 15999381 # DTB read accesses -system.cpu0.dtb.write_accesses 11286705 # DTB write accesses +system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16001894 # DTB read accesses +system.cpu0.dtb.write_accesses 11282746 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27280403 # DTB hits -system.cpu0.dtb.misses 5683 # DTB misses -system.cpu0.dtb.accesses 27286086 # DTB accesses +system.cpu0.dtb.hits 27278937 # DTB hits +system.cpu0.dtb.misses 5703 # DTB misses +system.cpu0.dtb.accesses 27284640 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -184,206 +184,206 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2611 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2611 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2611 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2611 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2611 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 2590 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2590 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2590 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2590 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2590 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1374 72.85% 72.85% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 512 27.15% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1886 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1366 72.81% 72.81% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 510 27.19% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1876 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2611 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2611 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2590 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74779098 # ITB inst hits -system.cpu0.itb.inst_misses 2611 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4466 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74797685 # ITB inst hits +system.cpu0.itb.inst_misses 2590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2813 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1917 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74781709 # ITB inst accesses -system.cpu0.itb.hits 74779098 # DTB hits -system.cpu0.itb.misses 2611 # DTB misses -system.cpu0.itb.accesses 74781709 # DTB accesses -system.cpu0.numCycles 5536444792 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74800275 # ITB inst accesses +system.cpu0.itb.hits 74797685 # DTB hits +system.cpu0.itb.misses 2590 # DTB misses +system.cpu0.itb.accesses 74800275 # DTB accesses +system.cpu0.numCycles 5536444787 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu0.committedInsts 72626333 # Number of instructions committed -system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5256 # Number of float alu accesses -system.cpu0.num_func_calls 8692525 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458276 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77485858 # number of integer instructions -system.cpu0.num_fp_insts 5256 # number of float instructions -system.cpu0.num_int_register_reads 144065688 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54441738 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4098 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268855171 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31825079 # number of times the CC registers were written -system.cpu0.num_mem_refs 27911721 # number of memory refs -system.cpu0.num_load_insts 16162181 # Number of load instructions -system.cpu0.num_store_insts 11749540 # Number of store instructions -system.cpu0.num_idle_cycles 5353607317.458248 # Number of idle cycles -system.cpu0.num_busy_cycles 182837474.541752 # Number of busy cycles -system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles -system.cpu0.Branches 18597106 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61764727 68.82% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59660 0.07% 68.89% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4403 0.00% 68.90% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed +system.cpu0.committedInsts 72639178 # Number of instructions committed +system.cpu0.committedOps 87981810 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77492203 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses +system.cpu0.num_func_calls 8694463 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9459638 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77492203 # number of integer instructions +system.cpu0.num_fp_insts 5289 # number of float instructions +system.cpu0.num_int_register_reads 144072055 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54447583 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 268879809 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31833575 # number of times the CC registers were written +system.cpu0.num_mem_refs 27909868 # number of memory refs +system.cpu0.num_load_insts 16164638 # Number of load instructions +system.cpu0.num_store_insts 11745230 # Number of store instructions +system.cpu0.num_idle_cycles 5353616276.220466 # Number of idle cycles +system.cpu0.num_busy_cycles 182828510.779535 # Number of busy cycles +system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles +system.cpu0.Branches 18600800 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 61776579 68.83% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4414 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16162181 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16164638 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11745230 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89742700 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819402 # number of replacements +system.cpu0.op_class::total 89752729 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819392 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597629 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53783791 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597669 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821817 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175357 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.830580 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.166594 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929357 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070638 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219237306 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219237306 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15302738 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14826284 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30129022 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10898497 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11441613 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186051 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209007 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395058 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235059 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222271 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236765 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223371 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26201235 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26267897 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52469132 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26387286 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26476904 # number of overall hits -system.cpu0.dcache.overall_hits::total 52864190 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197065 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199241 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396306 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137741 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 163937 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54401 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61672 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 219234764 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219234764 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15305281 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14823482 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30128763 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10894769 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11445022 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22339791 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 185755 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209286 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395041 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234992 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222324 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 457316 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236691 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223431 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 26200050 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26268504 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52468554 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26385805 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26477790 # number of overall hits +system.cpu0.dcache.overall_hits::total 52863595 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197438 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 198880 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396318 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137575 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 164088 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 301663 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54345 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61721 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 116066 # number of SoftPFReq misses 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of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025525 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036238 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605550 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240452 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270679 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511131 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239721 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226238 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236765 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223373 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26536041 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631075 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26776493 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26901754 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53678247 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 335013 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 362968 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697981 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389358 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424689 # number of overall misses +system.cpu0.dcache.overall_misses::total 814047 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15502719 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15022362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525081 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11032344 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11609110 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641454 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240100 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 271007 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511107 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239655 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226290 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236691 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223433 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 26535063 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631472 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53166535 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26775163 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26902479 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53677642 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012736 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013239 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012481 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014126 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226245 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227842 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227091 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019448 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012470 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014134 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226343 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227747 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227087 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019457 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017526 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013637 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012625 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013629 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014542 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015786 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.015165 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682264 # number of writebacks -system.cpu0.dcache.writebacks::total 682264 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682241 # number of writebacks +system.cpu0.dcache.writebacks::total 682241 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699214 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145342721 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1698998 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 145341757 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699510 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.519801 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127325 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536356 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110423 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121661 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542018 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -413,44 +413,44 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148742185 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148742185 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73936444 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71406277 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145342721 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73936444 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71406277 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145342721 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73936444 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71406277 # number of overall hits -system.cpu0.icache.overall_hits::total 145342721 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844540 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855192 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699732 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844540 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855192 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699732 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844540 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855192 # number of overall misses -system.cpu0.icache.overall_misses::total 1699732 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74780984 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261469 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74780984 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72261469 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74780984 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72261469 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011835 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011835 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011835 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 148740789 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148740789 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73955506 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71386251 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145341757 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73955506 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71386251 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145341757 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73955506 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71386251 # number of overall hits +system.cpu0.icache.overall_hits::total 145341757 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844055 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855461 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699516 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844055 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855461 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699516 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844055 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855461 # number of overall misses +system.cpu0.icache.overall_misses::total 1699516 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74799561 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72241712 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147041273 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74799561 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72241712 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147041273 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74799561 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72241712 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147041273 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011284 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011842 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011284 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,8 +459,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1699214 # number of writebacks -system.cpu0.icache.writebacks::total 1699214 # number of writebacks +system.cpu0.icache.writebacks::writebacks 1698998 # number of writebacks +system.cpu0.icache.writebacks::total 1698998 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -491,45 +491,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6203 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6203 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 6203 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6203 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6203 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 6189 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6189 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 6189 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6189 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6189 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000002000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000002000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000002000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3703 73.18% 73.18% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1357 26.82% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5060 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6203 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3697 73.27% 73.27% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1349 26.73% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5046 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6189 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6203 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6189 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5046 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5046 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 11235 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15529940 # DTB read hits -system.cpu1.dtb.read_misses 5414 # DTB read misses -system.cpu1.dtb.write_hits 11838406 # DTB write hits -system.cpu1.dtb.write_misses 789 # DTB write misses +system.cpu1.dtb.read_hits 15527164 # DTB read hits +system.cpu1.dtb.read_misses 5392 # DTB read misses +system.cpu1.dtb.write_hits 11842009 # DTB write hits +system.cpu1.dtb.write_misses 797 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 909 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15535354 # DTB read accesses -system.cpu1.dtb.write_accesses 11839195 # DTB write accesses +system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 15532556 # DTB read accesses +system.cpu1.dtb.write_accesses 11842806 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368346 # DTB hits -system.cpu1.dtb.misses 6203 # DTB misses -system.cpu1.dtb.accesses 27374549 # DTB accesses +system.cpu1.dtb.hits 27369173 # DTB hits +system.cpu1.dtb.misses 6189 # DTB misses +system.cpu1.dtb.accesses 27375362 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -559,107 +559,107 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3041 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3041 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3041 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3041 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3041 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 3051 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3051 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3051 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1721 81.53% 81.53% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 390 18.47% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2111 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1721 81.56% 81.56% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 389 18.44% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3041 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3051 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3051 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2111 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2111 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5152 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72259358 # ITB inst hits -system.cpu1.itb.inst_misses 3041 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5161 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 72239602 # ITB inst hits +system.cpu1.itb.inst_misses 3051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2817 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2022 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72262399 # ITB inst accesses -system.cpu1.itb.hits 72259358 # DTB hits -system.cpu1.itb.misses 3041 # DTB misses -system.cpu1.itb.accesses 72262399 # DTB accesses -system.cpu1.numCycles 88040649 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72242653 # ITB inst accesses +system.cpu1.itb.hits 72239602 # DTB hits +system.cpu1.itb.misses 3051 # DTB misses +system.cpu1.itb.accesses 72242653 # DTB accesses +system.cpu1.numCycles 88015617 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 70146546 # Number of instructions committed -system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6228 # Number of float alu accesses -system.cpu1.num_func_calls 8181374 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9272054 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75676825 # number of integer instructions -system.cpu1.num_fp_insts 6228 # number of float instructions -system.cpu1.num_int_register_reads 140994115 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52737742 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4674 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261998832 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30539220 # number of times the CC registers were written -system.cpu1.num_mem_refs 28027555 # number of memory refs -system.cpu1.num_load_insts 15693703 # Number of load instructions -system.cpu1.num_store_insts 12333852 # Number of store instructions -system.cpu1.num_idle_cycles 85384966.713327 # Number of idle cycles -system.cpu1.num_busy_cycles 2655682.286673 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles -system.cpu1.Branches 17799875 # Number of branches fetched -system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59388111 67.89% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57232 0.07% 67.96% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4166 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15693703 17.94% 85.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Class of executed instruction +system.cpu1.committedInsts 70132473 # Number of instructions committed +system.cpu1.committedOps 85819782 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75669076 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses +system.cpu1.num_func_calls 8179499 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9270637 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75669076 # number of integer instructions +system.cpu1.num_fp_insts 6195 # number of float instructions +system.cpu1.num_int_register_reads 140985520 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52730881 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 261969734 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30530329 # number of times the CC registers were written +system.cpu1.num_mem_refs 28028748 # number of memory refs +system.cpu1.num_load_insts 15690947 # Number of load instructions +system.cpu1.num_store_insts 12337801 # Number of store instructions +system.cpu1.num_idle_cycles 85360941.513009 # Number of idle cycles +system.cpu1.num_busy_cycles 2654675.486991 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles +system.cpu1.Branches 17796178 # Number of branches fetched +system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 59375458 67.88% 67.88% # Class of executed instruction +system.cpu1.op_class::IntMult 57193 0.07% 67.95% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4155 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction +system.cpu1.op_class::MemRead 15690947 17.94% 85.89% # Class of executed instruction +system.cpu1.op_class::MemWrite 12337801 14.11% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87477212 # Class of executed instruction +system.cpu1.op_class::total 87465703 # Class of executed instruction system.iobus.trans_dist::ReadReq 30164 # Transaction distribution system.iobus.trans_dist::ReadResp 30164 # Transaction distribution system.iobus.trans_dist::WriteReq 59002 # Transaction distribution @@ -711,14 +711,14 @@ system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321 system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -760,27 +760,27 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 109907 # number of replacements -system.l2c.tags.tagsinuse 65155.309141 # Cycle average of tags in use -system.l2c.tags.total_refs 4528496 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 65155.314985 # Cycle average of tags in use +system.l2c.tags.total_refs 4528037 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 175188 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 25.849350 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 25.846730 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48764.072075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48764.087166 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5143.224775 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4734.504525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5143.112513 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4734.411223 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4025.377664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2484.226979 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4025.485555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2484.315404 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.744081 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.078479 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.072243 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.078478 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.072241 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061422 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037906 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037908 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id @@ -792,156 +792,156 @@ system.l2c.tags.age_task_id_blocks_1024::3 10699 # system.l2c.tags.age_task_id_blocks_1024::4 50642 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40608233 # Number of tag accesses -system.l2c.tags.data_accesses 40608233 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.l2c.ReadReq_hits::total 14441 # number of ReadReq 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# number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 682241 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1666999 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1666999 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72515 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78631 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 151146 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833751 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 847665 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1681416 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 246350 # number of ReadSharedReq hits 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number of overall hits -system.l2c.overall_hits::cpu0.inst 833751 # number of overall hits -system.l2c.overall_hits::cpu0.data 318865 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5001 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847665 # number of overall hits -system.l2c.overall_hits::cpu1.data 337726 # number of overall hits -system.l2c.overall_hits::total 2352448 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 72343 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78788 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 151131 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833292 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 847909 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1681201 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 246688 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 258762 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 505450 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4715 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2284 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833292 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 319031 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4980 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 847909 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337550 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352188 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4715 # number of overall hits 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number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2427 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855453 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427161 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2533833 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4720 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2285 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844046 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4982 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2427 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855453 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427161 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2533833 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000438 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.000555 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990491 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989290 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.468673 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.515947 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.494363 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012763 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008792 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010765 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038176 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021840 # miss rate for ReadSharedReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.469288 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.515431 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.494388 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.012741 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008819 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.038051 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021942 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::total 0.029871 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.012763 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187827 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008792 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209670 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.071680 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.012763 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187827 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008792 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209670 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.071680 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000438 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.012741 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209783 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.071688 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000438 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.012741 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209783 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.071688 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -950,15 +950,15 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101943 # number of writebacks -system.l2c.writebacks::total 101943 # number of writebacks +system.l2c.writebacks::writebacks 101944 # number of writebacks +system.l2c.writebacks::total 101944 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40087 # Transaction distribution system.membus.trans_dist::ReadResp 74196 # Transaction distribution system.membus.trans_dist::WriteReq 27546 # Transaction distribution system.membus.trans_dist::WriteResp 27546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138133 # Transaction distribution -system.membus.trans_dist::CleanEvict 7977 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138134 # Transaction distribution +system.membus.trans_dist::CleanEvict 8203 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution @@ -972,17 +972,17 @@ system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 506563 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::total 613923 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 723054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 723281 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091644 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18254617 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18091708 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18254681 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20586137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20586201 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 434809 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram @@ -1036,47 +1036,47 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5060706 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2541063 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 39274 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 420 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5060329 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2540912 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 71244 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 71251 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291780 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 682264 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1667206 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 129872 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 682241 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1698998 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 137151 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1699732 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5084714 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7721762 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215520120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96323169 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 311967917 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 182968 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5322627 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.018535 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.134877 # Request fanout histogram +system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1699516 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 521013 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5116074 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581970 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41562 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7760372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217540984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96321057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83124 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313986697 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 182969 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5322182 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.018547 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.134917 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 5223970 98.15% 98.15% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 98657 1.85% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 5223474 98.15% 98.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 98708 1.85% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5322627 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 5322182 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 5188d100d..cd3a72dfc 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909671 # Number of seconds simulated -sim_ticks 2909670971500 # Number of ticks simulated -final_tick 2909670971500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909645 # Number of seconds simulated +sim_ticks 2909644861500 # Number of ticks simulated +final_tick 2909644861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 317481 # Simulator instruction rate (inst/s) -host_op_rate 382781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8214526706 # Simulator tick rate (ticks/s) -host_mem_usage 561408 # Number of bytes of host memory used -host_seconds 354.21 # Real time elapsed on the host -sim_insts 112454909 # Number of instructions simulated -sim_ops 135585028 # Number of ops (including micro ops) simulated +host_inst_rate 955579 # Simulator instruction rate (inst/s) +host_op_rate 1152126 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24724694945 # Simulator tick rate (ticks/s) +host_mem_usage 580436 # Number of bytes of host memory used +host_seconds 117.68 # Real time elapsed on the host +sim_insts 112454211 # Number of instructions simulated +sim_ops 135584166 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 523360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4648320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 522464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4660352 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 663236 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4253220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 664132 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4241316 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 523360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 663236 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 522464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 664132 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13465 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73133 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73321 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13529 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66287 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166623 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 179869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1597541 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 179563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1601691 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 227942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1461753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 228252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1457675 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 179869 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 227942 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407811 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581713 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 179563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 228252 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581714 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587736 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587737 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 179869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1600584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 179563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1604733 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 227942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1464733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 228252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1460655 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166623 # Number of read requests accepted -system.physmem.writeReqs 121755 # Number of write requests accepted -system.physmem.readBursts 166623 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10657728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166625 # Number of read requests accepted +system.physmem.writeReqs 121754 # Number of write requests accepted +system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10658176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5824 # Total number of bytes read from write queue +system.physmem.bytesWritten 7541376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 91 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 47111 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10080 # Per bank write bursts system.physmem.perBankRdBursts::1 9979 # Per bank write bursts system.physmem.perBankRdBursts::2 10697 # Per bank write bursts -system.physmem.perBankRdBursts::3 10654 # Per bank write bursts +system.physmem.perBankRdBursts::3 10657 # Per bank write bursts system.physmem.perBankRdBursts::4 18793 # Per bank write bursts system.physmem.perBankRdBursts::5 9662 # Per bank write bursts system.physmem.perBankRdBursts::6 9670 # Per bank write bursts -system.physmem.perBankRdBursts::7 10489 # Per bank write bursts -system.physmem.perBankRdBursts::8 9276 # Per bank write bursts +system.physmem.perBankRdBursts::7 10491 # Per bank write bursts +system.physmem.perBankRdBursts::8 9280 # Per bank write bursts system.physmem.perBankRdBursts::9 9982 # Per bank write bursts system.physmem.perBankRdBursts::10 9231 # Per bank write bursts -system.physmem.perBankRdBursts::11 8676 # Per bank write bursts +system.physmem.perBankRdBursts::11 8678 # Per bank write bursts system.physmem.perBankRdBursts::12 9823 # Per bank write bursts system.physmem.perBankRdBursts::13 10380 # Per bank write bursts -system.physmem.perBankRdBursts::14 9722 # Per bank write bursts +system.physmem.perBankRdBursts::14 9718 # Per bank write bursts system.physmem.perBankRdBursts::15 9413 # Per bank write bursts system.physmem.perBankWrBursts::0 7393 # Per bank write bursts system.physmem.perBankWrBursts::1 7263 # Per bank write bursts system.physmem.perBankWrBursts::2 8284 # Per bank write bursts -system.physmem.perBankWrBursts::3 8167 # Per bank write bursts +system.physmem.perBankWrBursts::3 8168 # Per bank write bursts system.physmem.perBankWrBursts::4 7485 # Per bank write bursts system.physmem.perBankWrBursts::5 7265 # Per bank write bursts system.physmem.perBankWrBursts::6 7108 # Per bank write bursts @@ -107,30 +107,30 @@ system.physmem.perBankWrBursts::7 7667 # Pe system.physmem.perBankWrBursts::8 7080 # Per bank write bursts system.physmem.perBankWrBursts::9 7523 # Per bank write bursts system.physmem.perBankWrBursts::10 6694 # Per bank write bursts -system.physmem.perBankWrBursts::11 6468 # Per bank write bursts +system.physmem.perBankWrBursts::11 6470 # Per bank write bursts system.physmem.perBankWrBursts::12 7527 # Per bank write bursts system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7264 # Per bank write bursts +system.physmem.perBankWrBursts::14 7260 # Per bank write bursts system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2909670614500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 2909644504500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157051 # Read request sizes (log2) +system.physmem.readPktSize::6 157053 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117374 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117373 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 613 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -163,129 +163,134 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 189 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 175 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6917 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58603 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.549016 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.176876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.004841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21372 36.47% 36.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14638 24.98% 61.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6011 10.26% 71.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3214 5.48% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2514 4.29% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1548 2.64% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1052 1.80% 85.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1122 1.91% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7132 12.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58603 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5730 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.058290 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.635756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5727 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58581 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.672197 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.145957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.231527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21388 36.51% 36.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14603 24.93% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5975 10.20% 71.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3225 5.51% 77.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2561 4.37% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1528 2.61% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1012 1.73% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1135 1.94% 87.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7154 12.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58581 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.894255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 552.382236 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5567 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5730 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.564572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.725438 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.838937 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 17 0.30% 0.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.16% 0.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.14% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 11 0.19% 0.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4763 83.12% 83.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 132 2.30% 86.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 73 1.27% 87.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 203 3.54% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 27 0.47% 91.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 153 2.67% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 54 0.94% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.03% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.23% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.40% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 95.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.12% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 171 2.98% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.10% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.42% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 3 0.05% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.19% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5730 # Writes before turning the bus around for reads -system.physmem.totQLat 1612014000 # Total ticks spent queuing -system.physmem.totMemAccLat 4734395250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832635000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9680.20 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5570 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5570 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.155117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.796345 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 15.496905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 17 0.31% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 13 0.23% 0.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4758 85.42% 86.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 105 1.89% 88.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 66 1.18% 89.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 70 1.26% 90.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 40 0.72% 91.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.31% 91.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 48 0.86% 92.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.18% 92.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 152 2.73% 95.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.14% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.18% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 62 1.11% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.16% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 1 0.02% 97.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.48% 97.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 105 1.89% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.04% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.13% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5570 # Writes before turning the bus around for reads +system.physmem.totQLat 1610742500 # Total ticks spent queuing +system.physmem.totMemAccLat 4733255000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9672.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28430.20 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28422.15 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -295,40 +300,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.26 # Average write queue length when enqueuing -system.physmem.readRowHits 136241 # Number of row buffer hits during reads -system.physmem.writeRowHits 89517 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.81 # Row buffer hit rate for reads +system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing +system.physmem.readRowHits 136266 # Number of row buffer hits during reads +system.physmem.writeRowHits 89520 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 10089780.13 # Average gap between requests -system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230746320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125903250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702187200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90312406830 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666579011000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948388462040 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.625842 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772320056250 # Time in different power states -system.physmem_0.memoryStateTime::REF 97160180000 # Time in different power states +system.physmem.avgGap 10089654.60 # Average gap between requests +system.physmem.pageHitRate 79.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230678280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125866125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702226200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90291916755 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666582969500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948370345100 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624992 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772326098500 # Time in different power states +system.physmem_0.memoryStateTime::REF 97159400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40187145000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40158524000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 212292360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 115834125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370675440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88507788255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668162009750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1948010627610 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.495988 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774979616000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97160180000 # Time in different power states +system.physmem_1.actEnergy 212194080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 115780500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596731200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370662480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190043786400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88418921265 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668225948000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947984023925 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.492219 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775082980250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97159400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37531027500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37402333250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -378,59 +383,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6370 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6370 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1827 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4542 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walks 6403 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6403 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1830 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4572 # Level at which table walker walks with short descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6369 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5319 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13473.303252 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11679.114902 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7408.984019 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 3974 74.71% 74.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1341 25.21% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::samples 6402 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6402 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6402 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5332 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13399.287322 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11603.034588 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7407.871184 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4008 75.17% 75.17% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1320 24.76% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5319 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5332 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 2989035968 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::mean 0.330748 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::stdev 0.470482 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 2000419000 66.93% 66.93% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::1 988616968 33.07% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 2989035968 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3517 66.13% 66.13% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1801 33.87% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5318 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6370 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3528 66.18% 66.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1803 33.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5331 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6403 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6370 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5318 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6403 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5331 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5318 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 11688 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5331 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 11734 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12041748 # DTB read hits -system.cpu0.dtb.read_misses 5569 # DTB read misses -system.cpu0.dtb.write_hits 9609883 # DTB write hits -system.cpu0.dtb.write_misses 801 # DTB write misses +system.cpu0.dtb.read_hits 12042048 # DTB read hits +system.cpu0.dtb.read_misses 5594 # DTB read misses +system.cpu0.dtb.write_hits 9609454 # DTB write hits +system.cpu0.dtb.write_misses 809 # DTB write misses system.cpu0.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3992 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3984 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 860 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12047317 # DTB read accesses -system.cpu0.dtb.write_accesses 9610684 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12047642 # DTB read accesses +system.cpu0.dtb.write_accesses 9610263 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21651631 # DTB hits -system.cpu0.dtb.misses 6370 # DTB misses -system.cpu0.dtb.accesses 21658001 # DTB accesses +system.cpu0.dtb.hits 21651502 # DTB hits +system.cpu0.dtb.misses 6403 # DTB misses +system.cpu0.dtb.accesses 21657905 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,131 +465,131 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3218 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3218 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 687 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2531 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3218 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3218 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3218 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2361 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13277.424820 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11544.822386 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6544.721859 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 607 25.71% 25.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 660 27.95% 53.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 188 7.96% 61.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.39% 78.02% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.14% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 510 21.60% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 6 0.25% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2361 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3203 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3203 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 686 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2517 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3203 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3203 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2349 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13262.452107 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11543.567684 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6519.168051 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.54% 25.54% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 662 28.18% 53.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 191 8.13% 61.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.48% 78.33% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.46% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 498 21.20% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2349 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1674 70.90% 70.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 687 29.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2361 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1663 70.80% 70.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 686 29.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3218 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3218 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3203 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3203 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2361 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2361 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5579 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56731893 # ITB inst hits -system.cpu0.itb.inst_misses 3218 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5552 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56738612 # ITB inst hits +system.cpu0.itb.inst_misses 3203 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2380 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56735111 # ITB inst accesses -system.cpu0.itb.hits 56731893 # DTB hits -system.cpu0.itb.misses 3218 # DTB misses -system.cpu0.itb.accesses 56735111 # DTB accesses -system.cpu0.numCycles 2910044257 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56741815 # ITB inst accesses +system.cpu0.itb.hits 56738612 # DTB hits +system.cpu0.itb.misses 3203 # DTB misses +system.cpu0.itb.accesses 56741815 # DTB accesses +system.cpu0.numCycles 2910043779 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3034 # number of quiesce instructions executed -system.cpu0.committedInsts 55192175 # Number of instructions committed -system.cpu0.committedOps 66601030 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58838667 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5226 # Number of float alu accesses -system.cpu0.num_func_calls 4816070 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7555391 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58838667 # number of integer instructions -system.cpu0.num_fp_insts 5226 # number of float instructions -system.cpu0.num_int_register_reads 106920418 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40489001 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3747 # number of times the floating registers were read +system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu0.committedInsts 55199902 # Number of instructions committed +system.cpu0.committedOps 66610456 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58846956 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5257 # Number of float alu accesses +system.cpu0.num_func_calls 4818664 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7556613 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58846956 # number of integer instructions +system.cpu0.num_fp_insts 5257 # number of float instructions +system.cpu0.num_int_register_reads 106933232 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40497320 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3778 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240444662 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25665883 # number of times the CC registers were written -system.cpu0.num_mem_refs 22275144 # number of memory refs -system.cpu0.num_load_insts 12196401 # Number of load instructions -system.cpu0.num_store_insts 10078743 # Number of store instructions -system.cpu0.num_idle_cycles 2694612539.353109 # Number of idle cycles -system.cpu0.num_busy_cycles 215431717.646891 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074030 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925970 # Percentage of idle cycles -system.cpu0.Branches 12738975 # Number of branches fetched -system.cpu0.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45781986 67.21% 67.21% # Class of executed instruction -system.cpu0.op_class::IntMult 56167 0.08% 67.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3968 0.01% 67.30% # Class of executed instruction +system.cpu0.num_cc_register_reads 240479401 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25666284 # number of times the CC registers were written +system.cpu0.num_mem_refs 22274939 # number of memory refs +system.cpu0.num_load_insts 12196843 # Number of load instructions +system.cpu0.num_store_insts 10078096 # Number of store instructions +system.cpu0.num_idle_cycles 2694635007.442764 # Number of idle cycles +system.cpu0.num_busy_cycles 215408771.557236 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074023 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925977 # Percentage of idle cycles +system.cpu0.Branches 12742817 # Number of branches fetched +system.cpu0.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45792240 67.22% 67.22% # Class of executed instruction +system.cpu0.op_class::IntMult 56099 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12196401 17.90% 85.20% # Class of executed instruction -system.cpu0.op_class::MemWrite 10078743 14.80% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12196843 17.90% 85.21% # Class of executed instruction +system.cpu0.op_class::MemWrite 10078096 14.79% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68117399 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819062 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702235 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43234880 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819574 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.752869 # Average number of references to valid blocks. +system.cpu0.op_class::total 68127374 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819099 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702232 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43234609 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819611 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.750157 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309006 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393230 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914831 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.298558 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.403674 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084567 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914851 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id @@ -592,264 +597,264 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177106290 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177106290 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11353905 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11758208 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23112113 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9226963 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9596855 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18823818 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190234 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202489 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392723 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213697 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443247 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221754 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238460 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460214 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20580868 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21355063 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41935931 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20771102 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21557552 # number of overall hits -system.cpu0.dcache.overall_hits::total 42328654 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199783 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 200066 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399849 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149794 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 148846 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298640 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58818 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59499 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118317 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10855 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11895 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22750 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 177105423 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177105423 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11354436 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11757578 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23112014 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9226475 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9597217 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18823692 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190286 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202415 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392701 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213920 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229309 # number of LoadLockedReq hits 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cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24860467000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13588028000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12886389500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26474417500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3047137000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3231000000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278137000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2491876500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2598064000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089940500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5539013500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5829064000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368077500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017251 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016692 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015975 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015273 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231747 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223499 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227518 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017110 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019400 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018296 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12800137000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12046217500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24846354500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13597399500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12864629500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26462029000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3048418500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229696000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278114500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2495078000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594854500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089932500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5543496500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824550500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368047000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017211 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016733 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016968 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015957 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015292 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015618 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231519 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223736 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227529 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017071 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019430 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018292 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016679 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016055 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019208 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018529 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.191338 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14827.480312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15174.574606 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64746.605338 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61192.857047 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62975.371685 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13784.777449 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13975.723264 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13880.937637 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13579.776158 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13510.567891 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.754633 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016649 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016086 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016363 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019176 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018562 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018864 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.755732 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14832.352133 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15176.477518 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64921.476694 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60912.499413 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62920.874113 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13826.480178 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13963.453959 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13895.526046 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13581.834767 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13506.614039 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.473956 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36643.346147 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34632.739096 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.976495 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33400.343638 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31660.957171 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.448432 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203237.310745 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200123.877361 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.000835 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186364.258470 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182730.623154 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.663344 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195283.228741 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191979.185193 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.974032 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36732.498443 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34503.134899 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35616.754085 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33480.329007 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31550.673828 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32513.588065 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203227.900000 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200129.879787 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201622.278245 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186338.909634 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182749.102049 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.373373 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195262.293061 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191994.940172 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.454680 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1695832 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.436658 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113855734 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1696344 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.118305 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1695677 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.436645 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113855199 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1696189 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.124123 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 60.007721 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.428938 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117203 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879744 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.966796 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.469848 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117123 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879824 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id @@ -857,62 +862,62 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task 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0.014537 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014680 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.322369 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014679 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014808 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014555 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014679 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.202657 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.202657 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13150.458715 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13465.007868 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.202657 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency @@ -1007,54 +1012,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6967 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6967 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2209 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4758 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6967 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6967 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6967 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5854 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13310.386061 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11595.564813 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7355.876792 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5853 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 6953 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2221 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4731 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 6952 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6952 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6952 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5860 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13274.317406 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11562.470731 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7349.012526 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5859 99.98% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5854 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3666 62.62% 62.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2188 37.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5854 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6967 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 5860 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 292297068 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean -4.609996 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1639785500 561.00% 561.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1347488432 -461.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 292297068 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3658 62.43% 62.43% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2201 37.57% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5859 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6967 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5859 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5854 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12821 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5859 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12812 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12477838 # DTB read hits -system.cpu1.dtb.read_misses 5947 # DTB read misses -system.cpu1.dtb.write_hits 9996447 # DTB write hits -system.cpu1.dtb.write_misses 1020 # DTB write misses +system.cpu1.dtb.read_hits 12477429 # DTB read hits +system.cpu1.dtb.read_misses 5926 # DTB read misses +system.cpu1.dtb.write_hits 9996759 # DTB write hits +system.cpu1.dtb.write_misses 1027 # DTB write misses system.cpu1.dtb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4688 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4677 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12483785 # DTB read accesses -system.cpu1.dtb.write_accesses 9997467 # DTB write accesses +system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12483355 # DTB read accesses +system.cpu1.dtb.write_accesses 9997786 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22474285 # DTB hits -system.cpu1.dtb.misses 6967 # DTB misses -system.cpu1.dtb.accesses 22481252 # DTB accesses +system.cpu1.dtb.hits 22474188 # DTB hits +system.cpu1.dtb.misses 6953 # DTB misses +system.cpu1.dtb.accesses 22481141 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1084,85 +1092,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3507 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3507 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3507 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3507 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3507 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2709 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13994.462901 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12131.377414 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7198.145608 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1959 72.31% 72.31% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 749 27.65% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 3501 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3501 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 842 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2659 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3501 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3501 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3501 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2700 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13966.111111 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12105.021463 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7193.126612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1956 72.44% 72.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 743 27.52% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2709 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2700 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1869 68.99% 68.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 840 31.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2709 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1858 68.81% 68.81% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 842 31.19% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2700 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3507 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3507 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3501 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3501 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2709 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2709 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6216 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58820191 # ITB inst hits -system.cpu1.itb.inst_misses 3507 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2700 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2700 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6201 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58812782 # ITB inst hits +system.cpu1.itb.inst_misses 3501 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2941 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2713 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2701 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58823698 # ITB inst accesses -system.cpu1.itb.hits 58820191 # DTB hits -system.cpu1.itb.misses 3507 # DTB misses -system.cpu1.itb.accesses 58823698 # DTB accesses -system.cpu1.numCycles 2909297686 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58816283 # ITB inst accesses +system.cpu1.itb.hits 58812782 # DTB hits +system.cpu1.itb.misses 3501 # DTB misses +system.cpu1.itb.accesses 58816283 # DTB accesses +system.cpu1.numCycles 2909245944 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 57262734 # Number of instructions committed -system.cpu1.committedOps 68983998 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 61052130 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses -system.cpu1.num_func_calls 5075478 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7674901 # number of instructions that are conditional controls -system.cpu1.num_int_insts 61052130 # number of integer instructions -system.cpu1.num_fp_insts 5870 # number of float instructions -system.cpu1.num_int_register_reads 111137302 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42154976 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4637 # number of times the floating registers were read +system.cpu1.committedInsts 57254309 # Number of instructions committed +system.cpu1.committedOps 68973710 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 61043070 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5904 # Number of float alu accesses +system.cpu1.num_func_calls 5072826 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7673629 # number of instructions that are conditional controls +system.cpu1.num_int_insts 61043070 # number of integer instructions +system.cpu1.num_fp_insts 5904 # number of float instructions +system.cpu1.num_int_register_reads 111123439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42146017 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4671 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1234 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 249286409 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26228170 # number of times the CC registers were written -system.cpu1.num_mem_refs 23131429 # number of memory refs -system.cpu1.num_load_insts 12645834 # Number of load instructions -system.cpu1.num_store_insts 10485595 # Number of store instructions -system.cpu1.num_idle_cycles 2689887383.006891 # Number of idle cycles -system.cpu1.num_busy_cycles 219410302.993109 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075417 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924583 # Percentage of idle cycles -system.cpu1.Branches 13176890 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47391308 67.14% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 58256 0.08% 67.22% # Class of executed instruction +system.cpu1.num_cc_register_reads 249248543 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26227592 # number of times the CC registers were written +system.cpu1.num_mem_refs 23131346 # number of memory refs +system.cpu1.num_load_insts 12645224 # Number of load instructions +system.cpu1.num_store_insts 10486122 # Number of store instructions +system.cpu1.num_idle_cycles 2689856281.302534 # Number of idle cycles +system.cpu1.num_busy_cycles 219389662.697466 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles +system.cpu1.Branches 13172935 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47380499 67.13% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction @@ -1186,15 +1194,15 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4483 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4490 0.01% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12645834 17.92% 85.15% # Class of executed instruction -system.cpu1.op_class::MemWrite 10485595 14.85% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12645224 17.92% 85.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 10486122 14.86% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70587679 # Class of executed instruction +system.cpu1.op_class::total 70576858 # Class of executed instruction system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution @@ -1245,7 +1253,7 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46333000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1279,25 +1287,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6288000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6279500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 36457000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186225545 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187070020 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084397 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084263 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084397 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067775 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067775 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 313834387000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084263 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067766 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1311,14 +1319,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28184876 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28184876 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4715128669 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4715128669 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28184876 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28184876 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28184876 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28184876 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28181877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28181877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4548907143 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4548907143 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28181877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28181877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28181877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28181877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1335,19 +1343,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123617.877193 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123617.877193 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130165.875359 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130165.875359 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123617.877193 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123617.877193 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 572 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123604.723684 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123604.723684 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125577.162737 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125577.162737 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123604.723684 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123604.723684 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123604.723684 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.533333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1361,14 +1369,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16784876 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16784876 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2903928669 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2903928669 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16784876 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16784876 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16784876 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16784876 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16781877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16781877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736290629 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736290629 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16781877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16781877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16781877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16781877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1377,266 +1385,266 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73617.877193 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73617.877193 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80165.875359 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80165.875359 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73604.723684 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73604.723684 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75538.058442 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75538.058442 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73604.723684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73604.723684 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 87560 # number of replacements -system.l2c.tags.tagsinuse 64865.201521 # Cycle average of tags in use -system.l2c.tags.total_refs 4551354 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 152795 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.787323 # Average number of references to valid blocks. +system.l2c.tags.replacements 87562 # number of replacements +system.l2c.tags.tagsinuse 64865.213908 # Cycle average of tags in use +system.l2c.tags.total_refs 4551019 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152797 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.784741 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50199.128097 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4090.007642 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2504.647366 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838092 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 50199.163746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4089.871618 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2504.674114 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838098 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5610.818089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2455.856604 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5610.944787 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2455.815915 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062406 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.038218 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.085614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.085616 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.037473 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56202 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40566832 # Number of tag accesses -system.l2c.tags.data_accesses 40566832 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5848 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3044 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6379 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3501 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18772 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683867 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683867 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1665046 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1665046 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 40564313 # Number of tag accesses +system.l2c.tags.data_accesses 40564313 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5816 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6360 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3489 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18690 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683901 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683901 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1664900 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1664900 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81302 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 85662 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166964 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 833466 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 844870 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1678336 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 254311 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 257239 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511550 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 335613 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6379 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3501 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 844870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 342901 # number of demand (read+write) hits -system.l2c.demand_hits::total 2375622 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5848 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3044 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833466 # number of overall hits -system.l2c.overall_hits::cpu0.data 335613 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6379 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3501 # number of overall hits -system.l2c.overall_hits::cpu1.inst 844870 # number of overall hits -system.l2c.overall_hits::cpu1.data 342901 # number of overall hits -system.l2c.overall_hits::total 2375622 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 80918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 86062 # number of ReadExReq hits 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demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 845838 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 343844 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375425 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5816 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3025 # number of overall hits +system.l2c.overall_hits::cpu0.inst 832345 # number of overall hits +system.l2c.overall_hits::cpu0.data 334708 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3489 # number of overall hits +system.l2c.overall_hits::cpu1.inst 845838 # number of overall hits +system.l2c.overall_hits::cpu1.data 343844 # number of overall hits +system.l2c.overall_hits::total 2375425 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 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+system.l2c.ReadReq_mshr_miss_rate::total 0.000428 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989316 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.994122 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.452191 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.419099 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.435698 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025147 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062758 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062758 # mshr miss rate for overall accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.454046 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417232 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435672 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025197 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021303 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023238 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062762 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009297 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.180770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000287 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011878 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.163541 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062762 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70814.692982 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70806.122449 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70810.401460 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 68045.356371 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 68019.586105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 68032.640408 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116772.667670 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117387.576454 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117067.460225 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120786.779020 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122840.091463 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121422.651934 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122186.632158 # average ReadSharedReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116739.144971 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117299.126850 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117006.799212 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120763.335002 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122962.271341 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121727.766886 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122393.147646 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120592.049674 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117291.892331 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120894.915421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117668.756601 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117843.801471 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190734.109251 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190724.666667 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187620.439765 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172284.026394 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174859.098048 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171226.297651 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.933198 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187626.471682 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172283.466135 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174833.607170 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171244.911613 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.643227 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183250.511211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183229.728778 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179943.599117 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 172570.266720 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179959.208228 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 172569.816529 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution -system.membus.trans_dist::CleanEvict 6389 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4498 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution +system.membus.trans_dist::CleanEvict 6607 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4500 # Transaction distribution -system.membus.trans_dist::ReadExReq 127155 # Transaction distribution -system.membus.trans_dist::ReadExResp 127155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 127157 # Transaction distribution +system.membus.trans_dist::ReadExResp 127157 # Transaction distribution system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546405 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655299 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 434320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 541912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 614797 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15301948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15465301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782421 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389996 # Request fanout histogram +system.membus.snoop_fanout::samples 390010 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389996 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 390010 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389996 # Request fanout histogram -system.membus.reqLayer0.occupancy 90452500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 390010 # Request fanout histogram +system.membus.reqLayer0.occupancy 90443000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1723000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1721000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823109916 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823181865 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952195249 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 943214000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64063181 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1187123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1918,60 +1925,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5053996 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2538070 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38133 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5053855 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2538047 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 74719 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2295003 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74697 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2294848 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 801245 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1665046 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 134452 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 801289 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1695677 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 141805 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295877 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295877 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1696350 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 523949 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295892 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295892 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1696195 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523971 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5075755 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18469 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34870 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7703202 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215163192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96418525 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48936 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 311656837 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176461 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2781455 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021257 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144239 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5106078 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2581570 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18395 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34840 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7740883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 217113784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96423069 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 313611645 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176532 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2781330 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021292 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144357 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2722330 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 59125 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2722109 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59221 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2781455 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4961451000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2781330 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4961202000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2553547000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2553314500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275712000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275768500 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11923000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11880000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22636000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22657000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index ed0884673..926ea5f21 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.112152 # Number of seconds simulated -sim_ticks 5112152301500 # Number of ticks simulated -final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5112151729000 # Number of ticks simulated +final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 646932 # Simulator instruction rate (inst/s) -host_op_rate 1324411 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16530551683 # Simulator tick rate (ticks/s) -host_mem_usage 604676 # Number of bytes of host memory used -host_seconds 309.26 # Real time elapsed on the host -sim_insts 200066731 # Number of instructions simulated -sim_ops 409580371 # Number of ops (including micro ops) simulated +host_inst_rate 1266983 # Simulator instruction rate (inst/s) +host_op_rate 2593792 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32374197845 # Simulator tick rate (ticks/s) +host_mem_usage 659352 # Number of bytes of host memory used +host_seconds 157.91 # Real time elapsed on the host +sim_insts 200067055 # Number of instructions simulated +sim_ops 409581065 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory @@ -21,16 +21,16 @@ system.physmem.bytes_read::pc.south_bridge.ide 28352 system.physmem.bytes_read::total 11490752 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory -system.physmem.bytes_written::total 9270016 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 9269888 # Number of bytes written to this memory +system.physmem.bytes_written::total 9269888 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 179543 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144844 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 144842 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144842 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s) @@ -39,48 +39,48 @@ system.physmem.bw_read::pc.south_bridge.ide 5546 # system.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 1813305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1813305 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1813305 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4061038 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224308568 # number of cpu cycles simulated +system.cpu.numCycles 10224307424 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.committedInsts 200066731 # Number of instructions committed -system.cpu.committedOps 409580371 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses +system.cpu.committedInsts 200067055 # Number of instructions committed +system.cpu.committedOps 409581065 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374584177 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2308877 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 40001070 # number of instructions that are conditional controls -system.cpu.num_int_insts 374583495 # number of integer instructions +system.cpu.num_func_calls 2308905 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 40001120 # number of instructions that are conditional controls +system.cpu.num_int_insts 374584177 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 682689563 # number of times the integer registers were read -system.cpu.num_int_register_writes 323557658 # number of times the integer registers were written +system.cpu.num_int_register_reads 682690924 # number of times the integer registers were read +system.cpu.num_int_register_writes 323558192 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233837318 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157316420 # number of times the CC registers were written -system.cpu.num_mem_refs 35667022 # number of memory refs -system.cpu.num_load_insts 27243255 # Number of load instructions -system.cpu.num_store_insts 8423767 # Number of store instructions -system.cpu.num_idle_cycles 9770324721.656570 # Number of idle cycles -system.cpu.num_busy_cycles 453983846.343430 # Number of busy cycles +system.cpu.num_cc_register_reads 233837631 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157316591 # number of times the CC registers were written +system.cpu.num_mem_refs 35667176 # number of memory refs +system.cpu.num_load_insts 27243343 # Number of load instructions +system.cpu.num_store_insts 8423833 # Number of store instructions +system.cpu.num_idle_cycles 9770322790.617842 # Number of idle cycles +system.cpu.num_busy_cycles 453984633.382158 # Number of busy cycles system.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955598 # Percentage of idle cycles -system.cpu.Branches 43152159 # Number of branches fetched -system.cpu.op_class::No_OpClass 172754 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373476545 91.18% 91.23% # Class of executed instruction -system.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 123078 0.03% 91.29% # Class of executed instruction +system.cpu.Branches 43152262 # Number of branches fetched +system.cpu.op_class::No_OpClass 172765 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373477070 91.18% 91.23% # Class of executed instruction +system.cpu.op_class::IntMult 144574 0.04% 91.26% # Class of executed instruction +system.cpu.op_class::IntDiv 123086 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction @@ -107,16 +107,16 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27240665 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27240752 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8423833 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409581402 # Class of executed instruction -system.cpu.dcache.tags.replacements 1621902 # number of replacements +system.cpu.op_class::total 409582096 # Class of executed instruction +system.cpu.dcache.tags.replacements 1621909 # number of replacements system.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622414 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.438984 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20181333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622421 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.439024 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy @@ -126,48 +126,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 282 system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88836888 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88836888 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12023339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12023339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8096662 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8096662 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58900 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58900 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20120001 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20120001 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20178901 # number of overall hits -system.cpu.dcache.overall_hits::total 20178901 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905249 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905249 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316707 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316707 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402757 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402757 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1221956 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1221956 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624713 # number of overall misses -system.cpu.dcache.overall_misses::total 1624713 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12928588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12928588 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8413369 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8413369 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 88837527 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88837527 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12023410 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12023410 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8096819 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8096819 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58904 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58904 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20120229 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20120229 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20179133 # number of overall hits +system.cpu.dcache.overall_hits::total 20179133 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905268 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905268 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 316618 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 316618 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402753 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402753 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1221886 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1221886 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1624639 # number of overall misses +system.cpu.dcache.overall_misses::total 1624639 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12928678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12928678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8413437 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8413437 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21341957 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21341957 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21803614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21803614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070019 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070019 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037643 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037643 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872416 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872416 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057256 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057256 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074516 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074516 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 21342115 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21342115 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21803772 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21803772 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037632 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037632 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872407 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872407 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057252 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057252 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -176,16 +176,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535779 # number of writebacks -system.cpu.dcache.writebacks::total 1535779 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks +system.cpu.dcache.writebacks::total 1535790 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12940 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.666881 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013997 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id @@ -193,32 +193,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52753 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52753 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12941 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12941 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12941 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12941 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12941 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12941 # number of overall hits +system.cpu.dtb_walker_cache.tags.tag_accesses 52745 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52745 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12937 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12937 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12937 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12937 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12937 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12937 # number of overall hits system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21898 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21898 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21898 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21898 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21898 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21898 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409033 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409033 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409033 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409033 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409033 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409033 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409108 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409108 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409108 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409108 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -227,14 +227,14 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2453 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2453 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 792216 # number of replacements +system.cpu.icache.tags.replacements 792340 # number of replacements system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243675150 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 792728 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.388095 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy @@ -245,26 +245,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 130 system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245260620 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245260620 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243675150 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243675150 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243675150 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243675150 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243675150 # number of overall hits -system.cpu.icache.overall_hits::total 243675150 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 792735 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 792735 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 792735 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 792735 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 792735 # number of overall misses -system.cpu.icache.overall_misses::total 792735 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244467885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244467885 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244467885 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244467885 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244467885 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244467885 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 245261161 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245261161 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243675443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243675443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243675443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243675443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243675443 # number of overall hits +system.cpu.icache.overall_hits::total 243675443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792859 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792859 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792859 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792859 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792859 # number of overall misses +system.cpu.icache.overall_misses::total 792859 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244468302 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244468302 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244468302 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244468302 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244468302 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244468302 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses @@ -279,18 +279,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 792216 # number of writebacks -system.cpu.icache.writebacks::total 792216 # number of writebacks +system.cpu.icache.writebacks::writebacks 792340 # number of writebacks +system.cpu.icache.writebacks::total 792340 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.189160 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id @@ -334,61 +334,61 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 106204 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks. +system.cpu.l2cache.tags.replacements 106202 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135114 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.317021 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10436.512729 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits -system.cpu.l2cache.overall_hits::total 2244012 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39442 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39254568 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39254568 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1539387 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1539387 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 792329 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 792329 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 179766 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 179766 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779612 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 779612 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6533 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2871 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275070 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1284474 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6533 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2871 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 779612 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1454836 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2243852 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6533 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2871 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 779612 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1454836 # number of overall hits +system.cpu.l2cache.overall_hits::total 2243852 # number of overall hits +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1349 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1349 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses @@ -407,50 +407,50 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 5 system.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses system.cpu.l2cache.overall_misses::total 180051 # number of overall misses -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792722 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 792722 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6657 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2901 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307362 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1316920 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1621783 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2424063 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6657 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1539387 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1539387 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 792329 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 792329 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1661 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1661 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314413 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314413 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792846 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 792846 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6534 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2876 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307234 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1316644 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6534 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 2876 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792846 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1621647 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2423903 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6534 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 2876 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792846 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1621647 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2423903 # number of overall (read+write) accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.812161 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.812161 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428249 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428249 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016692 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016692 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000153 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001739 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024605 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024433 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000153 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001739 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016692 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102865 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074281 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000153 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001739 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016692 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -459,44 +459,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks -system.cpu.l2cache.writebacks::total 98177 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks +system.cpu.l2cache.writebacks::total 98175 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 203470 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 1539387 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 792340 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 93857 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314418 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 792859 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1321433 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378058 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 35029964 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101452736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551417 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 329920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 758656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 330092729 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 203468 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 18930863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 18911304 99.90% 99.90% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram @@ -504,7 +504,7 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 18930863 # Request fanout histogram system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution system.iobus.trans_dist::WriteReq 57724 # Transaction distribution @@ -558,14 +558,14 @@ system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbrid system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 47568 # number of replacements -system.iocache.tags.tagsinuse 0.042441 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.042439 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042439 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002652 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002652 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -610,11 +610,11 @@ system.membus.trans_dist::ReadReq 13857337 # Tr system.membus.trans_dist::ReadResp 13903644 # Transaction distribution system.membus.trans_dist::WriteReq 13943 # Transaction distribution system.membus.trans_dist::WriteResp 13943 # Transaction distribution -system.membus.trans_dist::WritebackDirty 144844 # Transaction distribution -system.membus.trans_dist::CleanEvict 8271 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2561 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2109 # Transaction distribution -system.membus.trans_dist::ReadExReq 134351 # Transaction distribution +system.membus.trans_dist::WritebackDirty 144842 # Transaction distribution +system.membus.trans_dist::CleanEvict 8802 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2189 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1650 # Transaction distribution +system.membus.trans_dist::ReadExReq 134346 # Transaction distribution system.membus.trans_dist::ReadExResp 134346 # Transaction distribution system.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution system.membus.trans_dist::MessageReq 1696 # Transaction distribution @@ -625,32 +625,32 @@ system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slav system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 469415 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28211975 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28358181 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43211961 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46263225 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 14256561 # Request fanout histogram +system.membus.snoop_fanout::samples 14256182 # Request fanout histogram system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.010907 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram +system.membus.snoop_fanout::1 14254486 99.99% 99.99% # Request fanout histogram system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 14256561 # Request fanout histogram +system.membus.snoop_fanout::total 14256182 # Request fanout histogram system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 0929c11b9..38633f47f 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.194947 # Number of seconds simulated -sim_ticks 5194947216500 # Number of ticks simulated -final_tick 5194947216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194946 # Number of seconds simulated +sim_ticks 5194946000500 # Number of ticks simulated +final_tick 5194946000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 404245 # Simulator instruction rate (inst/s) -host_op_rate 779175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16350714303 # Simulator tick rate (ticks/s) -host_mem_usage 604972 # Number of bytes of host memory used -host_seconds 317.72 # Real time elapsed on the host -sim_insts 128436556 # Number of instructions simulated -sim_ops 247559476 # Number of ops (including micro ops) simulated +host_inst_rate 842553 # Simulator instruction rate (inst/s) +host_op_rate 1624008 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34079125299 # Simulator tick rate (ticks/s) +host_mem_usage 659848 # Number of bytes of host memory used +host_seconds 152.44 # Real time elapsed on the host +sim_insts 128436892 # Number of instructions simulated +sim_ops 247560077 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 821184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9031104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9031168 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9881024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 821184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8151488 # Number of bytes written to this memory -system.physmem.bytes_written::total 8151488 # Number of bytes written to this memory +system.physmem.bytes_read::total 9881152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8151616 # Number of bytes written to this memory +system.physmem.bytes_written::total 8151616 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141111 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12832 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141112 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154391 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 127367 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127367 # Number of write requests responded to by this memory +system.physmem.num_reads::total 154393 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 127369 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127369 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738453 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1902045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1569119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1569119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1569119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1902070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158086 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1569144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1569144 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1569144 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 158086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738453 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3471164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154391 # Number of read requests accepted -system.physmem.writeReqs 127367 # Number of write requests accepted -system.physmem.readBursts 154391 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127367 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9871424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 8149376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9881024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8151488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 3471214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154393 # Number of read requests accepted +system.physmem.writeReqs 127369 # Number of write requests accepted +system.physmem.readBursts 154393 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127369 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9872000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue +system.physmem.bytesWritten 8149824 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9881152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8151616 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 55287 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10087 # Per bank write bursts -system.physmem.perBankRdBursts::1 9529 # Per bank write bursts +system.physmem.perBankRdBursts::1 9534 # Per bank write bursts system.physmem.perBankRdBursts::2 9814 # Per bank write bursts -system.physmem.perBankRdBursts::3 9652 # Per bank write bursts +system.physmem.perBankRdBursts::3 9653 # Per bank write bursts system.physmem.perBankRdBursts::4 10130 # Per bank write bursts -system.physmem.perBankRdBursts::5 9950 # Per bank write bursts +system.physmem.perBankRdBursts::5 9948 # Per bank write bursts system.physmem.perBankRdBursts::6 9317 # Per bank write bursts system.physmem.perBankRdBursts::7 9200 # Per bank write bursts system.physmem.perBankRdBursts::8 8918 # Per bank write bursts system.physmem.perBankRdBursts::9 9357 # Per bank write bursts -system.physmem.perBankRdBursts::10 9066 # Per bank write bursts +system.physmem.perBankRdBursts::10 9071 # Per bank write bursts system.physmem.perBankRdBursts::11 9331 # Per bank write bursts system.physmem.perBankRdBursts::12 9713 # Per bank write bursts system.physmem.perBankRdBursts::13 9915 # Per bank write bursts @@ -79,53 +79,53 @@ system.physmem.perBankRdBursts::15 10131 # Pe system.physmem.perBankWrBursts::0 8252 # Per bank write bursts system.physmem.perBankWrBursts::1 7742 # Per bank write bursts system.physmem.perBankWrBursts::2 7578 # Per bank write bursts -system.physmem.perBankWrBursts::3 7566 # Per bank write bursts +system.physmem.perBankWrBursts::3 7567 # Per bank write bursts system.physmem.perBankWrBursts::4 7987 # Per bank write bursts system.physmem.perBankWrBursts::5 8326 # Per bank write bursts -system.physmem.perBankWrBursts::6 7980 # Per bank write bursts +system.physmem.perBankWrBursts::6 7984 # Per bank write bursts system.physmem.perBankWrBursts::7 7858 # Per bank write bursts -system.physmem.perBankWrBursts::8 7446 # Per bank write bursts +system.physmem.perBankWrBursts::8 7447 # Per bank write bursts system.physmem.perBankWrBursts::9 8118 # Per bank write bursts system.physmem.perBankWrBursts::10 7706 # Per bank write bursts -system.physmem.perBankWrBursts::11 7948 # Per bank write bursts +system.physmem.perBankWrBursts::11 7949 # Per bank write bursts system.physmem.perBankWrBursts::12 8417 # Per bank write bursts system.physmem.perBankWrBursts::13 8510 # Per bank write bursts system.physmem.perBankWrBursts::14 8023 # Per bank write bursts system.physmem.perBankWrBursts::15 7877 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5194947155500 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 5194945939500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154391 # Read request sizes (log2) +system.physmem.readPktSize::6 154393 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127367 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127369 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2785 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -156,115 +156,114 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 316.988566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.004327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.313677 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20115 35.38% 35.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13762 24.21% 59.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6339 11.15% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3489 6.14% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2420 4.26% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.81% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1162 2.04% 85.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 977 1.72% 87.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6989 12.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56850 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5891 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.179766 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 623.896687 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5890 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 56869 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 316.898416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.066814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.232113 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20064 35.28% 35.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13820 24.30% 59.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6395 11.25% 70.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3441 6.05% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2422 4.26% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1595 2.80% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1163 2.05% 85.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 983 1.73% 87.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6986 12.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56869 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5701 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.056657 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 634.190971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5700 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5891 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5891 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.615006 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.434725 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.404388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4837 82.11% 82.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 110 1.87% 83.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 36 0.61% 84.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 242 4.11% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 18 0.31% 89.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 210 3.56% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 69 1.17% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.05% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.22% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 22 0.37% 94.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.14% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.10% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 244 4.14% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 27 0.46% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 2 0.03% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 18 0.31% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5891 # Writes before turning the bus around for reads -system.physmem.totQLat 1583291001 # Total ticks spent queuing -system.physmem.totMemAccLat 4475309751 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 771205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10265.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5701 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5700 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.339649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.500075 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.394307 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4849 85.07% 85.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 101 1.77% 86.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 44 0.77% 87.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 52 0.91% 88.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 17 0.30% 88.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.26% 89.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 60 1.05% 90.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.11% 90.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 207 3.63% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.18% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.11% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.28% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 91 1.60% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.11% 96.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.05% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 36 0.63% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 144 2.53% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.19% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.16% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.05% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5700 # Writes before turning the bus around for reads +system.physmem.totQLat 1573374325 # Total ticks spent queuing +system.physmem.totMemAccLat 4465561825 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 771250000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10200.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29015.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28950.16 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s @@ -274,74 +273,74 @@ system.physmem.busUtil 0.03 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 125535 # Number of row buffer hits during reads -system.physmem.writeRowHits 99190 # Number of row buffer hits during writes +system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing +system.physmem.readRowHits 125550 # Number of row buffer hits during reads +system.physmem.writeRowHits 99170 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.88 # Row buffer hit rate for writes -system.physmem.avgGap 18437620.78 # Average gap between requests +system.physmem.writeRowHitRate 77.86 # Row buffer hit rate for writes +system.physmem.avgGap 18437354.72 # Average gap between requests system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 210727440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114980250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 605896200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 410112720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 339308689200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 137072684295 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2996729192250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3474452282355 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.813767 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4985214188974 # Time in different power states +system.physmem_0.actEnergy 210916440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115083375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 605927400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 410119200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 339308180640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 137084456790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2996714193750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474448877595 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.814114 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985194974722 # Time in different power states system.physmem_0.memoryStateTime::REF 173470440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36262439776 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36280536278 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219058560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119526000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 597183600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 415011600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 339308689200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 137519874945 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2996336934750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3474516278655 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.826083 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4984554950984 # Time in different power states +system.physmem_1.actEnergy 218998080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119493000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 597214800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 415018080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 339308180640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137426526900 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996414132250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474499563750 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.823871 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984690777488 # Time in different power states system.physmem_1.memoryStateTime::REF 173470440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36921702766 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36784611512 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10389894433 # number of cpu cycles simulated +system.cpu.numCycles 10389892001 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.committedInsts 128436556 # Number of instructions committed -system.cpu.committedOps 247559476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232158308 # Number of integer alu accesses +system.cpu.committedInsts 128436892 # Number of instructions committed +system.cpu.committedOps 247560077 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232158810 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2315823 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23152916 # number of instructions that are conditional controls -system.cpu.num_int_insts 232158308 # number of integer instructions +system.cpu.num_func_calls 2315811 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23152999 # number of instructions that are conditional controls +system.cpu.num_int_insts 232158810 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 434959182 # number of times the integer registers were read -system.cpu.num_int_register_writes 197962963 # number of times the integer registers were written +system.cpu.num_int_register_reads 434959716 # number of times the integer registers were read +system.cpu.num_int_register_writes 197963277 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132872914 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95460933 # number of times the CC registers were written -system.cpu.num_mem_refs 22321110 # number of memory refs -system.cpu.num_load_insts 13911495 # Number of load instructions -system.cpu.num_store_insts 8409615 # Number of store instructions -system.cpu.num_idle_cycles 9773995534.086119 # Number of idle cycles -system.cpu.num_busy_cycles 615898898.913881 # Number of busy cycles -system.cpu.not_idle_fraction 0.059279 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940721 # Percentage of idle cycles -system.cpu.Branches 26327382 # Number of branches fetched -system.cpu.op_class::No_OpClass 172226 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224809718 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140099 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 122815 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 132873102 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95461248 # number of times the CC registers were written +system.cpu.num_mem_refs 22321002 # number of memory refs +system.cpu.num_load_insts 13911426 # Number of load instructions +system.cpu.num_store_insts 8409576 # Number of store instructions +system.cpu.num_idle_cycles 9774021635.086119 # Number of idle cycles +system.cpu.num_busy_cycles 615870365.913881 # Number of busy cycles +system.cpu.not_idle_fraction 0.059276 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940724 # Percentage of idle cycles +system.cpu.Branches 26327440 # Number of branches fetched +system.cpu.op_class::No_OpClass 172203 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224810530 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140088 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 122745 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -368,18 +367,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13906523 5.62% 96.60% # Class of executed instruction -system.cpu.op_class::MemWrite 8409615 3.40% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13906455 5.62% 96.60% # Class of executed instruction +system.cpu.op_class::MemWrite 8409576 3.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247561012 # Class of executed instruction -system.cpu.dcache.tags.replacements 1623700 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20139431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1624212 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.399509 # Average number of references to valid blocks. +system.cpu.op_class::total 247561613 # Class of executed instruction +system.cpu.dcache.tags.replacements 1623668 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.995482 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20139358 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1624180 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.399708 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995481 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.995482 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -388,148 +387,148 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88718097 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88718097 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12002646 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12002646 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8075476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8075476 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 88717633 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88717633 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12002599 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12002599 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8075450 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8075450 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20078122 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20078122 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20137214 # number of overall hits -system.cpu.dcache.overall_hits::total 20137214 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907311 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907311 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 326143 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 326143 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402797 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402797 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1233454 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1233454 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636251 # number of overall misses -system.cpu.dcache.overall_misses::total 1636251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13562069000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13562069000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18448528971 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18448528971 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32010597971 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32010597971 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32010597971 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32010597971 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12909957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12909957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8401619 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8401619 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461889 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461889 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21311576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21311576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21773465 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21773465 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070280 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070280 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038819 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038819 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872065 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872065 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057877 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057877 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075149 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.541692 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.541692 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56565.767075 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56565.767075 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.999808 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25951.999808 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.378706 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19563.378706 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18014 # number of cycles access was blocked +system.cpu.dcache.demand_hits::cpu.data 20078049 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20078049 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20137141 # number of overall hits +system.cpu.dcache.overall_hits::total 20137141 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907290 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907290 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326130 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326130 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402796 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402796 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1233420 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1233420 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636216 # number of overall misses +system.cpu.dcache.overall_misses::total 1636216 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13559380500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13559380500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18441171467 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18441171467 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32000551967 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32000551967 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32000551967 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32000551967 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12909889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12909889 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401580 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401580 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461888 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461888 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21311469 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21311469 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21773357 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21773357 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070279 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070279 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038818 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038818 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872064 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872064 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057876 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057876 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075148 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075148 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14944.924445 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14944.924445 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56545.461831 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56545.461831 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25944.570355 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25944.570355 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19557.657404 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19557.657404 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19286 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 511 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 514 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.252446 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.521401 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540805 # number of writebacks -system.cpu.dcache.writebacks::total 1540805 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9476 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9763 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9763 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9763 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9763 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907024 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907024 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316667 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316667 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402763 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402763 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1223691 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1223691 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626454 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626454 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 1540773 # number of writebacks +system.cpu.dcache.writebacks::total 1540773 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 285 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9475 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9475 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9760 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9760 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9760 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9760 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907005 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 907005 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316655 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 316655 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402762 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402762 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1223660 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1223660 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1626422 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1626422 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12652957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12652957000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148864471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148864471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516948000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516948000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801821471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29801821471 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318769471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36318769471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132083500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132083500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786304500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786304500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918388000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918388000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070258 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070258 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037691 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037691 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12650383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12650383500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17142668967 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17142668967 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6518448000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6518448000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29793052467 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29793052467 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36311500467 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36311500467 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132085000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132085000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786349500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786349500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918434500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918434500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070257 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070257 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037690 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037690 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057419 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057419 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074699 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074699 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13949.969350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13949.969350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54154.251851 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54154.251851 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.602488 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.602488 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.041560 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.041560 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22330.031757 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22330.031757 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.242696 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.242696 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.247943 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.247943 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057418 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057418 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074698 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074698 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13947.424215 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13947.424215 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54136.738618 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54136.738618 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16184.366946 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16184.366946 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24347.492332 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24347.492332 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22326.001780 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22326.001780 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.245442 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.245442 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7583 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.052194 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13349 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7599 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.756679 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163358790000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052194 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.replacements 7581 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.052199 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13343 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7597 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.756351 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163352546000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052199 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id @@ -538,44 +537,44 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53077 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53077 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13349 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13349 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13349 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13349 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13349 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13349 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8793 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8793 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8793 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8793 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8793 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8793 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96493000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96493000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96493000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 96493000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96493000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 96493000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22142 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22142 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22142 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22142 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22142 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22142 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397119 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397119 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397119 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397119 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397119 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397119 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10973.842830 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10973.842830 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10973.842830 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10973.842830 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 53059 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53059 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13343 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13343 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13343 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13343 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13343 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13343 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96450500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96450500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96450500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 96450500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96450500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 96450500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22134 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22134 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22134 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22134 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22134 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22134 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397172 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397172 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397172 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397172 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397172 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397172 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10971.504948 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10971.504948 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10971.504948 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10971.504948 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10971.504948 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,40 +583,40 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8793 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8793 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8793 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8793 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8793 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8793 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87700000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87700000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87700000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87700000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87700000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87700000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397119 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397119 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397119 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9973.842830 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2983 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2983 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8791 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8791 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8791 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8791 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8791 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8791 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87659500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87659500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87659500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87659500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87659500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87659500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397172 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397172 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397172 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397172 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9971.504948 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9971.504948 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9971.504948 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 790533 # number of replacements -system.cpu.icache.tags.tagsinuse 510.213577 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144635652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791045 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.841244 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 790489 # number of replacements +system.cpu.icache.tags.tagsinuse 510.213579 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144635934 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791001 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.851771 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.213577 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.213579 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996511 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -626,44 +625,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 161 system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146217756 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146217756 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144635652 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144635652 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144635652 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144635652 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144635652 # number of overall hits -system.cpu.icache.overall_hits::total 144635652 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791052 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791052 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791052 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791052 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791052 # number of overall misses -system.cpu.icache.overall_misses::total 791052 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11851389500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11851389500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11851389500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11851389500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11851389500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11851389500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145426704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145426704 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145426704 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145426704 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145426704 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145426704 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.808402 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14981.808402 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.808402 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14981.808402 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.808402 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14981.808402 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146217950 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146217950 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144635934 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144635934 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144635934 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144635934 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144635934 # number of overall hits +system.cpu.icache.overall_hits::total 144635934 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791008 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791008 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791008 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791008 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791008 # number of overall misses +system.cpu.icache.overall_misses::total 791008 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11846341000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11846341000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11846341000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11846341000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11846341000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11846341000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145426942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145426942 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145426942 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145426942 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145426942 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145426942 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005439 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005439 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005439 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005439 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005439 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005439 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14976.259406 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14976.259406 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14976.259406 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14976.259406 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14976.259406 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14976.259406 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -672,42 +671,42 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 790533 # number of writebacks -system.cpu.icache.writebacks::total 790533 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791052 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791052 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791052 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791052 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791052 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791052 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060337500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11060337500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060337500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11060337500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060337500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11060337500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.808402 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.808402 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.808402 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.808402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.808402 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.808402 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 790489 # number of writebacks +system.cpu.icache.writebacks::total 790489 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791008 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791008 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791008 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791008 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791008 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791008 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055333000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11055333000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11055333000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055333000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11055333000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005439 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005439 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005439 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005439 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13976.259406 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13976.259406 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13976.259406 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13976.259406 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.069434 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.069456 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5168964583500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069434 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191840 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191840 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.warmup_cycle 5168951189500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069456 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191841 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191841 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id @@ -730,12 +729,12 @@ system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4247 system.cpu.itb_walker_cache.demand_misses::total 4247 # number of demand (read+write) misses system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4247 # number of overall misses system.cpu.itb_walker_cache.overall_misses::total 4247 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 44886000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886000 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 44886000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44856000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44856000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44856000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 44856000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44856000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 44856000 # number of overall miss cycles system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) @@ -750,12 +749,12 @@ system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.347573 system.cpu.itb_walker_cache.demand_miss_rate::total 0.347573 # miss rate for demand accesses system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.347573 # miss rate for overall accesses system.cpu.itb_walker_cache.overall_miss_rate::total 0.347573 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10568.872145 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10568.872145 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10568.872145 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10568.872145 # average overall miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10561.808335 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10561.808335 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10561.808335 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10561.808335 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10561.808335 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10561.808335 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -772,36 +771,36 @@ system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 40639000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 40639000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 40639000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 40639000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 40639000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 40639000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 40609000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 40609000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 40609000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 40609000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 40609000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 40609000 # number of overall MSHR miss cycles system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.347630 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.347630 # mshr miss rate for ReadReq accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.347573 # mshr miss rate for demand accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses 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+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9561.808335 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9561.808335 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87285 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64590.437600 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4366421 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151981 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 28.730045 # Average number of references to valid blocks. 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requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 50117.131899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006347 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146883 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.599295 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.554060 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.764727 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy @@ -811,140 +810,140 @@ system.cpu.l2cache.tags.occ_percent::total 0.985572 # system.cpu.l2cache.tags.occ_task_id_blocks::1024 64696 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2800 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56265 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2801 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5467 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56270 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39229727 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39229727 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1544562 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1544562 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 790520 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 790520 # number of WritebackClean hits +system.cpu.l2cache.tags.tag_accesses 39228445 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39228445 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1544529 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1544529 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 790476 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 790476 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits 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-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021767 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021618 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063883 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063883 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117233.600853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117233.600853 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121899.158354 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121899.158354 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361003 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361003 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016224 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021769 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021619 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087472 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063886 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000155 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001749 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016224 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087472 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063886 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68681.009957 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68681.009957 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117215.115716 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117215.115716 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121541.104964 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121541.104964 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121574.822770 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121574.649123 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121537.531583 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121536.383412 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121899.158354 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118104.682197 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118419.234843 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 109000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121899.158354 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118104.682197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118419.234843 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.233544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.233544 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.080790 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.080790 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121541.104964 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118082.478329 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118369.037624 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.236290 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.236290 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4855758 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4855602 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425060 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11070 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2660536 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2660470 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1671931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 790520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 91754 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1671913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 790489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 97528 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 791052 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323669 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 791008 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323647 # Transaction distribution system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995599 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19573 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8396395 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101219776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 306160680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 189298 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3174835 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372492 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5996122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10488 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8401946 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101214976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204098920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 306151400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 189316 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3174772 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077863 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077876 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3163101 99.63% 99.63% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 9208 0.29% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2526 0.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3163038 99.63% 99.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 9206 0.29% 99.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2528 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3174835 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5050067000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3174772 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5049912000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1186578000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1186512000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2990780492 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2990732492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13189500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13186500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 216035 # Transaction distribution system.iobus.trans_dist::ReadResp 216035 # Transaction distribution @@ -1167,13 +1166,13 @@ system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 4013816 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 4014316 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 10045000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10060500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1094500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1191,7 +1190,7 @@ system.iobus.reqLayer10.occupancy 177500 # La system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 24284500 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 24285000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1201,7 +1200,7 @@ system.iobus.reqLayer16.occupancy 10500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 240815899 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 241923874 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1216500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -1212,12 +1211,12 @@ system.iobus.respLayer1.utilization 0.0 # La system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 47507 # number of replacements -system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.108260 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5048330960000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 5048330957000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108260 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1233,14 +1232,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 842 system.iocache.demand_misses::total 842 # number of demand (read+write) misses system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses system.iocache.overall_misses::total 842 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141163690 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 141163690 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6072614209 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 6072614209 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 141163690 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 141163690 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 141163690 # number of overall miss cycles -system.iocache.overall_miss_latency::total 141163690 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138525690 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 138525690 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 5867864184 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5867864184 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 138525690 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 138525690 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 138525690 # number of overall miss cycles +system.iocache.overall_miss_latency::total 138525690 # number of overall miss cycles system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) @@ -1257,19 +1256,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167652.838480 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129978.900021 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129978.900021 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167652.838480 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167652.838480 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 694 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 164519.821853 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 125596.408048 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125596.408048 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 164519.821853 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 164519.821853 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 428 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 67 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 33 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.358209 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.969697 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1283,14 +1282,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 99063690 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3736614209 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3736614209 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 99063690 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 99063690 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96425690 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3530059456 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3530059456 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 96425690 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 96425690 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1299,73 +1298,72 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117652.838480 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79978.900021 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.900021 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 114519.821853 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 75557.779452 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75557.779452 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 546346 # Transaction distribution -system.membus.trans_dist::ReadResp 588520 # Transaction distribution +system.membus.trans_dist::ReadResp 588523 # Transaction distribution system.membus.trans_dist::WriteReq 13920 # Transaction distribution system.membus.trans_dist::WriteResp 13920 # Transaction distribution -system.membus.trans_dist::WritebackDirty 127367 # Transaction distribution -system.membus.trans_dist::CleanEvict 6933 # Transaction distribution +system.membus.trans_dist::WritebackDirty 127369 # Transaction distribution +system.membus.trans_dist::CleanEvict 7403 # Transaction distribution system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution -system.membus.trans_dist::ReadExReq 113266 # Transaction distribution -system.membus.trans_dist::ReadExResp 113266 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 42174 # Transaction distribution +system.membus.trans_dist::UpgradeResp 18 # Transaction distribution +system.membus.trans_dist::ReadExReq 113265 # Transaction distribution +system.membus.trans_dist::ReadExResp 113265 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 42177 # Transaction distribution system.membus.trans_dist::MessageReq 1654 # Transaction distribution system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 399599 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1520131 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1665201 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397971 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1518503 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95512 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95512 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1617323 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586472 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19607872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19608128 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 1571 # Total snoops (count) -system.membus.snoop_fanout::samples 901008 # Request fanout histogram +system.membus.snoop_fanout::samples 901025 # Request fanout histogram system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 899354 99.82% 99.82% # Request fanout histogram +system.membus.snoop_fanout::1 899371 99.82% 99.82% # Request fanout histogram system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 2 # Request fanout histogram -system.membus.snoop_fanout::total 901008 # Request fanout histogram -system.membus.reqLayer0.occupancy 344294500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 901025 # Request fanout histogram +system.membus.reqLayer0.occupancy 344310500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 503567500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 503566000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 4013184 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 4013684 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 852595593 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 852733442 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 2359184 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 2359684 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1928199616 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1924956500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 85638132 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 4280140 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt index 0ee8e01b1..dc74457ff 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000121 # Nu sim_ticks 121460 # Number of ticks simulated final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19821 # Simulator instruction rate (inst/s) -host_op_rate 19819 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 376677 # Simulator tick rate (ticks/s) -host_mem_usage 390876 # Number of bytes of host memory used -host_seconds 0.32 # Real time elapsed on the host +host_inst_rate 58804 # Simulator instruction rate (inst/s) +host_op_rate 58798 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1117518 # Simulator tick rate (ticks/s) +host_mem_usage 412400 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 8c7fdbc65..adb01be8a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000109 # Nu sim_ticks 108694 # Number of ticks simulated final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18329 # Simulator instruction rate (inst/s) -host_op_rate 18327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 311726 # Simulator tick rate (ticks/s) -host_mem_usage 397240 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host +host_inst_rate 71872 # Simulator instruction rate (inst/s) +host_op_rate 71865 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1222276 # Simulator tick rate (ticks/s) +host_mem_usage 417856 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index d98266934..fc2b85717 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000087 # Nu sim_ticks 86673 # Number of ticks simulated final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 26202 # Simulator instruction rate (inst/s) -host_op_rate 26199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 355322 # Simulator tick rate (ticks/s) -host_mem_usage 391844 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 58973 # Simulator instruction rate (inst/s) +host_op_rate 58962 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 799609 # Simulator tick rate (ticks/s) +host_mem_usage 411856 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index ee921f3ab..cf623ae19 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107210 # Number of ticks simulated final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29228 # Simulator instruction rate (inst/s) -host_op_rate 29224 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 490268 # Simulator tick rate (ticks/s) -host_mem_usage 394320 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 108799 # Simulator instruction rate (inst/s) +host_op_rate 108769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1824399 # Simulator tick rate (ticks/s) +host_mem_usage 416280 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt index 55628ad16..a9f8176e1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000046 # Nu sim_ticks 45733 # Number of ticks simulated final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 16358 # Simulator instruction rate (inst/s) -host_op_rate 16355 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 290200 # Simulator tick rate (ticks/s) -host_mem_usage 389816 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 42490 # Simulator instruction rate (inst/s) +host_op_rate 42477 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 753627 # Simulator tick rate (ticks/s) +host_mem_usage 411088 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 4855f53c1..be4c58d22 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41712 # Number of ticks simulated final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12099 # Simulator instruction rate (inst/s) -host_op_rate 12098 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 195791 # Simulator tick rate (ticks/s) -host_mem_usage 393888 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 38081 # Simulator instruction rate (inst/s) +host_op_rate 38070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 616024 # Simulator tick rate (ticks/s) +host_mem_usage 414508 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index a8631d9c5..08266d48d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000033 # Nu sim_ticks 32936 # Number of ticks simulated final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 22566 # Simulator instruction rate (inst/s) -host_op_rate 22561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 288279 # Simulator tick rate (ticks/s) -host_mem_usage 390660 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 52774 # Simulator instruction rate (inst/s) +host_op_rate 52753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 673978 # Simulator tick rate (ticks/s) +host_mem_usage 411572 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index 7f8b12151..c437c6665 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000042 # Nu sim_ticks 41659 # Number of ticks simulated final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23573 # Simulator instruction rate (inst/s) -host_op_rate 23567 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 380874 # Simulator tick rate (ticks/s) -host_mem_usage 390976 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 41992 # Simulator instruction rate (inst/s) +host_op_rate 41979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 678429 # Simulator tick rate (ticks/s) +host_mem_usage 412928 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 5c45eaf46..586c80689 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000030 # Nu sim_ticks 29949500 # Number of ticks simulated final_tick 29949500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25443 # Simulator instruction rate (inst/s) -host_op_rate 29781 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 165422007 # Simulator tick rate (ticks/s) -host_mem_usage 247956 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 167534 # Simulator instruction rate (inst/s) +host_op_rate 196036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1088591965 # Simulator tick rate (ticks/s) +host_mem_usage 269228 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -755,17 +755,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30080 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.100427 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 3b3a0c7c5..f429492e1 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17170000 # Number of ticks simulated final_tick 17170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24070 # Simulator instruction rate (inst/s) -host_op_rate 28186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89974051 # Simulator tick rate (ticks/s) -host_mem_usage 249040 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 56453 # Simulator instruction rate (inst/s) +host_op_rate 66106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211025109 # Simulator tick rate (ticks/s) +host_mem_usage 270504 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1167,16 +1167,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 587 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 4d42e5502..63280507a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18741000 # Number of ticks simulated final_tick 18741000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27191 # Simulator instruction rate (inst/s) -host_op_rate 31839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110934081 # Simulator tick rate (ticks/s) -host_mem_usage 245436 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 84742 # Simulator instruction rate (inst/s) +host_op_rate 99228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 345728368 # Simulator tick rate (ticks/s) +host_mem_usage 266024 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1082,19 +1082,19 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 409 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 368 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 383 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 297 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 913 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 636 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 452 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 893 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.549832 # Request fanout histogram diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index be08dbe1d..83487a6ff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28298500 # Number of ticks simulated final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76228 # Simulator instruction rate (inst/s) -host_op_rate 88939 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 471979620 # Simulator tick rate (ticks/s) -host_mem_usage 246976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 286813 # Simulator instruction rate (inst/s) +host_op_rate 333728 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1769783602 # Simulator tick rate (ticks/s) +host_mem_usage 267436 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -556,16 +556,17 @@ system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt index 338e36e87..f933f7176 100644 --- a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000050 # Nu sim_ticks 49855000 # Number of ticks simulated final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93266 # Simulator instruction rate (inst/s) -host_op_rate 107828 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 931188295 # Simulator tick rate (ticks/s) -host_mem_usage 634440 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 411650 # Simulator instruction rate (inst/s) +host_op_rate 475781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4107877451 # Simulator tick rate (ticks/s) +host_mem_usage 655016 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4988 # Number of instructions simulated sim_ops 5770 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -629,13 +629,13 @@ system.l2bus.snoop_filter.tot_snoops 0 # To system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 348 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt index bf796f4ef..010db5b17 100644 --- a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000053 # Nu sim_ticks 53334000 # Number of ticks simulated final_tick 53334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45290 # Simulator instruction rate (inst/s) -host_op_rate 45279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 435170568 # Simulator tick rate (ticks/s) -host_mem_usage 616512 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 486070 # Simulator instruction rate (inst/s) +host_op_rate 485474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4661655450 # Simulator tick rate (ticks/s) +host_mem_usage 680524 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5548 # Number of instructions simulated sim_ops 5548 # Number of ops (including micro ops) simulated system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts @@ -508,13 +508,13 @@ system.l2bus.snoop_filter.tot_snoops 0 # To system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.trans_dist::ReadResp 315 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 71 # Transaction distribution system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 589 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 865 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 7302f4619..7b63e03f4 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.147149 # Nu sim_ticks 147148719500 # Number of ticks simulated final_tick 147148719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 392484 # Simulator instruction rate (inst/s) -host_op_rate 394434 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 637618235 # Simulator tick rate (ticks/s) -host_mem_usage 382304 # Number of bytes of host memory used -host_seconds 230.78 # Real time elapsed on the host +host_inst_rate 1174056 # Simulator instruction rate (inst/s) +host_op_rate 1179890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1907338487 # Simulator tick rate (ticks/s) +host_mem_usage 402756 # Number of bytes of host memory used +host_seconds 77.15 # Real time elapsed on the host sim_insts 90576862 # Number of instructions simulated sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -600,18 +600,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 255 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 368 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2837384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2837498 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 120942848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 120942912 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 947397 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000132 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 459938f5d..31446f740 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107836000 # Number of ticks simulated -final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107700000 # Number of ticks simulated +final_tick 107700000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68965 # Simulator instruction rate (inst/s) -host_op_rate 68965 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7480497 # Simulator tick rate (ticks/s) -host_mem_usage 247424 # Number of bytes of host memory used -host_seconds 14.42 # Real time elapsed on the host -sim_insts 994171 # Number of instructions simulated -sim_ops 994171 # Number of ops (including micro ops) simulated +host_inst_rate 155633 # Simulator instruction rate (inst/s) +host_op_rate 155632 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16853882 # Simulator tick rate (ticks/s) +host_mem_usage 312924 # Number of bytes of host memory used +host_seconds 6.39 # Real time elapsed on the host +sim_insts 994522 # Number of instructions simulated +sim_ops 994522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213927577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100427112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 48727948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11884865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 3565460 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7725162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1188487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7725162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 395171773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213927577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 48727948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 3565460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1188487 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267409471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213927577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100427112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 48727948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11884865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 3565460 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7725162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1188487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7725162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 395171773 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107808000 # Total gap between requests +system.physmem.totGap 107672000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -230,15 +230,15 @@ system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # By system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation -system.physmem.totQLat 6565250 # Total ticks spent queuing -system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6586250 # Total ticks spent queuing +system.physmem.totMemAccLat 19073750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9889.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28639.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.09 # Data bus utilization in percentage @@ -250,169 +250,169 @@ system.physmem.readRowHits 510 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161873.87 # Average gap between requests +system.physmem.avgGap 161669.67 # Average gap between requests system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.349855 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states +system.physmem_0.actBackEnergy 38199690 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27380250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76058610 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.484363 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47670750 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52812250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.346948 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states +system.physmem_1.actBackEnergy 32151420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32685750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74025645 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.451450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57549250 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43929750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81652 # Number of BP lookups -system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81595 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78953 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78929 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76214 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.560200 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215673 # number of cpu cycles simulated +system.cpu0.numCycles 215401 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19727 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482343 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81595 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76859 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165670 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched +system.cpu0.fetch.PendingTrapStallCycles 1993 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6732 # Number of cache lines fetched system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 188739 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.555609 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213598 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30459 16.14% 16.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78270 41.47% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 797 0.42% 58.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 613 0.32% 58.99% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73671 39.03% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2652 1.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 188739 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378805 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.239279 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15463 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18382 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152999 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 645 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 471851 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename +system.cpu0.rename.IdleCycles 16060 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2005 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15072 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152998 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1354 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 468673 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.SQFullEvents 851 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 320440 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 934717 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 705961 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307367 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13073 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4337 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 149926 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75817 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73307 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72919 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 392051 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388622 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12300 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11714 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 188739 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.059045 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.124370 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33524 17.76% 17.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4207 2.23% 19.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74141 39.28% 59.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73776 39.09% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1579 0.84% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 884 0.47% 99.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 404 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 188739 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 61 21.18% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.18% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 124 43.06% 64.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 35.76% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164274 42.27% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued @@ -441,40 +441,40 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149282 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75066 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued -system.cpu0.iq.rate 1.803221 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 388622 # Type of FU issued +system.cpu0.iq.rate 1.804179 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 288 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000741 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 966302 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405302 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 386770 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 388910 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72419 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking +system.cpu0.iew.iewBlockCycles 1969 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispatchedInsts 466549 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 149926 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75817 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -482,53 +482,53 @@ system.cpu0.iew.memOrderViolationEvents 63 # Nu system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed +system.cpu0.iew.iewExecutedInsts 387610 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 148943 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73663 # number of nop insts executed -system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76988 # Number of branches executed -system.cpu0.iew.exec_stores 74970 # Number of stores executed -system.cpu0.iew.exec_rate 1.798528 # Inst execution rate -system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 229603 # num instructions producing a value -system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value -system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit +system.cpu0.iew.exec_nop 73609 # number of nop insts executed +system.cpu0.iew.exec_refs 223859 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76931 # Number of branches executed +system.cpu0.iew.exec_stores 74916 # Number of stores executed +system.cpu0.iew.exec_rate 1.799481 # Inst execution rate +system.cpu0.iew.wb_sent 387178 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 386770 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229443 # num instructions producing a value +system.cpu0.iew.wb_consumers 232488 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.795581 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986903 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 13089 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186278 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.434007 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.148610 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33753 18.12% 18.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 76007 40.80% 58.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 664 0.36% 60.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 518 0.28% 60.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72154 38.73% 99.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 496 0.27% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453726 # Number of instructions committed -system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186278 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453402 # Number of instructions committed +system.cpu0.commit.committedOps 453402 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 221578 # Number of memory references committed -system.cpu0.commit.loads 147381 # Number of loads committed +system.cpu0.commit.refs 221416 # Number of memory references committed +system.cpu0.commit.loads 147273 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 76084 # Number of branches committed +system.cpu0.commit.branches 76030 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 305914 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305698 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72762 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159140 35.10% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -557,103 +557,103 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147357 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74143 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453402 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 651740 # The number of ROB reads -system.cpu0.rob.rob_writes 936154 # The number of ROB writes +system.cpu0.rob.rob_reads 651125 # The number of ROB reads +system.cpu0.rob.rob_writes 935459 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 380826 # Number of Instructions Simulated -system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693989 # number of integer regfile reads -system.cpu0.int_regfile_writes 312909 # number of integer regfile writes +system.cpu0.committedInsts 380556 # Number of Instructions Simulated +system.cpu0.committedOps 380556 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566017 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566017 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.766733 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.766733 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693485 # number of integer regfile reads +system.cpu0.int_regfile_writes 312678 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225727 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.118700 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149407 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 873.725146 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.118700 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275622 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275622 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 602739 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 602739 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75912 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75912 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73546 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73546 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits -system.cpu0.dcache.overall_hits::total 149559 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149458 # number of overall hits +system.cpu0.dcache.overall_hits::total 149458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 553 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 553 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses -system.cpu0.dcache.overall_misses::total 1114 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1108 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1108 # number of overall misses +system.cpu0.dcache.overall_misses::total 1108 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16789000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 16789000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34744480 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34744480 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 51533480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 51533480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 51533480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 51533480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76465 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76465 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74101 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74101 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150566 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150566 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150566 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150566 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007232 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007232 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007490 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007490 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007359 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007359 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007359 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007359 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30359.855335 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30359.855335 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62602.666667 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62602.666667 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46510.361011 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46510.361011 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46510.361011 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -664,107 +664,107 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 178 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 370 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 370 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 378 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 378 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 748 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 748 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 748 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 748 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6853000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8423500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8423500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15276500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15276500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15276500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15276500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002393 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002393 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002389 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002391 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002391 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002391 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37448.087432 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37448.087432 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47590.395480 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47590.395480 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42434.722222 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42434.722222 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.159002 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.159002 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471014 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471014 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits -system.cpu0.icache.overall_hits::total 5951 # number of overall hits +system.cpu0.icache.tags.tag_accesses 7339 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7339 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits +system.cpu0.icache.overall_hits::total 5949 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses system.cpu0.icache.overall_misses::total 783 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40394500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40394500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40394500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40394500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40394500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40394500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6732 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6732 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116310 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116310 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116310 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116310 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116310 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116310 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51589.399745 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51589.399745 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51589.399745 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51589.399745 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51589.399745 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -787,396 +787,397 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31312500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31312500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31312500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31312500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31312500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31312500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090315 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090315 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090315 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090315 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51500.822368 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51500.822368 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51500.822368 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 53782 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits +system.cpu1.branchPred.lookups 52270 # Number of BP lookups +system.cpu1.branchPred.condPredicted 48857 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 45038 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 43957 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.599805 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 912 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162898 # number of cpu cycles simulated +system.cpu1.numCycles 162626 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 30636 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 289541 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52270 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44869 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 123502 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 21117 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 458 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.849098 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199028 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 55186 35.24% 35.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51235 32.72% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6397 4.09% 72.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3507 2.24% 74.29% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 942 0.60% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 33361 21.31% 96.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1213 0.77% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 812 0.52% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3932 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156585 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.321412 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.780410 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17913 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 54188 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 79912 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3224 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1338 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 274398 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1338 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18610 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 24678 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13550 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 81416 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 16983 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 271226 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15241 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle +system.cpu1.rename.RenamedOperands 191192 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520363 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 405271 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 177667 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13525 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 21370 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76128 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 36144 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36135 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 31079 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225686 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6135 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 227404 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12625 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 706 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156585 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.452272 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.380275 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 58755 37.52% 37.52% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20747 13.25% 50.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35642 22.76% 73.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 35172 22.46% 96.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3374 2.15% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1612 1.03% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 878 0.56% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 207 0.13% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 198 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156585 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 24.01% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.01% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 41 12.46% 36.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 63.53% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 111654 49.10% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 80158 35.25% 84.35% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35592 15.65% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued -system.cpu1.iq.rate 1.445076 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 227404 # Type of FU issued +system.cpu1.iq.rate 1.398325 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 329 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001447 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 611730 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 244482 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 225916 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 227733 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30932 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1427 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7175 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 268817 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 146 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76128 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 36144 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 440 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1492 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 226425 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75137 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 979 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 38393 # number of nop insts executed -system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed -system.cpu1.iew.exec_branches 47858 # Number of branches executed -system.cpu1.iew.exec_stores 37349 # Number of stores executed -system.cpu1.iew.exec_rate 1.438864 # Inst execution rate -system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 133368 # num instructions producing a value -system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value -system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 36996 # number of nop insts executed +system.cpu1.iew.exec_refs 110644 # number of memory reference insts executed +system.cpu1.iew.exec_branches 46426 # Number of branches executed +system.cpu1.iew.exec_stores 35507 # Number of stores executed +system.cpu1.iew.exec_rate 1.392305 # Inst execution rate +system.cpu1.iew.wb_sent 226182 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 225916 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 128242 # num instructions producing a value +system.cpu1.iew.wb_consumers 134834 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.389175 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.951110 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 13383 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5429 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154086 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.657380 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.063453 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 63982 41.52% 41.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 43006 27.91% 69.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5237 3.40% 72.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6258 4.06% 76.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1532 0.99% 77.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30979 20.11% 97.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 844 0.55% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1302 0.84% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 264603 # Number of instructions committed -system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154086 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 255379 # Number of instructions committed +system.cpu1.commit.committedOps 255379 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 113401 # Number of memory references committed -system.cpu1.commit.loads 76852 # Number of loads committed -system.cpu1.commit.membars 4272 # Number of memory barriers committed -system.cpu1.commit.branches 46786 # Number of branches committed +system.cpu1.commit.refs 108350 # Number of memory references committed +system.cpu1.commit.loads 73633 # Number of loads committed +system.cpu1.commit.membars 4715 # Number of memory barriers committed +system.cpu1.commit.branches 45393 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 182306 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175866 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 36183 14.17% 14.17% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 106131 41.56% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.73% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 78348 30.68% 86.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34717 13.59% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 430627 # The number of ROB reads -system.cpu1.rob.rob_writes 558953 # The number of ROB writes -system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.commit.op_class_0::total 255379 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1302 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 420960 # The number of ROB reads +system.cpu1.rob.rob_writes 540023 # The number of ROB writes +system.cpu1.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6041 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 222757 # Number of Instructions Simulated -system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 407061 # number of integer regfile reads -system.cpu1.int_regfile_writes 190501 # number of integer regfile writes +system.cpu1.committedInsts 214481 # Number of Instructions Simulated +system.cpu1.committedOps 214481 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.758230 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.758230 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.318860 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.318860 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391734 # number of integer regfile reads +system.cpu1.int_regfile_writes 183502 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads +system.cpu1.misc_regfile_reads 112279 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.736588 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40830 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1407.931034 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.736588 # Average occupied blocks per requestor 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of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 34649 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 78832 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 78832 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 78832 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 78832 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011203 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011203 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004531 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004531 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.750000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.750000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008271 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008271 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008271 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008271 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18115.151515 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 18115.151515 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21426.751592 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21426.751592 # average WriteReq miss latency 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access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses 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of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1988000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1748500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 548000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 548000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3736500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3736500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3736500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3736500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003712 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003712 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003059 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.750000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003425 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003425 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003425 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12121.951220 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12121.951220 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16495.283019 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16495.283019 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10745.098039 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10745.098039 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13838.888889 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13838.888889 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.417280 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20534 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 41.399194 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.417280 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164877 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164877 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits -system.cpu1.icache.overall_hits::total 19585 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses -system.cpu1.icache.overall_misses::total 580 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 21613 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21613 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20534 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20534 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20534 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20534 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20534 # number of overall hits +system.cpu1.icache.overall_hits::total 20534 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 583 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 583 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 583 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 583 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 583 # number of overall misses +system.cpu1.icache.overall_misses::total 583 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14299500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14299500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14299500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14299500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14299500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14299500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21117 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21117 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21117 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21117 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21117 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21117 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027608 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.027608 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027608 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.027608 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.027608 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.027608 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24527.444254 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24527.444254 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24527.444254 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24527.444254 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24527.444254 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -1295,408 +1296,407 @@ system.cpu1.icache.fast_writes 0 # nu system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.writebacks::writebacks 383 # number of writebacks system.cpu1.icache.writebacks::total 383 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 87 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 87 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11785500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11785500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11785500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11785500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11785500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11785500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023488 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023488 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023488 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023488 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23761.088710 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23761.088710 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23761.088710 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 46151 # Number of BP lookups -system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits +system.cpu2.branchPred.lookups 51016 # Number of BP lookups +system.cpu2.branchPred.condPredicted 47608 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1273 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43707 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 42688 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage +system.cpu2.branchPred.BTBHitPct 97.668566 # BTB Hit Percentage system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162526 # number of cpu cycles simulated +system.cpu2.numCycles 162253 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 31836 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 280333 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51016 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43591 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 126252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2703 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1153 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 22874 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 441 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.745481 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.165535 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 60810 37.86% 37.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50841 31.66% 69.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7311 4.55% 74.07% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3498 2.18% 76.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 961 0.60% 76.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 31234 19.45% 96.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1226 0.76% 97.06% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 786 0.49% 97.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3938 2.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160605 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.314423 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.727752 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17488 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 62772 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 75260 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3724 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1351 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 265175 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1351 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18185 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 29493 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13900 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 76790 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20876 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 262017 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 183428 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 498093 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 388599 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 169446 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13982 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1189 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1258 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 25354 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 72684 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33991 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34917 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28890 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 216663 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7106 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 219007 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13119 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11098 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 687 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160605 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.363637 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.376138 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 64456 40.13% 40.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23625 14.71% 54.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33318 20.75% 75.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 32915 20.49% 96.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3374 2.10% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 893 0.56% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160605 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 108075 49.35% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77606 35.44% 84.78% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33326 15.22% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued -system.cpu2.iq.rate 1.178390 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 219007 # Type of FU issued +system.cpu2.iq.rate 1.349787 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001566 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 598981 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 236927 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 217448 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 219350 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28643 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2671 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1575 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking +system.cpu2.iew.iewSquashCycles 1351 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8096 # Number of cycles IEW is blocking system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewDispatchedInsts 259522 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 72684 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33991 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1139 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1062 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 217972 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 71586 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1035 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 30772 # number of nop insts executed -system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed -system.cpu2.iew.exec_branches 40210 # Number of branches executed -system.cpu2.iew.exec_stores 26919 # Number of stores executed -system.cpu2.iew.exec_rate 1.172317 # Inst execution rate -system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 104798 # num instructions producing a value -system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value -system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back -system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle +system.cpu2.iew.exec_nop 35753 # number of nop insts executed +system.cpu2.iew.exec_refs 104818 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45124 # Number of branches executed +system.cpu2.iew.exec_stores 33232 # Number of stores executed +system.cpu2.iew.exec_rate 1.343408 # Inst execution rate +system.cpu2.iew.wb_sent 217734 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 217448 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 122408 # num instructions producing a value +system.cpu2.iew.wb_consumers 129014 # num instructions consuming a value +system.cpu2.iew.wb_rate 1.340179 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.948796 # average fanout of values written-back +system.cpu2.commit.commitSquashedInsts 13957 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6419 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1273 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 158015 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.553777 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.025126 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 70555 44.65% 44.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41677 26.38% 71.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5250 3.32% 74.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7214 4.57% 78.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1535 0.97% 79.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28695 18.16% 98.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 838 0.53% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 950 0.60% 99.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1301 0.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 213383 # Number of instructions committed -system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 158015 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 245520 # Number of instructions committed +system.cpu2.commit.committedOps 245520 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 84961 # Number of memory references committed -system.cpu2.commit.loads 58837 # Number of loads committed -system.cpu2.commit.membars 7109 # Number of memory barriers committed -system.cpu2.commit.branches 39190 # Number of branches committed +system.cpu2.commit.refs 102429 # Number of memory references committed +system.cpu2.commit.loads 70013 # Number of loads committed +system.cpu2.commit.membars 5702 # Number of memory barriers committed +system.cpu2.commit.branches 44083 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 146276 # Number of committed integer instructions. +system.cpu2.commit.int_insts 168630 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 34870 14.20% 14.20% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 102519 41.76% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.96% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 75715 30.84% 86.80% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32416 13.20% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 383202 # The number of ROB reads -system.cpu2.rob.rob_writes 455861 # The number of ROB writes -system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.commit.op_class_0::total 245520 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1301 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 415605 # The number of ROB reads +system.cpu2.rob.rob_writes 521544 # The number of ROB writes +system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1648 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 176294 # Number of Instructions Simulated -system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 321409 # number of integer regfile reads -system.cpu2.int_regfile_writes 151400 # number of integer regfile writes +system.cpu2.committedInsts 204948 # Number of Instructions Simulated +system.cpu2.committedOps 204948 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.791679 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.791679 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.263138 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.263138 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 374158 # number of integer regfile reads +system.cpu2.int_regfile_writes 175347 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads +system.cpu2.misc_regfile_reads 106430 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.147052 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38440 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1372.857143 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.147052 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045209 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045209 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits -system.cpu2.dcache.overall_hits::total 63394 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses -system.cpu2.dcache.overall_misses::total 626 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 605000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11659000 # 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-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 301603 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 301603 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42391 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42391 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 32186 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 32186 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 74577 # number of demand (read+write) hits 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misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8601000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 8601000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3593000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3593000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 655000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 655000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12194000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12194000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12194000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12194000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 42920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 42920 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32345 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 75265 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 75265 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 75265 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 75265 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012325 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.012325 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004916 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004916 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009141 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.009141 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009141 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.009141 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16258.979206 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16258.979206 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22597.484277 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22597.484277 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11293.103448 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 11293.103448 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17723.837209 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17723.837209 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17723.837209 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1705,106 +1705,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 359 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 359 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 53 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 412 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 412 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 412 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 276 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 276 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1653000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1653000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1845000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 597000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 597000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3498000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3498000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3498000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3498000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003961 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003961 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003277 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003277 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003667 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003667 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003667 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9723.529412 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9723.529412 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17405.660377 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17405.660377 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10293.103448 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10293.103448 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12673.913043 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12673.913043 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 77.661611 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 22304 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 44.608000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.661611 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151683 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.151683 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits -system.cpu2.icache.overall_hits::total 25515 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses -system.cpu2.icache.overall_misses::total 573 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency +system.cpu2.icache.tags.tag_accesses 23374 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 23374 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 22304 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 22304 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 22304 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 22304 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 22304 # number of overall hits +system.cpu2.icache.overall_hits::total 22304 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses +system.cpu2.icache.overall_misses::total 570 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8095000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8095000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8095000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8095000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8095000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8095000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22874 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22874 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22874 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 22874 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 22874 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 22874 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024919 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024919 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024919 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024919 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024919 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024919 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14201.754386 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14201.754386 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14201.754386 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14201.754386 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14201.754386 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1815,407 +1815,407 @@ system.cpu2.icache.fast_writes 0 # nu system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.writebacks::writebacks 386 # number of writebacks system.cpu2.icache.writebacks::total 386 # number of writebacks -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 70 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 70 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 70 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7049500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7049500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7049500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7049500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7049500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7049500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021859 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021859 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021859 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021859 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14099 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14099 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14099 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 14099 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 52678 # Number of BP lookups -system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits +system.cpu3.branchPred.lookups 49230 # Number of BP lookups +system.cpu3.branchPred.condPredicted 45728 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1271 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 41796 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 40803 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage +system.cpu3.branchPred.BTBHitPct 97.624175 # BTB Hit Percentage system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 162161 # number of cpu cycles simulated +system.cpu3.numCycles 161890 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32992 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 268412 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49230 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 41709 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 124419 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2697 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched +system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24017 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 159937 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.678236 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.146445 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 63357 39.61% 39.61% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 49486 30.94% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7847 4.91% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3455 2.16% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 942 0.59% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 28830 18.03% 96.24% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1207 0.75% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 797 0.50% 97.49% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 4016 2.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 159937 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.304095 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.657990 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17620 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 66098 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 70935 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3926 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1348 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 252986 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1348 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18323 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 31370 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 72885 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22031 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 249675 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 20026 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 174506 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 471658 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 368736 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 160859 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13647 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1202 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1275 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 26657 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 68456 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 31644 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33001 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 26549 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 205848 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7559 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 208921 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 4 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12739 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10220 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 712 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159937 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.306271 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.372225 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 67005 41.89% 41.89% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24940 15.59% 57.49% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31075 19.43% 76.92% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30637 19.16% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3376 2.11% 98.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1620 1.01% 99.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 871 0.54% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 214 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159937 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.70% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.70% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 41 12.35% 37.05% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 62.95% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 103999 49.78% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 73864 35.35% 85.13% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31058 14.87% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued -system.cpu3.iq.rate 1.405159 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 208921 # Type of FU issued +system.cpu3.iq.rate 1.290512 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 332 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001589 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 578115 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 226182 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 207437 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 209253 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 26373 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1480 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions +system.cpu3.iew.iewSquashCycles 1348 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8395 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 247262 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 160 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 68456 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 31644 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 438 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1065 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 207928 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 67431 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 993 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 37293 # number of nop insts executed -system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed -system.cpu3.iew.exec_branches 46686 # Number of branches executed -system.cpu3.iew.exec_stores 35323 # Number of stores executed -system.cpu3.iew.exec_rate 1.398844 # Inst execution rate -system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 128132 # num instructions producing a value -system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value -system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 33855 # number of nop insts executed +system.cpu3.iew.exec_refs 98404 # number of memory reference insts executed +system.cpu3.iew.exec_branches 43312 # Number of branches executed +system.cpu3.iew.exec_stores 30973 # Number of stores executed +system.cpu3.iew.exec_rate 1.284378 # Inst execution rate +system.cpu3.iew.wb_sent 207701 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 207437 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 116002 # num instructions producing a value +system.cpu3.iew.wb_consumers 122598 # num instructions consuming a value +system.cpu3.iew.wb_rate 1.281345 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.946198 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 13505 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6847 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1271 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157409 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.484744 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.997930 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 73609 46.76% 46.76% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 39844 25.31% 72.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5242 3.33% 75.41% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7652 4.86% 80.27% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1542 0.98% 81.25% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 26417 16.78% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 849 0.54% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 951 0.60% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1303 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 255867 # Number of instructions committed -system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157409 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 233712 # Number of instructions committed +system.cpu3.commit.committedOps 233712 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 108145 # Number of memory references committed -system.cpu3.commit.loads 73642 # Number of loads committed -system.cpu3.commit.membars 5159 # Number of memory barriers committed -system.cpu3.commit.branches 45627 # Number of branches committed +system.cpu3.commit.refs 96099 # Number of memory references committed +system.cpu3.commit.loads 65935 # Number of loads committed +system.cpu3.commit.membars 6131 # Number of memory barriers committed +system.cpu3.commit.branches 42256 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 175889 # Number of committed integer instructions. +system.cpu3.commit.int_insts 160475 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.72% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 78801 30.80% 86.52% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 34503 13.48% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33044 14.14% 14.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 98438 42.12% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.26% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 72066 30.84% 87.09% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30164 12.91% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 425596 # The number of ROB reads -system.cpu3.rob.rob_writes 542328 # The number of ROB writes -system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.commit.op_class_0::total 233712 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1303 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 402737 # The number of ROB reads +system.cpu3.rob.rob_writes 496962 # The number of ROB writes +system.cpu3.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1953 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 214294 # Number of Instructions Simulated -system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 391365 # number of integer regfile reads -system.cpu3.int_regfile_writes 183208 # number of integer regfile writes +system.cpu3.committedInsts 194537 # Number of Instructions Simulated +system.cpu3.committedOps 194537 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.832181 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.832181 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.201662 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.201662 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 355006 # number of integer regfile reads +system.cpu3.int_regfile_writes 166699 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads +system.cpu3.misc_regfile_reads 100037 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.251319 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 36167 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1291.678571 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.251319 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047366 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047366 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits -system.cpu3.dcache.overall_hits::total 78210 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses -system.cpu3.dcache.overall_misses::total 673 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3790500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3790500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 680500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 680500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 13139500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 13139500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 13139500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 13139500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 44451 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 44451 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 34432 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 285043 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 285043 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40546 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40546 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 29945 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 29945 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 17 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 17 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 70491 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 70491 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 70491 # number of overall hits +system.cpu3.dcache.overall_hits::total 70491 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 489 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 489 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 53 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 53 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 638 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 638 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 638 # number of overall misses +system.cpu3.dcache.overall_misses::total 638 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8138500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8138500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3781500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3781500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 606500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 606500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11920000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11920000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11920000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11920000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41035 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41035 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30094 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 71129 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 71129 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 71129 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 71129 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011917 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.011917 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004951 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004951 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.757143 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.757143 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008970 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008970 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008970 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008970 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16643.149284 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16643.149284 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25379.194631 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 25379.194631 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11443.396226 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11443.396226 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18683.385580 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18683.385580 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18683.385580 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2224,106 +2224,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 328 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 328 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits 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accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003712 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003712 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003712 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9993.788820 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9993.788820 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 20771.844660 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 20771.844660 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10443.396226 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10443.396226 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14198.863636 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14198.863636 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 80.879647 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23443 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 47.074297 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 80.879647 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.157968 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.157968 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits -system.cpu3.icache.overall_hits::total 21310 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 572 # 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average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 24515 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24515 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23443 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23443 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23443 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23443 # number of demand (read+write) hits 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accesses +system.cpu3.icache.demand_miss_rate::total 0.023900 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023900 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023900 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13445.121951 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13445.121951 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13445.121951 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13445.121951 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13445.121951 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number 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76 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 76 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 76 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 76 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss 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0.718294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.006073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.075910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 61.760427 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.322052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2.559109 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.677187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1.231634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.717957 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average 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accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 22 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) @@ -2555,9 +2555,9 @@ system.l2c.ReadExReq_miss_rate::cpu2.data 1 # m system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.169355 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018072 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.173387 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.022000 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses @@ -2566,55 +2566,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.173387 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.022000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.018072 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses 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latency +system.l2c.overall_avg_miss_latency::cpu2.data 99423.076923 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 68300 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 115461.538462 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78416.053019 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2625,23 +2625,23 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 6 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 2 # 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-system.l2c.overall_mshr_miss_latency::cpu2.inst 219000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1163000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 495500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 1365500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 45719000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 436500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 1162500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 145500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 1371000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 45737000 # number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses @@ -2725,9 +2725,9 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses @@ -2736,129 +2736,128 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21850 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18981.481481 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18921.052632 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19119.047619 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18909.090909 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18983.146067 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71090.425532 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90875 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90833.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 107041.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76229.007634 # average ReadExReq mshr miss latency system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66276.053215 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70497.041420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66091.463415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89423.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105461.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68674.174174 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 290 # Transaction distribution -system.membus.trans_dist::UpgradeResp 89 # Transaction distribution -system.membus.trans_dist::ReadExReq 162 # Transaction distribution +system.membus.trans_dist::UpgradeReq 291 # Transaction distribution +system.membus.trans_dist::ReadExReq 159 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1650 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 232 # Total snoops (count) -system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.snoops 230 # Total snoops (count) +system.membus.snoop_fanout::samples 985 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 985 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 987 # Request fanout histogram -system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 985 # Request fanout histogram +system.membus.reqLayer0.occupancy 928501 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.respLayer1.occupancy 3534750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 4931 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1335 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2366 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2779 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1468 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 294 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 294 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 387 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 387 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadSharedReq 678 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1386 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 379 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1380 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7371 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 59008 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 56256 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 56704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 56448 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1022 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram +system.toL2Bus.pkt_size::total 244288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1020 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3461 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.293268 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.185819 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1230 35.54% 35.54% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 830 23.98% 59.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 557 16.09% 75.61% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 844 24.39% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2867,24 +2866,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3461 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3950967 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 746494 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 429965 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752493 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 440466 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 422962 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 903a3bff1..1d3cbd064 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 140858 # Simulator instruction rate (inst/s) -host_op_rate 140857 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18239325 # Simulator tick rate (ticks/s) -host_mem_usage 243264 # Number of bytes of host memory used -host_seconds 4.81 # Real time elapsed on the host +host_inst_rate 1830828 # Simulator instruction rate (inst/s) +host_op_rate 1830758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 237054275 # Simulator tick rate (ticks/s) +host_mem_usage 306784 # Number of bytes of host memory used +host_seconds 0.37 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -750,14 +750,14 @@ system.cpu3.icache.writebacks::writebacks 279 # n system.cpu3.icache.writebacks::total 279 # number of writebacks system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use +system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks. +system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 55.207589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor @@ -766,18 +766,18 @@ system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Av system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id +system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19424 # Number of tag accesses system.l2c.tags.data_accesses 19424 # Number of data accesses system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits @@ -944,24 +944,24 @@ system.l2c.no_allocate_misses 0 # Nu system.membus.trans_dist::ReadResp 423 # Transaction distribution system.membus.trans_dist::UpgradeReq 273 # Transaction distribution system.membus.trans_dist::UpgradeResp 80 # Transaction distribution -system.membus.trans_dist::ReadExReq 412 # Transaction distribution +system.membus.trans_dist::ReadExReq 183 # Transaction distribution system.membus.trans_dist::ReadExResp 136 # Transaction distribution system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1747 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1747 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 1108 # Request fanout histogram +system.membus.snoop_fanout::samples 879 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1108 # Request fanout histogram +system.membus.snoop_fanout::total 879 # Request fanout histogram system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -970,7 +970,7 @@ system.toL2Bus.snoop_filter.hit_single_snoops 0 system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1050 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution @@ -978,24 +978,24 @@ system.toL2Bus.trans_dist::ReadExReq 412 # Tr system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 40704 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 233088 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 813d17b05..eb0bc0573 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,91 +1,91 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000265 # Number of seconds simulated -sim_ticks 264840500 # Number of ticks simulated -final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000264 # Number of seconds simulated +sim_ticks 263565500 # Number of ticks simulated +final_tick 263565500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127010 # Simulator instruction rate (inst/s) -host_op_rate 127009 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50783237 # Simulator tick rate (ticks/s) -host_mem_usage 243272 # Number of bytes of host memory used -host_seconds 5.22 # Real time elapsed on the host -sim_insts 662366 # Number of instructions simulated -sim_ops 662366 # Number of ops (including micro ops) simulated +host_inst_rate 798172 # Simulator instruction rate (inst/s) +host_op_rate 798158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 317271660 # Simulator tick rate (ticks/s) +host_mem_usage 306776 # Number of bytes of host memory used +host_seconds 0.83 # Real time elapsed on the host +sim_insts 663039 # Number of instructions simulated +sim_ops 663039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69204809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40065942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 2428239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3642358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 13112490 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5342126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1214119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3885182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138895265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69204809 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 2428239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 13112490 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1214119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85959657 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69204809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40065942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 2428239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3642358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 13112490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5342126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1214119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3885182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138895265 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 529681 # number of cpu cycles simulated +system.cpu0.numCycles 527131 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158238 # Number of instructions committed -system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses +system.cpu0.committedInsts 158196 # Number of instructions committed +system.cpu0.committedOps 158196 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108956 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108984 # number of integer instructions +system.cpu0.num_conditional_control_insts 25969 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108956 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315026 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110562 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73853 # number of memory refs -system.cpu0.num_load_insts 48895 # Number of load instructions -system.cpu0.num_store_insts 24958 # Number of store instructions +system.cpu0.num_mem_refs 73832 # number of memory refs +system.cpu0.num_load_insts 48881 # Number of load instructions +system.cpu0.num_store_insts 24951 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 527130.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26841 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction +system.cpu0.Branches 26834 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23561 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60781 38.41% 53.29% # Class of executed instruction system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction @@ -114,36 +114,36 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 48965 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24951 15.77% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158300 # Class of executed instruction +system.cpu0.op_class::total 158258 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.050771 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73302 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 438.934132 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.050771 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283302 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283302 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 295559 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295559 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48703 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48703 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24717 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24717 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits -system.cpu0.dcache.overall_hits::total 73441 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73420 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73420 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73420 # number of overall hits +system.cpu0.dcache.overall_hits::total 73420 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -154,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 351 # system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses system.cpu0.dcache.overall_misses::total 351 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4817500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4817500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6985500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6985500 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 11803000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11803000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11803000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11803000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48871 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48871 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24900 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24900 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73771 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73771 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73771 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003438 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003438 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007349 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007349 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004758 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004758 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004758 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004758 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28675.595238 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28675.595238 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38172.131148 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38172.131148 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33626.780627 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33626.780627 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33626.780627 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,88 +214,88 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4649500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6802500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6802500 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11452000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11452000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11452000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003438 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007349 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004758 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004758 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004758 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27675.595238 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27675.595238 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37172.131148 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37172.131148 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32626.780627 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32626.780627 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 211.380247 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157792 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.884368 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.380247 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.412852 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.412852 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits -system.cpu0.icache.overall_hits::total 157834 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158726 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158726 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157792 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157792 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157792 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157792 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157792 # number of overall hits +system.cpu0.icache.overall_hits::total 157792 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20140500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20140500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20140500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20140500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20140500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20140500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158259 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158259 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158259 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158259 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158259 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158259 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002951 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002951 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002951 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002951 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002951 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002951 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43127.408994 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43127.408994 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43127.408994 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43127.408994 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43127.408994 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -312,158 +312,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19673500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19673500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19673500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19673500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002951 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002951 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002951 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002951 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42127.408994 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42127.408994 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42127.408994 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 529680 # number of cpu cycles simulated +system.cpu1.numCycles 527130 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168829 # Number of instructions committed -system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses +system.cpu1.committedInsts 170790 # Number of instructions committed +system.cpu1.committedOps 170790 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110708 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111193 # number of integer instructions +system.cpu1.num_conditional_control_insts 34050 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110708 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written +system.cpu1.num_int_register_reads 268858 # number of times the integer registers were read +system.cpu1.num_int_register_writes 101318 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54535 # number of memory refs -system.cpu1.num_load_insts 41264 # Number of load instructions -system.cpu1.num_store_insts 13271 # Number of store instructions -system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles -system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles -system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles -system.cpu1.Branches 34479 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction -system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction -system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction -system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 52827 # number of memory refs +system.cpu1.num_load_insts 41019 # Number of load instructions +system.cpu1.num_store_insts 11808 # Number of store instructions +system.cpu1.num_idle_cycles 73818.861681 # Number of idle cycles +system.cpu1.num_busy_cycles 453311.138319 # Number of busy cycles +system.cpu1.not_idle_fraction 0.859961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.140039 # Percentage of idle cycles +system.cpu1.Branches 35703 # Number of branches fetched +system.cpu1.op_class::No_OpClass 26483 15.50% 15.50% # Class of executed instruction +system.cpu1.op_class::IntAlu 74610 43.68% 59.18% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.18% # Class of executed instruction +system.cpu1.op_class::MemRead 57921 33.91% 93.09% # Class of executed instruction +system.cpu1.op_class::MemWrite 11808 6.91% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 168861 # Class of executed instruction +system.cpu1.op_class::total 170822 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.474097 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 25884 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 892.551724 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.474097 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051707 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051707 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits -system.cpu1.dcache.overall_hits::total 54188 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses -system.cpu1.dcache.overall_misses::total 270 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2920000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2920000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2149500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2149500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 245500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 245500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5069500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5069500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5069500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5069500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41257 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41257 # number of ReadReq accesses(hits+misses) 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WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 211529 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 211529 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40844 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40844 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 11631 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 11631 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 52475 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 52475 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 52475 # number of overall hits +system.cpu1.dcache.overall_hits::total 52475 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 167 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 272 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 272 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 272 # number of overall misses +system.cpu1.dcache.overall_misses::total 272 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1891500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1891500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1642500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1642500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 250000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 250000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3534000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3534000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3534000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3534000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 41011 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 41011 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 11736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 11736 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 52747 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 52747 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 52747 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 52747 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004072 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004072 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008947 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008947 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005157 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005157 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005157 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005157 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11326.347305 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11326.347305 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 15642.857143 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 15642.857143 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4464.285714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 12992.647059 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12992.647059 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12992.647059 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,99 +472,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 272 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1537500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1537500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 194000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3262000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3262000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3262000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3262000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004072 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004072 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008947 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008947 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005157 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005157 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005157 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10326.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10326.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14642.857143 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14642.857143 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3464.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11992.647059 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11992.647059 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 66.953040 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 170457 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 465.729508 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 66.953040 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130768 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130768 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits -system.cpu1.icache.overall_hits::total 168496 # number of overall hits +system.cpu1.icache.tags.tag_accesses 171189 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 171189 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 170457 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 170457 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 170457 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 170457 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 170457 # number of overall hits +system.cpu1.icache.overall_hits::total 170457 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5688500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5688500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5688500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5688500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5688500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5688500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 170823 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 170823 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 170823 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 170823 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 170823 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 170823 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002143 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002143 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002143 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002143 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002143 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002143 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15542.349727 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15542.349727 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15542.349727 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15542.349727 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15542.349727 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -581,158 +581,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5322500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5322500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5322500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5322500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5322500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5322500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002143 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002143 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14542.349727 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14542.349727 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14542.349727 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 529681 # number of cpu cycles simulated +system.cpu2.numCycles 527130 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165415 # Number of instructions committed -system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses +system.cpu2.committedInsts 168244 # Number of instructions committed +system.cpu2.committedOps 168244 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 109603 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110386 # number of integer instructions +system.cpu2.num_conditional_control_insts 33329 # number of instructions that are conditional controls +system.cpu2.num_int_insts 109603 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written +system.cpu2.num_int_register_reads 267321 # number of times the integer registers were read +system.cpu2.num_int_register_writes 101101 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 55033 # number of memory refs -system.cpu2.num_load_insts 40858 # Number of load instructions -system.cpu2.num_store_insts 14175 # Number of store instructions -system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles -system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles -system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles -system.cpu2.Branches 33177 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction -system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction -system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction -system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 52443 # number of memory refs +system.cpu2.num_load_insts 40463 # Number of load instructions +system.cpu2.num_store_insts 11980 # Number of store instructions +system.cpu2.num_idle_cycles 74087.861169 # Number of idle cycles +system.cpu2.num_busy_cycles 453042.138831 # Number of busy cycles +system.cpu2.not_idle_fraction 0.859450 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.140550 # Percentage of idle cycles +system.cpu2.Branches 34984 # Number of branches fetched +system.cpu2.op_class::No_OpClass 25761 15.31% 15.31% # Class of executed instruction +system.cpu2.op_class::IntAlu 74059 44.01% 59.32% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.32% # Class of executed instruction +system.cpu2.op_class::MemRead 56476 33.56% 92.88% # Class of executed instruction +system.cpu2.op_class::MemWrite 11980 7.12% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165447 # Class of executed instruction +system.cpu2.op_class::total 168276 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.444081 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 26343 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 878.100000 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.444081 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053602 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053602 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits -system.cpu2.dcache.overall_hits::total 54681 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 209996 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 209996 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40285 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40285 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 11801 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 11801 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 52086 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 52086 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 52086 # number of overall hits +system.cpu2.dcache.overall_hits::total 52086 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 170 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 104 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 104 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses -system.cpu2.dcache.overall_misses::total 271 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of 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number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency +system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses +system.cpu2.dcache.overall_misses::total 274 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2220000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2220000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1703000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1703000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 260000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 3923000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 3923000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 3923000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 3923000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40455 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40455 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 11905 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 11905 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 52360 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 52360 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 52360 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 52360 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004202 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.004202 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.008736 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.008736 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.005233 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.005233 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.005233 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.005233 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13058.823529 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13058.823529 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 16375 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 16375 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4482.758621 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4482.758621 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14317.518248 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14317.518248 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14317.518248 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -741,99 +741,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 170 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 170 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.demand_mshr_misses::cpu2.data 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 274 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2050000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2050000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1599000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1599000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3649000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3649000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3649000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3649000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004202 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004202 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.008736 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.008736 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.005233 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.005233 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.005233 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12058.823529 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12058.823529 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15375 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15375 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3482.758621 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3482.758621 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13317.518248 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13317.518248 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 69.363893 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 167911 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 458.773224 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.363893 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135476 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135476 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu2.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits -system.cpu2.icache.overall_hits::total 165082 # number of overall hits +system.cpu2.icache.tags.tag_accesses 168643 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 168643 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 167911 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 167911 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 167911 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 167911 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 167911 # number of overall hits +system.cpu2.icache.overall_hits::total 167911 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8088500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8088500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8088500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8088500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8088500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8088500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 168277 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 168277 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 168277 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 168277 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 168277 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 168277 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002175 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002175 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002175 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22099.726776 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22099.726776 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22099.726776 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22099.726776 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22099.726776 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -850,158 +850,158 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7722500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7722500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7722500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7722500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002175 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21099.726776 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21099.726776 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21099.726776 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 529680 # number of cpu cycles simulated +system.cpu3.numCycles 527131 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 169884 # Number of instructions committed -system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses +system.cpu3.committedInsts 165809 # Number of instructions committed +system.cpu3.committedOps 165809 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112442 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110793 # number of integer instructions +system.cpu3.num_conditional_control_insts 30690 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112442 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written +system.cpu3.num_int_register_reads 289238 # number of times the integer registers were read +system.cpu3.num_int_register_writes 110642 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53409 # number of memory refs -system.cpu3.num_load_insts 41060 # Number of load instructions -system.cpu3.num_store_insts 12349 # Number of store instructions -system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles -system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles -system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles -system.cpu3.Branches 35208 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction -system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction -system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction -system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 57921 # number of memory refs +system.cpu3.num_load_insts 41890 # Number of load instructions +system.cpu3.num_store_insts 16031 # Number of store instructions +system.cpu3.num_idle_cycles 74358.001718 # Number of idle cycles +system.cpu3.num_busy_cycles 452772.998282 # Number of busy cycles +system.cpu3.not_idle_fraction 0.858938 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.141062 # Percentage of idle cycles +system.cpu3.Branches 32344 # Number of branches fetched +system.cpu3.op_class::No_OpClass 23127 13.95% 13.95% # Class of executed instruction +system.cpu3.op_class::IntAlu 75479 45.51% 59.46% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.46% # Class of executed instruction +system.cpu3.op_class::MemRead 51204 30.88% 90.33% # Class of executed instruction +system.cpu3.op_class::MemWrite 16031 9.67% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 169916 # Class of executed instruction +system.cpu3.op_class::total 165841 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.704074 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 34341 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1184.172414 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.704074 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050203 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050203 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits -system.cpu3.dcache.overall_hits::total 53061 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses -system.cpu3.dcache.overall_misses::total 268 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency +system.cpu3.dcache.tags.tag_accesses 231895 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 231895 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41733 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41733 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 15853 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 15853 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 57586 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 57586 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 57586 # number of overall hits +system.cpu3.dcache.overall_hits::total 57586 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 150 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 150 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 109 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 109 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 56 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses +system.cpu3.dcache.overall_misses::total 259 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1542500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 1542500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1810500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1810500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 250500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 250500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 3353000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 3353000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 3353000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 3353000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41883 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41883 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 15962 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 15962 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 57845 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57845 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57845 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57845 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003581 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003581 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006829 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.006829 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835821 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004477 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004477 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004477 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004477 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 10283.333333 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 10283.333333 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16610.091743 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16610.091743 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4473.214286 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4473.214286 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 12945.945946 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 12945.945946 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 12945.945946 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1010,69 +1010,69 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 150 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 150 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 109 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 259 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 259 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1392500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1392500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1701500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1701500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 194500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 194500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3094000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3094000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3094000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3094000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003581 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006829 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006829 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004477 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004477 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004477 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9283.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9283.333333 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15610.091743 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15610.091743 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3473.214286 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3473.214286 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11945.945946 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11945.945946 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 64.942208 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 165475 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 450.885559 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.942208 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126840 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126840 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits -system.cpu3.icache.overall_hits::total 169550 # number of overall hits +system.cpu3.icache.tags.tag_accesses 166209 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 166209 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 165475 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165475 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165475 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165475 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165475 # number of overall hits +system.cpu3.icache.overall_hits::total 165475 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses @@ -1085,18 +1085,18 @@ system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses +system.cpu3.icache.ReadReq_accesses::cpu3.inst 165842 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 165842 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 165842 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 165842 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 165842 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 165842 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002213 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002213 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002213 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002213 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002213 # miss rate for overall accesses system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency @@ -1125,12 +1125,12 @@ system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002213 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002213 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002213 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002213 # mshr miss rate for overall accesses system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency @@ -1139,30 +1139,30 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses 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-system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.881447 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 230.714883 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.006864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.227742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.835119 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 46.668024 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.066881 # Average occupied blocks per requestor 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system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005298 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id @@ -1204,9 +1204,9 @@ system.l2c.overall_hits::cpu3.inst 357 # nu system.l2c.overall_hits::cpu3.data 9 # number of overall hits system.l2c.overall_hits::total 1218 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses @@ -1242,46 +1242,46 @@ system.l2c.overall_misses::cpu3.inst 10 # nu system.l2c.overall_misses::cpu3.data 16 # number of overall misses system.l2c.overall_misses::total 594 # number of overall misses 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miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 118000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 118000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2.data 475500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3.data 119000 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::total 4640000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 16964000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 16965000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 9819500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 821500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 960500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 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-system.l2c.overall_miss_latency::cpu0.inst 16964000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 16965000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 9819500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 821500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 960500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 3820000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1372000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 553500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 958000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 831500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 955500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3806500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1380500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 555500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 955000 # number of overall miss cycles system.l2c.overall_miss_latency::total 35269000 # number of overall miss cycles system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 14 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) @@ -1355,37 +1355,37 @@ system.l2c.overall_miss_rate::cpu3.inst 0.027248 # mi system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.327815 # miss rate for overall accesses system.l2c.ReadExReq_avg_miss_latency::cpu0.data 59515.151515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 60142.857143 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 59733.333333 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 60000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 59647.887324 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59522.807018 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 58678.571429 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58769.230769 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55350 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 59248.663102 # average ReadCleanReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 59821.428571 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 60333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 59714.285714 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 59651.408451 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 59526.315789 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 59392.857143 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 58561.538462 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 55550 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 59247.326203 # average ReadCleanReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 59507.575758 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59250 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 59000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 59437.500000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 59500 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::total 59487.179487 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 59522.807018 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 59526.315789 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 58678.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 60031.250000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 58769.230769 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 59652.173913 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 55350 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 59875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 59392.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 59718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 58561.538462 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 60021.739130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 55550 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::total 59375.420875 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 59522.807018 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 59526.315789 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 59512.121212 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 58678.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 60031.250000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 58769.230769 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 59652.173913 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 55350 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 59875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 59392.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 59718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 58561.538462 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 60021.739130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 55550 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 59687.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::total 59375.420875 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1395,29 +1395,29 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 7 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 7 # number of ReadCleanReq MSHR hits -system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 6 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 4 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 11 # number of ReadCleanReq MSHR hits +system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 20 # number of ReadCleanReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::cpu1.data 1 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu2.data 1 # number of ReadSharedReq MSHR hits system.l2c.ReadSharedReq_mshr_hits::total 2 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits 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+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49539.548023 # average ReadCleanReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49526.315789 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 49800 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49518.518519 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50068.181818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49687.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49562.937063 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution -system.membus.trans_dist::UpgradeResp 76 # Transaction distribution system.membus.trans_dist::ReadExReq 208 # Transaction distribution system.membus.trans_dist::ReadExResp 142 # Transaction distribution system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1481 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1481 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) @@ -1588,53 +1587,53 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 685132 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 3976 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1120 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1854 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 424 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 424 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5866 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41344 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41472 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1032 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram +system.toL2Bus.pkt_size::total 183616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1028 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2918 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.265250 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.153418 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1002 34.34% 34.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 794 27.21% 61.55% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 468 16.04% 77.59% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 654 22.41% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -1643,24 +1642,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2918 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3048992 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 500989 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 435970 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 554485 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 441968 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 552992 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 411482 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt index 1566487a2..7c2d41959 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.010022 # Nu sim_ticks 10021833 # Number of ticks simulated final_tick 10021833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 66575 # Simulator tick rate (ticks/s) -host_mem_usage 401248 # Number of bytes of host memory used -host_seconds 150.54 # Real time elapsed on the host +host_tick_rate 141404 # Simulator tick rate (ticks/s) +host_mem_usage 425972 # Number of bytes of host memory used +host_seconds 70.87 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39622272 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 760ab889a..02b6c9c1b 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.004723 # Nu sim_ticks 4722948 # Number of ticks simulated final_tick 4722948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 22839 # Simulator tick rate (ticks/s) -host_mem_usage 403984 # Number of bytes of host memory used -host_seconds 206.79 # Real time elapsed on the host +host_tick_rate 43612 # Simulator tick rate (ticks/s) +host_mem_usage 429416 # Number of bytes of host memory used +host_seconds 108.30 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 38973248 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index edf017693..ac17b1f35 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.007679 # Nu sim_ticks 7678882 # Number of ticks simulated final_tick 7678882 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 60394 # Simulator tick rate (ticks/s) -host_mem_usage 401808 # Number of bytes of host memory used -host_seconds 127.15 # Real time elapsed on the host +host_tick_rate 131227 # Simulator tick rate (ticks/s) +host_mem_usage 425824 # Number of bytes of host memory used +host_seconds 58.52 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 39687936 # Number of bytes read from this memory diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index 6281c21fd..64e77dffe 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1819 +1,1816 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000541 # Number of seconds simulated -sim_ticks 540820000 # Number of ticks simulated -final_tick 540820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000535 # Number of seconds simulated +sim_ticks 535115500 # Number of ticks simulated +final_tick 535115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 46544616 # Simulator tick rate (ticks/s) -host_mem_usage 216108 # Number of bytes of host memory used -host_seconds 11.62 # Real time elapsed on the host +host_tick_rate 114251239 # Simulator tick rate (ticks/s) +host_mem_usage 237088 # Number of bytes of host memory used +host_seconds 4.68 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 88157 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 82701 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 84142 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 82645 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 83993 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 79749 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78765 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 84222 # Number of bytes read from this memory -system.physmem.bytes_read::total 664374 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 426368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5567 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5462 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5416 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5447 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5329 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5472 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5421 # Number of bytes written to this memory -system.physmem.bytes_written::total 470013 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11108 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10881 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11102 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10890 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10914 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11079 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87861 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6662 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5567 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5462 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5447 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5329 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5472 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5421 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50307 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 163006176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 152917792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 155582264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 152814245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 155306756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 147459413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 145639954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 155730187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1228456788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 788373211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10293628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10099479 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10014423 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10071743 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 9853556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10117969 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10227063 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10023668 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 869074738 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 788373211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 173299804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 163017270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 165596687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 162885988 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165160312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 157577382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 155867017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 165753855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2097531526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 81574 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80110 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79121 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 81238 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80899 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 79820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79202 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 79066 # Number of bytes read from this memory +system.physmem.bytes_read::total 641030 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 406208 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5473 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5509 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5540 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5404 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5375 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5435 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5475 # Number of bytes written to this memory +system.physmem.bytes_written::total 449807 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10829 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10961 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11026 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87827 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6347 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5473 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5509 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5540 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5388 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5375 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5435 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5475 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49946 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 152441856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 149705998 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 147857799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 151813954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 151180446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 149164059 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 148009168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 147755017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1197928298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 759103409 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10227699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10294974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10352905 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10068854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10098754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10044560 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10156686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10231436 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 840579277 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 759103409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 162669555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 160000972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 158210704 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 161882808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 161279200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 159208619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 158165854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 157986453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2038507575 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99596 # number of read accesses completed -system.cpu0.num_writes 55268 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22066 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.486377 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13717 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22459 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.610757 # Average number of references to valid blocks. +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 55271 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22387 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.751313 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13331 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22793 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.584873 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.486377 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.764622 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.764622 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338295 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338295 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8878 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8878 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1162 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1162 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 10040 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 10040 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 10040 # number of overall hits -system.cpu0.l1c.overall_hits::total 10040 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36478 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36478 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23899 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23899 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60377 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60377 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60377 # number of overall misses -system.cpu0.l1c.overall_misses::total 60377 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 603408975 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 603408975 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 722750184 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 722750184 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1326159159 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1326159159 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1326159159 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1326159159 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45356 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25061 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70417 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70417 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70417 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70417 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.804260 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.804260 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953633 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953633 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.857421 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.857421 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.857421 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.857421 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16541.723093 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16541.723093 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 30241.858823 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 30241.858823 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21964.641486 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21964.641486 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21964.641486 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21964.641486 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 828428 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 391.751313 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765139 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765139 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338274 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338274 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8660 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1174 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1174 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9834 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9834 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9834 # number of overall hits +system.cpu0.l1c.overall_hits::total 9834 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36517 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36517 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23979 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23979 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60496 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60496 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60496 # number of overall misses +system.cpu0.l1c.overall_misses::total 60496 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 647463503 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 647463503 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 554640697 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 554640697 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1202104200 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1202104200 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1202104200 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1202104200 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45177 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45177 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25153 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25153 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70330 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70330 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808310 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808310 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953326 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953326 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860173 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860173 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860173 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860173 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17730.468083 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 17730.468083 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23130.268026 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 23130.268026 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 19870.804681 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 19870.804681 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 19870.804681 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 19870.804681 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 749854 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 62795 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 59820 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.192579 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.535172 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9669 # number of writebacks -system.cpu0.l1c.writebacks::total 9669 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36478 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23899 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60377 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60377 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60377 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60377 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9885 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5567 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5567 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15452 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15452 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 566933975 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 566933975 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 698852184 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 698852184 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1265786159 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1265786159 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1265786159 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1265786159 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 722511018 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 722511018 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 853790554 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 853790554 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1576301572 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1576301572 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.804260 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.804260 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953633 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953633 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.857421 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857421 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.857421 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15541.805335 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15541.805335 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 29241.900665 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 29241.900665 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20964.707736 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 73091.655842 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73091.655842 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153366.365008 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153366.365008 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102012.786177 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102012.786177 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9840 # number of writebacks +system.cpu0.l1c.writebacks::total 9840 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36517 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36517 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23979 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23979 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60496 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60496 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60496 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60496 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9959 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9959 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5475 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5475 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15434 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15434 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 610946503 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 610946503 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 530662697 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 530662697 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1141609200 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1141609200 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1141609200 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1141609200 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 751203683 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 751203683 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 933372844 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 933372844 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1684576527 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1684576527 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808310 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808310 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953326 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953326 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860173 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860173 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860173 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16730.468083 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16730.468083 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22130.309729 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22130.309729 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18870.821211 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75429.629782 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75429.629782 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 170479.058265 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170479.058265 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109147.112025 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109147.112025 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98929 # number of read accesses completed -system.cpu1.num_writes 55238 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22532 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.132482 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13440 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.586106 # Average number of references to valid blocks. +system.cpu1.num_reads 99085 # number of read accesses completed +system.cpu1.num_writes 54836 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22258 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.296117 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22654 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.590536 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.132482 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765884 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765884 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338385 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338385 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8754 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8754 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1152 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1152 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9906 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9906 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9906 # number of overall hits -system.cpu1.l1c.overall_hits::total 9906 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36277 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36277 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 24198 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 24198 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60475 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60475 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60475 # number of overall misses -system.cpu1.l1c.overall_misses::total 60475 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 602891984 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 602891984 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 733995398 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 733995398 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1336887382 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1336887382 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1336887382 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1336887382 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45031 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45031 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25350 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25350 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70381 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70381 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70381 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70381 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805601 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805601 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954556 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859252 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859252 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859252 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859252 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16619.124624 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16619.124624 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 30332.895198 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 30332.895198 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 22106.446995 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 22106.446995 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 22106.446995 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 22106.446995 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 828861 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.296117 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764250 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764250 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 336817 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 336817 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8647 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8647 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1131 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1131 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9778 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9778 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9778 # number of overall hits +system.cpu1.l1c.overall_hits::total 9778 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36589 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36589 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23685 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23685 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60274 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60274 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60274 # number of overall misses +system.cpu1.l1c.overall_misses::total 60274 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 652011208 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 652011208 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 548619495 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 548619495 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1200630703 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1200630703 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1200630703 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1200630703 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45236 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45236 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24816 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24816 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70052 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70052 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70052 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70052 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808847 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.808847 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954425 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954425 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860418 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860418 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860418 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860418 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17819.869578 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 17819.869578 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23163.162128 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 23163.162128 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 19919.545791 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 19919.545791 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 19919.545791 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 19919.545791 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 748495 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62856 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 59422 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.186665 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.596261 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9918 # number of writebacks -system.cpu1.l1c.writebacks::total 9918 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36277 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36277 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24198 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 24198 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60475 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60475 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60475 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60475 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9741 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5463 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5463 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15204 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15204 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 566614984 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 566614984 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 709800398 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 709800398 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1276415382 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1276415382 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1276415382 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1276415382 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 713705140 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 713705140 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858653101 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858653101 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1572358241 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1572358241 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805601 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805601 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954556 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859252 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859252 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859252 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15619.124624 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15619.124624 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 29333.019175 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 29333.019175 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 21106.496602 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 73268.159327 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73268.159327 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 157176.112209 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157176.112209 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 103417.406012 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103417.406012 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks +system.cpu1.l1c.writebacks::total 9809 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36589 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36589 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23685 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23685 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60274 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60274 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60274 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60274 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9902 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9902 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5511 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5511 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15413 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15413 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 615423208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 615423208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 524934495 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 524934495 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1140357703 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1140357703 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1140357703 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1140357703 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 747152224 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 747152224 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 944376752 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 944376752 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1691528976 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1691528976 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808847 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808847 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954425 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954425 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860418 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860418 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860418 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16819.896909 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16819.896909 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22163.162128 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22163.162128 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18919.562382 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 75454.678247 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75454.678247 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 171362.139721 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171362.139721 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 109746.900409 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 109746.900409 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99726 # number of read accesses completed -system.cpu2.num_writes 55227 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22340 # number of replacements -system.cpu2.l1c.tags.tagsinuse 393.100704 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13463 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22750 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.591780 # Average number of references to valid blocks. +system.cpu2.num_reads 99705 # number of read accesses completed +system.cpu2.num_writes 55132 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22489 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.363987 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13472 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22889 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.588580 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 393.100704 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.767775 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.767775 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 400 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338035 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338035 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1109 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1109 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9766 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9766 # number of overall hits -system.cpu2.l1c.overall_hits::total 9766 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36622 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36622 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23922 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23922 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60544 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60544 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60544 # number of overall misses -system.cpu2.l1c.overall_misses::total 60544 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 606579368 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 606579368 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 739451035 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 739451035 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1346030403 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1346030403 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1346030403 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1346030403 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45279 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45279 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25031 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25031 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70310 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70310 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808808 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808808 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955695 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955695 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.861101 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.861101 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.861101 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.861101 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16563.250724 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16563.250724 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30910.920283 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 30910.920283 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 22232.267491 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 22232.267491 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 22232.267491 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 22232.267491 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 834628 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.363987 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.768289 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.768289 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 339330 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 339330 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8744 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8744 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1142 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1142 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9886 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9886 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9886 # number of overall hits +system.cpu2.l1c.overall_hits::total 9886 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36705 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36705 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23982 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23982 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60687 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60687 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60687 # number of overall misses +system.cpu2.l1c.overall_misses::total 60687 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 655863609 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 655863609 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 555301116 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 555301116 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1211164725 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1211164725 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1211164725 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1211164725 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25124 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70573 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70573 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70573 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70573 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807609 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.807609 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954545 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954545 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859918 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859918 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859918 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859918 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17868.508623 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 17868.508623 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23154.912685 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 23154.912685 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 19957.564635 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 19957.564635 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 19957.564635 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 19957.564635 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 744784 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 63193 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 59741 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.207602 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.466882 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9768 # number of writebacks -system.cpu2.l1c.writebacks::total 9768 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36622 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36622 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23922 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23922 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60544 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60544 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60544 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60544 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9774 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9774 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5417 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15191 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15191 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 569957368 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 569957368 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 715531035 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 715531035 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1285488403 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1285488403 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1285488403 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1285488403 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 714145091 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 714145091 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 834952155 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 834952155 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1549097246 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1549097246 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808808 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808808 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955695 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955695 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.861101 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.861101 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.861101 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15563.250724 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15563.250724 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29911.003888 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29911.003888 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 21232.300525 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73065.796092 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73065.796092 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154135.527968 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154135.527968 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 101974.672240 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 101974.672240 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9941 # number of writebacks +system.cpu2.l1c.writebacks::total 9941 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36705 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36705 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23982 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23982 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60687 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60687 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60687 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60687 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9745 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9745 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5541 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5541 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15286 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 619160609 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 619160609 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 531319116 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 531319116 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1150479725 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1150479725 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1150479725 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1150479725 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 736103391 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 736103391 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 958643718 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 958643718 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1694747109 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1694747109 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807609 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807609 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954545 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954545 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859918 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859918 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859918 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16868.563111 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16868.563111 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22154.912685 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22154.912685 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18957.597591 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75536.520369 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75536.520369 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 173009.153221 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173009.153221 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 110869.233874 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 110869.233874 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99494 # number of read accesses completed -system.cpu3.num_writes 54686 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22431 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.658378 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13393 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.586589 # Average number of references to valid blocks. +system.cpu3.num_reads 99493 # number of read accesses completed +system.cpu3.num_writes 55186 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22493 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.330553 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13483 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22894 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.588932 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.658378 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.766911 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.766911 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_blocks::cpu3 393.330553 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768224 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768224 # Average percentage of cache occupancy system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337999 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337999 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8615 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8615 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1106 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9721 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9721 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9721 # number of overall hits -system.cpu3.l1c.overall_hits::total 9721 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36594 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36594 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23974 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23974 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60568 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60568 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60568 # number of overall misses -system.cpu3.l1c.overall_misses::total 60568 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 607642440 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 607642440 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 730577546 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 730577546 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1338219986 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1338219986 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1338219986 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1338219986 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25080 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25080 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70289 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70289 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70289 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70289 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809441 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809441 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955901 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955901 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861700 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861700 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861700 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861700 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16604.974586 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16604.974586 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 30473.744306 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 30473.744306 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 22094.505118 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 22094.505118 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 22094.505118 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 22094.505118 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 833585 # number of cycles access was blocked +system.cpu3.l1c.tags.tag_accesses 338296 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338296 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8738 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8738 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1110 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1110 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9848 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9848 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9848 # number of overall hits +system.cpu3.l1c.overall_hits::total 9848 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36582 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36582 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23939 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23939 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60521 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60521 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60521 # number of overall misses +system.cpu3.l1c.overall_misses::total 60521 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 654319900 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 654319900 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 552232159 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 552232159 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1206552059 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1206552059 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1206552059 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1206552059 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45320 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45320 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25049 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70369 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70369 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70369 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70369 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807193 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807193 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955687 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955687 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860052 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860052 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860052 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860052 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17886.389481 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 17886.389481 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23068.305234 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 23068.305234 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 19936.089275 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 19936.089275 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 19936.089275 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 19936.089275 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 748969 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63208 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 59958 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.187967 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.491561 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9871 # number of writebacks -system.cpu3.l1c.writebacks::total 9871 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36594 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36594 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23974 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23974 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60568 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60568 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60568 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60568 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9814 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9814 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5449 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5449 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15263 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15263 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 571049440 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 571049440 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 706605546 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 706605546 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1277654986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1277654986 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1277654986 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1277654986 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 718813002 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 718813002 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 842609106 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 842609106 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1561422108 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1561422108 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809441 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955901 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955901 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861700 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861700 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861700 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15605.001913 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15605.001913 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 29473.827730 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 29473.827730 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 21094.554649 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 73243.631751 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73243.631751 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 154635.548908 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154635.548908 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102301.127432 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102301.127432 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9953 # number of writebacks +system.cpu3.l1c.writebacks::total 9953 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36582 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36582 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23939 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60521 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60521 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60521 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60521 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9878 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9878 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5388 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15266 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15266 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 617737900 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 617737900 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 528295159 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 528295159 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1146033059 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1146033059 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1146033059 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1146033059 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 746486832 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 746486832 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 927844496 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 927844496 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1674331328 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1674331328 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807193 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807193 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955687 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955687 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860052 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860052 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860052 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16886.389481 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16886.389481 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22068.388780 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22068.388780 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18936.122321 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75570.645070 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75570.645070 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 172205.734224 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172205.734224 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109677.147124 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109677.147124 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99490 # number of read accesses completed -system.cpu4.num_writes 54928 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22277 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.439470 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13388 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22671 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.590534 # Average number of references to valid blocks. +system.cpu4.num_reads 99921 # number of read accesses completed +system.cpu4.num_writes 55196 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22380 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.777413 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13581 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22786 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.596024 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.439470 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.764530 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.764530 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337649 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337649 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8692 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8692 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1145 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1145 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9837 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9837 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9837 # number of overall hits -system.cpu4.l1c.overall_hits::total 9837 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36462 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36462 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23928 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23928 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60390 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60390 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60390 # number of overall misses -system.cpu4.l1c.overall_misses::total 60390 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 604688688 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 604688688 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 724847511 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 724847511 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1329536199 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1329536199 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1329536199 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1329536199 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45154 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45154 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25073 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25073 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70227 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70227 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70227 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70227 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807503 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807503 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954333 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954333 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859926 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859926 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859926 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859926 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16584.078986 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16584.078986 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30292.858200 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 30292.858200 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 22015.833731 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 22015.833731 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 22015.833731 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 22015.833731 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 834109 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.777413 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.767143 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.767143 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 339211 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 339211 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8862 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8862 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1132 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1132 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9994 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9994 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9994 # number of overall hits +system.cpu4.l1c.overall_hits::total 9994 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36800 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36800 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23778 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23778 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60578 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60578 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60578 # number of overall misses +system.cpu4.l1c.overall_misses::total 60578 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 655197570 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 655197570 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 548908934 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 548908934 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1204106504 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1204106504 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1204106504 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1204106504 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45662 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45662 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24910 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24910 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70572 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70572 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70572 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70572 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805922 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805922 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954556 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954556 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858386 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858386 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858386 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858386 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17804.281793 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 17804.281793 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23084.739423 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 23084.739423 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 19876.960349 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 19876.960349 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 19876.960349 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 19876.960349 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 750268 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 63123 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 59848 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.214027 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.536225 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9949 # number of writebacks -system.cpu4.l1c.writebacks::total 9949 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36462 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36462 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23928 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23928 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60390 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60390 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9946 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5329 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5329 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15275 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15275 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 568228688 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 568228688 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 700919511 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 700919511 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1269148199 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1269148199 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1269148199 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1269148199 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 727166434 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 727166434 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 837934166 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 837934166 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1565100600 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1565100600 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807503 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807503 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954333 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954333 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859926 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859926 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859926 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15584.133838 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15584.133838 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29292.858200 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29292.858200 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 21015.866849 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 73111.445204 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73111.445204 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157240.413961 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157240.413961 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102461.577741 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102461.577741 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9770 # number of writebacks +system.cpu4.l1c.writebacks::total 9770 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36800 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36800 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23778 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23778 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60578 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60578 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60578 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60578 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9925 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9925 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5406 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5406 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15331 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15331 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 618398570 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 618398570 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 525131934 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 525131934 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1143530504 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1143530504 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1143530504 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1143530504 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 750294225 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 750294225 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 944567825 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 944567825 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1694862050 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1694862050 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805922 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805922 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954556 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954556 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858386 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858386 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858386 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16804.308967 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16804.308967 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22084.781479 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22084.781479 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18876.993364 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 75596.395466 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75596.395466 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174725.827784 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174725.827784 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 110551.304546 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 110551.304546 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99495 # number of read accesses completed -system.cpu5.num_writes 55318 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22409 # number of replacements -system.cpu5.l1c.tags.tagsinuse 392.682039 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13393 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22790 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.587670 # Average number of references to valid blocks. +system.cpu5.num_reads 99482 # number of read accesses completed +system.cpu5.num_writes 55607 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22456 # number of replacements +system.cpu5.l1c.tags.tagsinuse 392.242325 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13457 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22866 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.588516 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 392.682039 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.766957 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.766957 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337688 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337688 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8637 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8637 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1146 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1146 # number of WriteReq hits +system.cpu5.l1c.tags.occ_blocks::cpu5 392.242325 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.766098 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.766098 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 410 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.800781 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338143 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338143 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8578 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8578 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1205 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1205 # number of WriteReq hits system.cpu5.l1c.demand_hits::cpu5 9783 # number of demand (read+write) hits system.cpu5.l1c.demand_hits::total 9783 # number of demand (read+write) hits system.cpu5.l1c.overall_hits::cpu5 9783 # number of overall hits system.cpu5.l1c.overall_hits::total 9783 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36329 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36329 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24118 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24118 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60447 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60447 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60447 # number of overall misses -system.cpu5.l1c.overall_misses::total 60447 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 601479868 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 601479868 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 729882091 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 729882091 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1331361959 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1331361959 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1331361959 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1331361959 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44966 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25264 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25264 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70230 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70230 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807922 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.807922 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954639 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.954639 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860701 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860701 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860701 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860701 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16556.466404 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16556.466404 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 30262.960901 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 30262.960901 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 22025.277665 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 22025.277665 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 22025.277665 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 22025.277665 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 826632 # number of cycles access was blocked +system.cpu5.l1c.ReadReq_misses::cpu5 36239 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36239 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 24308 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 24308 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60547 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60547 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60547 # number of overall misses +system.cpu5.l1c.overall_misses::total 60547 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 647043171 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 647043171 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 559180438 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 559180438 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1206223609 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1206223609 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1206223609 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1206223609 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44817 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44817 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25513 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25513 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70330 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70330 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70330 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70330 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808599 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808599 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952769 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952769 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860899 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860899 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860899 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860899 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17854.884820 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 17854.884820 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23003.967336 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 23003.967336 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 19922.103638 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 19922.103638 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 19922.103638 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 19922.103638 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 749399 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 62727 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 59952 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.178249 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.499983 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9995 # number of writebacks -system.cpu5.l1c.writebacks::total 9995 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36329 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36329 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24118 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24118 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60447 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60447 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9798 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9798 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5473 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5473 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15271 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15271 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 565152868 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 565152868 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 705764091 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 705764091 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1270916959 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1270916959 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1270916959 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1270916959 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 717311081 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 717311081 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 861132955 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 861132955 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1578444036 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1578444036 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807922 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807922 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954639 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954639 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860701 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860701 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860701 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15556.521457 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15556.521457 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 29262.960901 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 29262.960901 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 21025.310752 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 73209.949071 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73209.949071 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 157342.034533 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157342.034533 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 103362.192129 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 103362.192129 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 10051 # number of writebacks +system.cpu5.l1c.writebacks::total 10051 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36239 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36239 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24308 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 24308 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60547 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60547 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60547 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60547 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9869 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5375 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5375 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15244 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15244 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 610804171 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 610804171 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 534872438 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 534872438 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1145676609 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1145676609 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1145676609 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1145676609 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 745114179 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 745114179 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 938602875 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 938602875 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1683717054 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1683717054 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808599 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808599 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952769 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952769 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860899 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860899 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860899 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16854.884820 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16854.884820 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22003.967336 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22003.967336 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18922.103638 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 75500.474111 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75500.474111 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 174623.790698 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174623.790698 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 110451.131855 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 110451.131855 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55059 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22318 # number of replacements -system.cpu6.l1c.tags.tagsinuse 390.741535 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13451 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22720 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.592033 # Average number of references to valid blocks. +system.cpu6.num_reads 99231 # number of read accesses completed +system.cpu6.num_writes 55266 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22476 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.210816 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13488 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22863 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.589949 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 390.741535 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.763167 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.763167 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338536 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338536 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8731 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8731 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1150 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1150 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9881 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9881 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9881 # number of overall hits -system.cpu6.l1c.overall_hits::total 9881 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36733 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36733 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23795 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23795 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60528 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60528 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60528 # number of overall misses -system.cpu6.l1c.overall_misses::total 60528 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 609896687 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 609896687 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 716784676 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 716784676 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1326681363 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1326681363 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1326681363 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1326681363 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45464 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45464 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24945 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24945 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70409 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70409 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70409 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70409 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807958 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807958 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953899 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953899 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859663 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859663 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859663 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859663 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16603.508752 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16603.508752 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 30123.331624 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 30123.331624 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21918.473483 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21918.473483 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21918.473483 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21918.473483 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 822803 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 393.210816 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767990 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767990 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 339081 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 339081 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9910 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9910 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9910 # number of overall hits +system.cpu6.l1c.overall_hits::total 9910 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36605 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36605 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 24011 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 24011 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60616 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60616 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60616 # number of overall misses +system.cpu6.l1c.overall_misses::total 60616 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 653690176 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 653690176 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 554778070 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 554778070 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1208468246 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1208468246 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1208468246 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1208468246 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45308 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45308 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25218 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25218 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70526 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70526 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70526 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70526 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807915 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807915 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952137 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.952137 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859484 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859484 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859484 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859484 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17857.947712 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 17857.947712 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23105.163050 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 23105.163050 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 19936.456480 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 19936.456480 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 19936.456480 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 19936.456480 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 748048 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62827 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 59929 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.096328 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.482237 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9777 # number of writebacks -system.cpu6.l1c.writebacks::total 9777 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36733 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36733 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23795 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23795 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60528 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60528 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60528 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60528 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9837 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9837 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5532 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5532 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15369 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 573164687 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 573164687 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 692991676 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 692991676 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1266156363 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1266156363 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1266156363 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1266156363 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 718909036 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 718909036 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 867837123 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 867837123 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1586746159 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1586746159 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807958 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807958 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953899 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953899 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859663 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859663 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859663 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15603.535976 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15603.535976 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 29123.415676 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 29123.415676 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20918.523047 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 73082.142523 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73082.142523 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 156875.835683 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156875.835683 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103243.292277 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103243.292277 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9811 # number of writebacks +system.cpu6.l1c.writebacks::total 9811 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36605 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24011 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 24011 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60616 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60616 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60616 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60616 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9828 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5436 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5436 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15264 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15264 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 617085176 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 617085176 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 530767070 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 530767070 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1147852246 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1147852246 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1147852246 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1147852246 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 743889866 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 743889866 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 938428736 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 938428736 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1682318602 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1682318602 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952137 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952137 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859484 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859484 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859484 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16857.947712 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16857.947712 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22105.163050 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22105.163050 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18936.456480 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 75690.869556 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75690.869556 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 172632.217807 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172632.217807 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 110214.793108 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 110214.793108 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99734 # number of read accesses completed -system.cpu7.num_writes 54921 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22329 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.290074 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13499 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22713 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.594329 # Average number of references to valid blocks. +system.cpu7.num_reads 99956 # number of read accesses completed +system.cpu7.num_writes 55531 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22312 # number of replacements +system.cpu7.l1c.tags.tagsinuse 393.161929 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13691 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22714 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.602756 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.290074 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766192 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766192 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338596 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338596 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8795 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8795 # number of ReadReq hits +system.cpu7.l1c.tags.occ_blocks::cpu7 393.161929 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.767894 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.767894 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338939 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338939 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8916 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8916 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1165 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1165 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9960 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9960 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9960 # number of overall hits -system.cpu7.l1c.overall_hits::total 9960 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36684 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36684 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60474 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60474 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60474 # number of overall misses -system.cpu7.l1c.overall_misses::total 60474 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 611011013 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 611011013 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 715403706 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 715403706 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1326414719 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1326414719 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1326414719 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1326414719 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45479 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45479 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24955 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24955 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70434 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70434 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70434 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70434 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806614 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806614 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953316 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953316 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858591 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858591 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858591 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858591 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16656.062943 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16656.062943 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 30071.614376 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 30071.614376 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21933.636257 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21933.636257 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21933.636257 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21933.636257 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 829723 # number of cycles access was blocked +system.cpu7.l1c.demand_hits::cpu7 10081 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 10081 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 10081 # number of overall hits +system.cpu7.l1c.overall_hits::total 10081 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36493 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36493 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23963 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23963 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60456 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60456 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60456 # number of overall misses +system.cpu7.l1c.overall_misses::total 60456 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 649044669 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 649044669 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 555516702 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 555516702 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1204561371 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1204561371 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1204561371 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1204561371 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45409 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25128 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25128 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70537 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70537 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70537 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70537 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803651 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803651 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953637 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953637 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.857082 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.857082 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.857082 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.857082 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17785.456636 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 17785.456636 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23182.268581 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 23182.268581 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 19924.595921 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 19924.595921 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 19924.595921 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 19924.595921 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 753584 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63058 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 60106 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.158093 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.537584 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9746 # number of writebacks -system.cpu7.l1c.writebacks::total 9746 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36684 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36684 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60474 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60474 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60474 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60474 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9918 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9918 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5421 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5421 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15339 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15339 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 574327013 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 574327013 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 691615706 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 691615706 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1265942719 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1265942719 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1265942719 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1265942719 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 726668427 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 726668427 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 847371643 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 847371643 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1574040070 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1574040070 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806614 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806614 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953316 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953316 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858591 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858591 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858591 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15656.062943 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15656.062943 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 29071.698445 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 29071.698445 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20933.669329 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 73267.637326 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73267.637326 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 156312.791551 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 156312.791551 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102616.863550 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102616.863550 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9825 # number of writebacks +system.cpu7.l1c.writebacks::total 9825 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36493 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36493 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23963 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23963 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60456 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60456 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60456 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60456 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9946 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9946 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5477 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5477 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15423 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15423 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 612553669 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 612553669 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 531553702 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 531553702 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1144107371 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1144107371 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1144107371 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1144107371 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 750008205 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 750008205 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 931574803 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 931574803 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1681583008 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1681583008 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803651 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803651 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953637 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953637 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.857082 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857082 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.857082 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16785.511441 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16785.511441 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22182.268581 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22182.268581 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18924.629003 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75408.023829 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75408.023829 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 170088.516158 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 170088.516158 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 109030.863516 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 109030.863516 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 14328 # number of replacements -system.l2c.tags.tagsinuse 791.177993 # Cycle average of tags in use -system.l2c.tags.total_refs 163940 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 15120 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.842593 # Average number of references to valid blocks. +system.l2c.tags.replacements 13679 # number of replacements +system.l2c.tags.tagsinuse 785.030982 # Cycle average of tags in use +system.l2c.tags.total_refs 164295 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14481 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.345556 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 732.189847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.660754 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.418431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.928491 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.181835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.391664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.508374 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.134486 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 7.764111 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.715029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007245 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007218 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006356 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006967 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.007582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.772635 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 650 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2105170 # Number of tag accesses -system.l2c.tags.data_accesses 2105170 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 77576 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77576 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 276 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 259 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 261 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 303 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 269 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2227 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1751 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1771 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1804 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1773 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1863 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1769 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1750 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1757 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14238 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10760 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10778 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10893 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 11049 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10672 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10913 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 11141 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10949 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 87155 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12511 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12697 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12535 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12706 # number of demand (read+write) hits -system.l2c.demand_hits::total 101393 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12511 # number of overall hits -system.l2c.overall_hits::cpu1 12549 # number of overall hits -system.l2c.overall_hits::cpu2 12697 # number of overall hits -system.l2c.overall_hits::cpu3 12822 # number of overall hits -system.l2c.overall_hits::cpu4 12535 # number of overall hits -system.l2c.overall_hits::cpu5 12682 # number of overall hits -system.l2c.overall_hits::cpu6 12891 # number of overall hits -system.l2c.overall_hits::cpu7 12706 # number of overall hits -system.l2c.overall_hits::total 101393 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2046 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2029 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2111 # number of UpgradeReq misses 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number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6350 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6496 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6621 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6441 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6459 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6363 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6261 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6314 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51305 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11531 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11539 # number of ReadSharedReq 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(read+write) accesses -system.l2c.demand_accesses::cpu4 17910 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17975 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18124 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18022 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 144429 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17881 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18035 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18283 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18199 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17910 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17975 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18124 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18022 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 144429 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.881137 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.886801 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.883264 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.887354 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.870291 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.885969 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.874623 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.873023 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.880327 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.724252 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.727371 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.727534 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.724732 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.711565 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.721986 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.720492 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.721729 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.722483 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.066863 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.065950 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.065941 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.060299 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.068029 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.060196 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.060862 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.064827 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.064097 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.300319 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.304186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.305530 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.295456 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.300112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.294465 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.288733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.294973 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.297973 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.300319 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.304186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.305530 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.295456 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.300112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.294465 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.294973 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.297973 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 35601.406158 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 34925.076885 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 35378.244908 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 35456.214008 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 35693.546483 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 32969.044019 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 35093.094089 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 36289.873679 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 35166.777622 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 63839.279626 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 63760.182222 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 63724.387793 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 63759.930591 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 63808.390992 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 63736.696125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 63693.574595 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 63773.836515 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 63761.952006 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68765.771725 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68892.788436 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69363.318596 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69021.739069 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68245.722721 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68995.566524 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69281.724377 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68727.146245 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 68905.889596 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 64546.602793 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 64472.160591 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 64500.674544 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 64453.741678 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 64451.494512 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 64431.188929 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 64464.574814 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 64481.052859 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64475.405010 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 64546.602793 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 64472.160591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 64500.674544 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 64453.741678 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 64451.494512 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 64431.188929 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 64464.574814 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 64481.052859 # average overall miss latency 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cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006943 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.007094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006901 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006317 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006713 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006806 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006919 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.766632 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 802 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per 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# number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 10825 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 10836 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 86729 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 12568 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12601 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12713 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12549 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12592 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12616 # number of demand (read+write) hits +system.l2c.demand_hits::total 101011 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12568 # number of overall hits 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number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 159063367 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 159738542 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1267666465 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 49231417 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 51778912 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 49960071 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 52497915 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 48409406 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 49972406 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 48755897 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 49161911 # number of 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6353 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6361 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6545 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6431 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6478 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51480 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11485 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11578 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11589 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11564 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11669 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11496 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11521 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11539 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92441 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17986 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17915 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18063 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17917 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18030 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17952 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18017 # number of demand (read+write) accesses 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0.060924 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.061791 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.301234 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.296623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.296186 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.299604 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.294176 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.299041 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.298574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.299772 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.298150 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.301234 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.296623 # miss rate for overall accesses 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ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 34001.392507 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 34078.887709 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70230.266762 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69877.074224 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 70664.881188 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69997.220000 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69156.294286 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69989.364146 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70051.576149 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69931.594595 # average ReadSharedReq miss latency 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(read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 154148371 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 153787468 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 154302292 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1233700860 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 156425796 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 153118465 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 153714512 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 154904663 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 153299293 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 154148371 # number of overall MSHR miss cycles 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uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 532738235 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4231987643 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 302507401 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 304491446 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 306673088 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 296941482 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 299721877 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 297975047 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 302462757 # number of WriteReq MSHR uncacheable cycles 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-system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.874623 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.873023 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.879897 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.723150 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726601 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.726476 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723645 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.711101 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.721358 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719534 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.720779 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.721606 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.066083 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.065170 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.064912 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.059704 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.066806 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059766 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.060187 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.064144 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063324 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.297163 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.299424 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.303410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.304491 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.294687 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.299162 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.293964 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287961 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.294196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.297163 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 53341.056724 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 53434.268775 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 53352.335386 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 53304.519221 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 53306.082677 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 53314.491388 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 53354.660591 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 53296.911928 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 53338.045682 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 53883.459930 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 53797.322458 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 53787.708108 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 53824.577558 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 53807.612671 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 53775.355556 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 53766.751387 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 53809.574379 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 53806.527929 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59102.244094 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59354.937500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59851.245707 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59219.962963 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58804.469281 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59213.835735 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59609.813725 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58991.884154 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59266.536035 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 54626.215540 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 54561.088268 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 54612.227232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 54530.816707 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 54521.049645 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 54489.644966 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 54566.127994 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 54543.620898 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54556.724062 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 52764.098533 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 52785.315368 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 52765.784326 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 52785.004688 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 52769.356762 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 52816.364564 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 52783.700823 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 52838.805102 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 52788.573706 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 54295.560625 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 54792.270414 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54559.892541 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 54609.213696 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 54556.747044 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 54641.302997 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 54897.485358 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 54617.265818 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 54621.150483 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 53315.849081 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 53506.356509 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 53405.474259 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 53436.149279 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 53392.965693 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 53470.330714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 53544.547726 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 53467.336006 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 53442.272686 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.879091 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.882378 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889944 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.876223 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877383 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875213 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.869163 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871599 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.877624 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.725119 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.720530 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.715941 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.726428 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.723000 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.713980 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.724926 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.723835 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.721698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060427 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062878 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.060402 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063992 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.058874 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.061413 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.059630 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060577 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061023 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.297344 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.300678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.295507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.295355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.298878 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.293178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.298154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.297961 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.299051 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.297344 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20793.145295 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20771.712555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.084384 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20737.336893 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20718.154568 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20760.129440 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20722.885454 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20708.580488 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20741.143139 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24285.835384 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 23942.015331 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 23976.722977 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23906.158397 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24418.595347 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 23905.807618 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24097.867653 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 23975.594157 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 24063.749388 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 60435.688761 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 60163.767857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 60832.001429 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 60240.191892 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59677.107715 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60108.402266 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 60324.903930 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59915.208870 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 60212.795426 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 28924.888314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 28923.019456 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 28812.467104 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 28927.107937 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 29001.001324 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 28657.440231 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 28750.695083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 28638.138827 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 28828.827873 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53478.342438 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53528.071198 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53575.323140 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53520.679490 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53508.103980 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53534.804641 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53571.977818 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53563.064046 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53534.903328 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 55252.493333 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 55271.636595 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 55356.153069 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 55111.633630 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 55462.967617 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 55437.218047 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 55650.921251 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 55411.013699 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 55369.106167 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 54107.738936 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 54151.346895 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 54220.779326 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 54082.192716 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 54197.260682 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 54205.591315 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 54312.268558 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 54219.151482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 54186.935729 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 127545 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 121489 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 125196 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 119242 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 78710 # Transaction distribution -system.membus.trans_dist::ReadResp 84594 # Transaction distribution -system.membus.trans_dist::WriteReq 43645 # Transaction distribution -system.membus.trans_dist::WriteResp 43644 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6662 # Transaction distribution -system.membus.trans_dist::CleanEvict 1288 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60944 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50160 # Transaction distribution -system.membus.trans_dist::ReadExReq 49324 # Transaction distribution -system.membus.trans_dist::ReadExResp 3261 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5890 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 428122 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1134381 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1134381 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56843 # Total snoops (count) -system.membus.snoop_fanout::samples 246442 # Request fanout histogram +system.membus.trans_dist::ReadReq 79046 # Transaction distribution +system.membus.trans_dist::ReadResp 84668 # Transaction distribution +system.membus.trans_dist::WriteReq 43599 # Transaction distribution +system.membus.trans_dist::WriteResp 43596 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6347 # Transaction distribution +system.membus.trans_dist::CleanEvict 1243 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60999 # Transaction distribution +system.membus.trans_dist::ReadExReq 49250 # Transaction distribution +system.membus.trans_dist::ReadExResp 3150 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5631 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377529 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 377529 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1090828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1090828 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56847 # Total snoops (count) +system.membus.snoop_fanout::samples 245688 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 246442 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 245688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 246442 # Request fanout histogram -system.membus.reqLayer0.occupancy 292771939 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.1 # Layer utilization (%) -system.membus.respLayer0.occupancy 296967000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 54.9 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 667370 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 284034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 336982 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12889 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6892 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78711 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370868 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 5 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43646 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43643 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 84238 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20479 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29389 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29387 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162232 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162225 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292173 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122572 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122851 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122953 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122967 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122678 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 981914 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769628 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1794530 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1801428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1789097 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1796324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1791880 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1784489 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14330220 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335082 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 628739 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.148986 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.990092 # Request fanout histogram +system.membus.snoop_fanout::total 245688 # Request fanout histogram +system.membus.reqLayer0.occupancy 290283631 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.2 # Layer utilization (%) +system.membus.respLayer0.occupancy 245575000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 45.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 665524 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283935 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335837 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12315 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6571 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 79051 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371557 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43601 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43596 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 84007 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105887 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29231 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29230 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162413 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162411 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 292528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133251 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133559 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133487 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1068067 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1785416 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1780080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1798067 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1787232 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784031 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1781660 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1785403 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14303561 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 335445 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 626448 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148675 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.987271 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 176143 28.02% 28.02% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 257926 41.02% 69.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 134453 21.38% 90.42% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 47224 7.51% 97.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 11211 1.78% 99.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1632 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 146 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 174709 27.89% 27.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 258191 41.22% 69.10% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 133874 21.37% 90.47% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 46929 7.49% 97.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 11007 1.76% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1601 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 133 0.02% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 628739 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 500695190 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 92.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 101141048 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101214213 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101195728 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 101296930 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 101179412 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 101203668 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101388789 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 18.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101354632 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 18.7 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 626448 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 498178453 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102533331 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102040683 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102532818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102294677 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.1 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102527849 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102329742 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.1 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102510939 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 102349372 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index ffbbc56b2..36475e393 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1811 +1,1811 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000534 # Number of seconds simulated -sim_ticks 534039500 # Number of ticks simulated -final_tick 534039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000530 # Number of seconds simulated +sim_ticks 530176500 # Number of ticks simulated +final_tick 530176500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 46952087 # Simulator tick rate (ticks/s) -host_mem_usage 215976 # Number of bytes of host memory used -host_seconds 11.37 # Real time elapsed on the host +host_tick_rate 118834220 # Simulator tick rate (ticks/s) +host_mem_usage 236308 # Number of bytes of host memory used +host_seconds 4.46 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 80135 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 83816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 79566 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 82290 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82935 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 84320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79631 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 84304 # Number of bytes read from this memory -system.physmem.bytes_read::total 656997 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 418368 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5388 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5503 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5449 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5363 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5499 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5488 # Number of bytes written to this memory -system.physmem.bytes_written::total 461890 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10833 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10989 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10835 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10972 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87288 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6537 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5512 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5388 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5503 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5449 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5363 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5499 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5488 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50059 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 150054444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 156947192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 148988979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 154089726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 155297501 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 157890943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 149110693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 157860982 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1230240460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 783402726 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10321334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10089141 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 9961810 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10304481 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10203365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10042328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10296991 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10276393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 864898570 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 783402726 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 160375777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 167036333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 158950789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 164394207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165500867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 167933271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 159407684 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 168137376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2095139030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 78184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 80178 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 79911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80308 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 82157 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 80611 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 79164 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 81441 # Number of bytes read from this memory +system.physmem.bytes_read::total 641954 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 404160 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5485 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5418 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5526 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5422 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5386 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5538 # Number of bytes written to this memory +system.physmem.bytes_written::total 447793 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11071 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10935 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10881 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87113 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5485 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5400 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5418 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5526 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5422 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5458 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5386 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5538 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49948 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 147467872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 151228883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 150725277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 151474085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 154961602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 152045592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 149316313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 153611109 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1210830733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 762312173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10345611 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10185287 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10219238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10422944 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10226783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10294685 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10158881 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10445578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 844611181 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 762312173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 157813483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 161414171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 160944516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 161897029 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 165188385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 162340277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 159475194 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 164056687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2055441914 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 98970 # number of read accesses completed -system.cpu0.num_writes 54697 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22262 # number of replacements -system.cpu0.l1c.tags.tagsinuse 392.444163 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13142 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22657 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.580041 # Average number of references to valid blocks. +system.cpu0.num_reads 99175 # number of read accesses completed +system.cpu0.num_writes 54789 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22440 # number of replacements +system.cpu0.l1c.tags.tagsinuse 392.189512 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13440 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22832 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.588648 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 392.444163 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.766493 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.766493 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 335259 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 335259 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8424 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8424 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1108 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1108 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9532 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9532 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9532 # number of overall hits -system.cpu0.l1c.overall_hits::total 9532 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36392 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36392 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23768 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23768 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60160 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60160 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60160 # number of overall misses -system.cpu0.l1c.overall_misses::total 60160 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 598420373 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 598420373 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 705577272 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 705577272 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1303997645 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1303997645 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1303997645 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1303997645 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44816 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44816 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24876 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24876 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69692 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69692 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69692 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69692 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.812031 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.812031 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955459 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.955459 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.863227 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.863227 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.863227 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.863227 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16443.734145 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 16443.734145 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 29686.017839 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 29686.017839 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21675.492769 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21675.492769 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21675.492769 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21675.492769 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 798798 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 392.189512 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765995 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765995 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338141 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338141 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8693 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8693 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1204 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1204 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9897 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9897 # number of overall hits +system.cpu0.l1c.overall_hits::total 9897 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36509 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36509 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23927 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23927 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60436 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60436 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60436 # number of overall misses +system.cpu0.l1c.overall_misses::total 60436 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 645236912 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 645236912 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 543361201 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 543361201 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1188598113 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1188598113 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1188598113 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1188598113 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45202 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45202 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25131 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25131 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70333 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70333 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70333 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70333 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807686 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807686 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952091 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952091 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859284 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859284 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859284 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859284 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 17673.365800 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 17673.365800 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 22709.123626 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 22709.123626 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 19667.054620 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 19667.054620 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 19667.054620 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 19667.054620 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 716464 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 61887 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 58624 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.907363 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.221343 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9766 # number of writebacks -system.cpu0.l1c.writebacks::total 9766 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36392 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36392 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23768 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23768 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60160 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60160 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9799 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9799 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5512 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5512 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15311 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 562029373 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 562029373 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 681810272 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 681810272 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1243839645 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1243839645 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1243839645 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1243839645 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 706647630 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 706647630 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 855364129 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 855364129 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1562011759 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1562011759 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.812031 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.812031 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955459 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955459 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.863227 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.863227 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.863227 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15443.761623 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15443.761623 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 28686.059912 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 28686.059912 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20675.526014 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 72114.259618 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72114.259618 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 155182.171444 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155182.171444 # average WriteReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 102018.924891 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 102018.924891 # average overall mshr uncacheable latency +system.cpu0.l1c.writebacks::writebacks 9950 # number of writebacks +system.cpu0.l1c.writebacks::total 9950 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36509 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36509 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23927 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60436 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60436 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60436 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60436 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9705 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9705 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5489 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5489 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15194 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15194 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 608727912 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 608727912 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 519435201 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 519435201 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1128163113 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1128163113 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1128163113 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1128163113 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 718425919 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 718425919 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 939004763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 939004763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1657430682 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1657430682 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807686 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807686 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952091 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952091 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859284 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859284 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859284 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859284 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 16673.365800 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 16673.365800 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 21709.165420 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 21709.165420 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 18667.071166 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 74026.369809 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74026.369809 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 171070.279286 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 171070.279286 # average WriteReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 109084.551928 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 109084.551928 # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98379 # number of read accesses completed -system.cpu1.num_writes 54883 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22236 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.015365 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13378 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22622 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.591371 # Average number of references to valid blocks. +system.cpu1.num_reads 99705 # number of read accesses completed +system.cpu1.num_writes 54823 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22335 # number of replacements +system.cpu1.l1c.tags.tagsinuse 390.697643 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13624 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22725 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.599516 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.015365 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.763702 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.763702 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_blocks::cpu1 390.697643 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.763081 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.763081 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id system.cpu1.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 335372 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 335372 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8546 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8546 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1143 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9689 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9689 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9689 # number of overall hits -system.cpu1.l1c.overall_hits::total 9689 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36240 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36240 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23835 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23835 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60075 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60075 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60075 # number of overall misses -system.cpu1.l1c.overall_misses::total 60075 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 593535449 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 593535449 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 712426271 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 712426271 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1305961720 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1305961720 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1305961720 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1305961720 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44786 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44786 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24978 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24978 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 69764 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 69764 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 69764 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 69764 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.809181 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.809181 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954240 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954240 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.861117 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.861117 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.861117 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.861117 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16377.909741 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 16377.909741 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 29889.921166 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 29889.921166 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21738.855098 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21738.855098 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21738.855098 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21738.855098 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 803378 # number of cycles access was blocked +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 339221 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 339221 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8840 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8840 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1148 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1148 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9988 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9988 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9988 # number of overall hits +system.cpu1.l1c.overall_hits::total 9988 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36605 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36605 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23987 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23987 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60592 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60592 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60592 # number of overall misses +system.cpu1.l1c.overall_misses::total 60592 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 646842299 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 646842299 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 543658224 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 543658224 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1190500523 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1190500523 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1190500523 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1190500523 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45445 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45445 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25135 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25135 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70580 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70580 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70580 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70580 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805479 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805479 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954327 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954327 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858487 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858487 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858487 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858487 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 17670.872804 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 17670.872804 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 22664.702714 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 22664.702714 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 19647.816923 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 19647.816923 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 19647.816923 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 19647.816923 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 718948 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62137 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 59028 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.929140 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.179779 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9779 # number of writebacks -system.cpu1.l1c.writebacks::total 9779 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36240 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36240 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23835 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23835 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60075 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60075 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60075 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60075 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9833 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9833 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5388 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5388 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15221 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 557295449 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 557295449 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 688592271 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 688592271 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1245887720 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1245887720 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1245887720 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1245887720 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 707451122 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 707451122 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 858171680 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 858171680 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1565622802 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1565622802 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809181 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.809181 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954240 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954240 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.861117 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861117 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.861117 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15377.909741 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15377.909741 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 28889.963121 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 28889.963121 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20738.871744 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 71946.620767 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71946.620767 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 159274.625093 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159274.625093 # average WriteReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 102859.391761 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 102859.391761 # average overall mshr uncacheable latency +system.cpu1.l1c.writebacks::writebacks 9932 # number of writebacks +system.cpu1.l1c.writebacks::total 9932 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36605 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36605 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23987 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23987 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60592 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60592 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60592 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60592 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9715 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9715 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5400 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15115 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15115 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 610238299 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 610238299 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 519672224 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 519672224 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1129910523 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1129910523 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1129910523 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1129910523 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 721621903 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 721621903 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 954237303 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 954237303 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1675859206 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1675859206 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805479 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805479 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954327 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954327 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858487 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858487 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858487 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858487 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 16670.900123 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 16670.900123 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 21664.744403 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 21664.744403 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 18647.849931 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74279.145960 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74279.145960 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 176710.611667 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 176710.611667 # average WriteReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 110873.913728 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 110873.913728 # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99126 # number of read accesses completed -system.cpu2.num_writes 55057 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22416 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.045662 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13448 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22823 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.589230 # Average number of references to valid blocks. +system.cpu2.num_reads 99117 # number of read accesses completed +system.cpu2.num_writes 54908 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22381 # number of replacements +system.cpu2.l1c.tags.tagsinuse 392.253516 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13534 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22797 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.593675 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.045662 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.765714 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.765714 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337969 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337969 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8656 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8656 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1187 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1187 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9843 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9843 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9843 # number of overall hits -system.cpu2.l1c.overall_hits::total 9843 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36613 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36613 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23839 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23839 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60452 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60452 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60452 # number of overall misses -system.cpu2.l1c.overall_misses::total 60452 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 594021809 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 594021809 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 716005587 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 716005587 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1310027396 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1310027396 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1310027396 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1310027396 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45269 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45269 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25026 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70295 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70295 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70295 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70295 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808787 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808787 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952569 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952569 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859976 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859976 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859976 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859976 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16224.341327 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 16224.341327 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 30035.051261 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 30035.051261 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21670.538543 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21670.538543 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21670.538543 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21670.538543 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 801429 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 392.253516 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.766120 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.766120 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 416 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338010 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338010 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8679 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8679 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1137 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9816 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9816 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9816 # number of overall hits +system.cpu2.l1c.overall_hits::total 9816 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36478 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36478 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24024 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24024 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60502 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60502 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60502 # number of overall misses +system.cpu2.l1c.overall_misses::total 60502 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 647459345 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 647459345 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 543523925 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 543523925 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1190983270 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1190983270 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1190983270 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1190983270 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45157 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45157 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25161 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25161 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70318 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70318 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70318 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70318 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.807804 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.807804 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954811 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954811 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.860406 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.860406 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.860406 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.860406 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 17749.310406 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 17749.310406 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 22624.206002 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 22624.206002 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 19685.023140 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 19685.023140 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 19685.023140 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 19685.023140 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 722959 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62324 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 59032 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.859075 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.246900 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9798 # number of writebacks -system.cpu2.l1c.writebacks::total 9798 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36613 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36613 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23839 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23839 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60452 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60452 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60452 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60452 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9743 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5322 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5322 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15065 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15065 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 557410809 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 557410809 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 692167587 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 692167587 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1249578396 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1249578396 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1249578396 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1249578396 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 702012144 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 702012144 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 835893746 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 835893746 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1537905890 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1537905890 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808787 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808787 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952569 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952569 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859976 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859976 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859976 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15224.395952 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15224.395952 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 29035.093209 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 29035.093209 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20670.588169 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 72052.975880 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72052.975880 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 157063.838031 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157063.838031 # average WriteReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 102084.692333 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 102084.692333 # average overall mshr uncacheable latency +system.cpu2.l1c.writebacks::writebacks 9774 # number of writebacks +system.cpu2.l1c.writebacks::total 9774 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36478 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36478 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24024 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24024 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60502 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60502 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60502 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60502 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9767 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9767 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5419 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5419 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15186 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15186 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 610981345 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 610981345 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 519499925 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 519499925 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1130481270 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1130481270 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1130481270 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1130481270 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 722748371 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 722748371 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 934057840 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 934057840 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1656806211 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1656806211 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.807804 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.807804 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954811 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954811 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860406 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.860406 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860406 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.860406 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 16749.310406 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 16749.310406 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 21624.206002 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 21624.206002 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 18685.023140 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 73999.014129 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 73999.014129 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 172367.196900 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 172367.196900 # average WriteReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 109100.896286 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 109100.896286 # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99267 # number of read accesses completed -system.cpu3.num_writes 54937 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22308 # number of replacements -system.cpu3.l1c.tags.tagsinuse 393.396608 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13642 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22699 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.600996 # Average number of references to valid blocks. +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55255 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22194 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.395366 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13678 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22603 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.605141 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 393.396608 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.768353 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.768353 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 336965 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 336965 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8834 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8834 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1126 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1126 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9960 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9960 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9960 # number of overall hits -system.cpu3.l1c.overall_hits::total 9960 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36404 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36404 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23769 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23769 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60173 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60173 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60173 # number of overall misses -system.cpu3.l1c.overall_misses::total 60173 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 595557078 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 595557078 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 707954928 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 707954928 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1303512006 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1303512006 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1303512006 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1303512006 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45238 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45238 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24895 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24895 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70133 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70133 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70133 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70133 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804722 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.804722 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954770 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954770 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.857984 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.857984 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.857984 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.857984 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16359.660422 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 16359.660422 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 29784.800707 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 29784.800707 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21662.739202 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21662.739202 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21662.739202 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21662.739202 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 796210 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.395366 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.764444 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.764444 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 403 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 337339 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 337339 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8923 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8923 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1132 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1132 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 10055 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 10055 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 10055 # number of overall hits +system.cpu3.l1c.overall_hits::total 10055 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36521 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36521 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23639 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23639 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60160 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60160 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60160 # number of overall misses +system.cpu3.l1c.overall_misses::total 60160 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 641069966 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 641069966 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 531956623 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 531956623 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1173026589 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1173026589 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1173026589 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1173026589 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45444 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45444 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24771 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24771 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70215 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70215 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70215 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70215 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.803648 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.803648 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954301 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954301 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.856797 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.856797 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.856797 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.856797 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 17553.461461 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 17553.461461 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 22503.347138 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 22503.347138 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 19498.447291 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 19498.447291 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 19498.447291 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 19498.447291 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 718925 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 61792 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.885325 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.224121 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9835 # number of writebacks -system.cpu3.l1c.writebacks::total 9835 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36404 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36404 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23769 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23769 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60173 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60173 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60173 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60173 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9778 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9778 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5503 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5503 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15281 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15281 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 559153078 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 559153078 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 684188928 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 684188928 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1243342006 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1243342006 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1243342006 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1243342006 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 702217176 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 702217176 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 867552200 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 867552200 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1569769376 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1569769376 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804722 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804722 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954770 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954770 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.857984 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857984 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.857984 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15359.660422 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15359.660422 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 28784.926922 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 28784.926922 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20662.789058 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 71816.033545 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71816.033545 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 157650.772306 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157650.772306 # average WriteReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 102726.874943 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 102726.874943 # average overall mshr uncacheable latency +system.cpu3.l1c.writebacks::writebacks 9851 # number of writebacks +system.cpu3.l1c.writebacks::total 9851 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36521 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36521 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23639 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60160 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60160 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60160 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60160 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9973 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9973 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5527 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15500 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15500 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 604549966 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 604549966 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 508318623 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 508318623 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1112868589 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1112868589 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1112868589 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1112868589 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738348758 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738348758 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 962176807 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 962176807 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1700525565 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1700525565 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.803648 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.803648 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954301 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954301 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.856797 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.856797 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.856797 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.856797 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 16553.488842 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 16553.488842 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 21503.389441 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 21503.389441 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 18498.480535 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 74034.769678 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74034.769678 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 174086.630541 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174086.630541 # average WriteReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 109711.326774 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 109711.326774 # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 98613 # number of read accesses completed -system.cpu4.num_writes 54610 # number of write accesses completed -system.cpu4.l1c.tags.replacements 21998 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.447255 # Cycle average of tags in use +system.cpu4.num_reads 98958 # number of read accesses completed +system.cpu4.num_writes 54718 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22445 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.205168 # Cycle average of tags in use system.cpu4.l1c.tags.total_refs 13326 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22393 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.595097 # Average number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22839 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.583476 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.447255 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.766499 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.766499 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 385 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 335144 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 335144 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8557 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8557 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9727 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9727 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9727 # number of overall hits -system.cpu4.l1c.overall_hits::total 9727 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36223 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36223 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23758 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23758 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59981 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59981 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59981 # number of overall misses -system.cpu4.l1c.overall_misses::total 59981 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 587952444 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 587952444 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 716203349 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 716203349 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1304155793 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1304155793 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1304155793 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1304155793 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44780 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44780 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24928 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24928 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69708 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69708 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69708 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69708 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.808910 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.808910 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953065 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953065 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860461 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860461 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860461 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860461 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16231.467410 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 16231.467410 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 30145.776118 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 30145.776118 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21742.815108 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21742.815108 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21742.815108 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21742.815108 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 805297 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.205168 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766026 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766026 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 336585 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 336585 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8551 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8551 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1195 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1195 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9746 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9746 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9746 # number of overall hits +system.cpu4.l1c.overall_hits::total 9746 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36430 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36430 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23820 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23820 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60250 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60250 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60250 # number of overall misses +system.cpu4.l1c.overall_misses::total 60250 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 646410865 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 646410865 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 541537295 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 541537295 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1187948160 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1187948160 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1187948160 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1187948160 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44981 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44981 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25015 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25015 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809898 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.809898 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952229 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952229 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.860763 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.860763 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.860763 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.860763 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 17743.916141 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 17743.916141 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 22734.563182 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 22734.563182 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 19716.981909 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 19716.981909 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 19716.981909 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 19716.981909 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 719943 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 61957 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 58800 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.997676 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.243929 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9749 # number of writebacks -system.cpu4.l1c.writebacks::total 9749 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36223 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36223 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23758 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23758 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59981 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59981 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59981 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59981 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9847 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9847 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5452 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5452 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 551729444 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 551729444 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 692447349 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 692447349 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1244176793 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1244176793 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1244176793 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1244176793 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 708336585 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 708336585 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 860694197 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 860694197 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1569030782 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1569030782 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.808910 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.808910 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953065 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953065 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860461 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860461 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860461 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15231.467410 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15231.467410 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 29145.860300 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 29145.860300 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20742.848452 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 71934.252564 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71934.252564 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157867.607667 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157867.607667 # average WriteReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 102557.734623 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 102557.734623 # average overall mshr uncacheable latency +system.cpu4.l1c.writebacks::writebacks 9851 # number of writebacks +system.cpu4.l1c.writebacks::total 9851 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36430 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23820 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23820 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60250 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60250 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60250 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60250 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9773 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5424 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5424 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15197 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15197 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 609980865 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 609980865 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 517717295 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 517717295 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1127698160 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1127698160 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1127698160 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1127698160 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 724329762 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 724329762 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 945564873 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 945564873 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1669894635 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1669894635 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809898 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809898 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952229 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952229 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860763 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.860763 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860763 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.860763 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 16743.916141 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 16743.916141 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 21734.563182 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 21734.563182 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 18716.981909 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74115.395682 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74115.395682 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 174329.806969 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 174329.806969 # average WriteReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 109883.176614 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 109883.176614 # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99530 # number of read accesses completed -system.cpu5.num_writes 55068 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22260 # number of replacements -system.cpu5.l1c.tags.tagsinuse 393.692529 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13670 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22641 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.603772 # Average number of references to valid blocks. +system.cpu5.num_reads 99011 # number of read accesses completed +system.cpu5.num_writes 55007 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22453 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.576438 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13255 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22854 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.579986 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 393.692529 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.768931 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.768931 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337364 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337364 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8908 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8908 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1154 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1154 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 10062 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 10062 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 10062 # number of overall hits -system.cpu5.l1c.overall_hits::total 10062 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36264 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36264 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23895 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23895 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60159 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60159 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60159 # number of overall misses -system.cpu5.l1c.overall_misses::total 60159 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 595565994 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 595565994 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 715910266 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 715910266 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1311476260 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1311476260 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1311476260 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1311476260 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45172 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45172 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25049 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70221 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70221 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70221 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70221 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802798 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.802798 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953930 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953930 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.856710 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.856710 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.856710 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.856710 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16423.064030 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 16423.064030 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 29960.672358 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 29960.672358 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21800.167224 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21800.167224 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21800.167224 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21800.167224 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 800309 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.576438 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.764798 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.764798 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 336606 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 336606 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8524 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8524 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1134 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9658 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9658 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9658 # number of overall hits +system.cpu5.l1c.overall_hits::total 9658 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36435 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36435 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23892 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23892 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60327 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60327 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60327 # number of overall misses +system.cpu5.l1c.overall_misses::total 60327 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 644721410 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 644721410 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 540612961 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 540612961 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1185334371 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1185334371 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1185334371 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1185334371 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44959 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44959 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25026 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25026 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69985 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69985 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69985 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69985 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810405 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.810405 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954687 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954687 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.861999 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.861999 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.861999 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.861999 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 17695.112117 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 17695.112117 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 22627.363176 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 22627.363176 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 19648.488587 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 19648.488587 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 19648.488587 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 19648.488587 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 717184 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 61932 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 58708 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.922383 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.216120 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9774 # number of writebacks -system.cpu5.l1c.writebacks::total 9774 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36264 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36264 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23895 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23895 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60159 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60159 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60159 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60159 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9698 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9698 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5363 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5363 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15061 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15061 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 559302994 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 559302994 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 692016266 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 692016266 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1251319260 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1251319260 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1251319260 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1251319260 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 697234186 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 697234186 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 847695253 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 847695253 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1544929439 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1544929439 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802798 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802798 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953930 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953930 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.856710 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856710 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.856710 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15423.091606 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15423.091606 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 28960.714208 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 28960.714208 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20800.200469 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 71894.636626 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71894.636626 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 158063.630990 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158063.630990 # average WriteReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 102578.144811 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 102578.144811 # average overall mshr uncacheable latency +system.cpu5.l1c.writebacks::writebacks 9910 # number of writebacks +system.cpu5.l1c.writebacks::total 9910 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36435 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36435 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23892 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23892 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60327 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60327 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60327 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60327 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9763 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9763 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5458 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15221 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15221 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 608288410 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 608288410 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 516720961 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 516720961 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1125009371 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1125009371 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1125009371 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1125009371 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 723860386 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 723860386 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 946272316 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 946272316 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1670132702 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1670132702 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.810405 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810405 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954687 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954687 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.861999 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.861999 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861999 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.861999 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 16695.167010 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 16695.167010 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 21627.363176 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 21627.363176 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 18648.521740 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74143.233227 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74143.233227 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 173373.454745 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173373.454745 # average WriteReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 109725.556928 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 109725.556928 # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 100001 # number of read accesses completed -system.cpu6.num_writes 54955 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22371 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.789220 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13659 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.599789 # Average number of references to valid blocks. +system.cpu6.num_reads 99860 # number of read accesses completed +system.cpu6.num_writes 55212 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22379 # number of replacements +system.cpu6.l1c.tags.tagsinuse 392.641405 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13476 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22769 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.591857 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.789220 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.767166 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.767166 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338676 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338676 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8791 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8791 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1193 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1193 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9984 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9984 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9984 # number of overall hits -system.cpu6.l1c.overall_hits::total 9984 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36779 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36779 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23715 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23715 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60494 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60494 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60494 # number of overall misses -system.cpu6.l1c.overall_misses::total 60494 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 595549144 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 595549144 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 708070907 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 708070907 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1303620051 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1303620051 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1303620051 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1303620051 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45570 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45570 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24908 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70478 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70478 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70478 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70478 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807088 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.807088 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952104 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.952104 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858339 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858339 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858339 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858339 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16192.641018 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 16192.641018 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 29857.512418 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 29857.512418 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21549.576008 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21549.576008 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21549.576008 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21549.576008 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 794028 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 392.641405 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.766878 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.766878 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338111 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338111 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8761 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1100 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1100 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits +system.cpu6.l1c.overall_hits::total 9861 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36533 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36533 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23935 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23935 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60468 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60468 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60468 # number of overall misses +system.cpu6.l1c.overall_misses::total 60468 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 641137331 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 641137331 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 545446790 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 545446790 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1186584121 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1186584121 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1186584121 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1186584121 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45294 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45294 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25035 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70329 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70329 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70329 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70329 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806575 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806575 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956062 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956062 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859788 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859788 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859788 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859788 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 17549.539622 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 17549.539622 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 22788.668895 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 22788.668895 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 19623.339965 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 19623.339965 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 19623.339965 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 19623.339965 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 722832 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62044 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 59177 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.797821 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.214746 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9773 # number of writebacks -system.cpu6.l1c.writebacks::total 9773 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36779 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36779 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23715 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23715 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60494 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60494 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60494 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60494 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9743 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5502 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5502 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15245 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15245 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 558770144 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 558770144 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 684356907 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 684356907 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1243127051 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1243127051 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1243127051 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1243127051 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702205139 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702205139 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 875087157 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 875087157 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1577292296 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1577292296 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807088 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807088 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952104 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952104 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858339 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858339 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858339 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15192.641018 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15192.641018 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 28857.554586 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 28857.554586 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20549.592538 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 72072.784461 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 72072.784461 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 159048.919847 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 159048.919847 # average WriteReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 103462.925287 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 103462.925287 # average overall mshr uncacheable latency +system.cpu6.l1c.writebacks::writebacks 9900 # number of writebacks +system.cpu6.l1c.writebacks::total 9900 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36533 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36533 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23935 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23935 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60468 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60468 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60468 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60468 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9853 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9853 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5386 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5386 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15239 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 604606331 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 604606331 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 521511790 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 521511790 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1126118121 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1126118121 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1126118121 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1126118121 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 730958843 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 730958843 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 936459347 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 936459347 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1667418190 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1667418190 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806575 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806575 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956062 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956062 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859788 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859788 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859788 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859788 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 16549.594367 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 16549.594367 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 21788.668895 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 21788.668895 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 18623.373040 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74186.424744 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74186.424744 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 173869.169514 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173869.169514 # average WriteReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 109417.822036 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 109417.822036 # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99732 # number of read accesses completed -system.cpu7.num_writes 55186 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22105 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.370136 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13595 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22490 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.604491 # Average number of references to valid blocks. +system.cpu7.num_reads 99316 # number of read accesses completed +system.cpu7.num_writes 55530 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22262 # number of replacements +system.cpu7.l1c.tags.tagsinuse 392.242621 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13656 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22650 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.602914 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.370136 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.764395 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.764395 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 385 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_blocks::cpu7 392.242621 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.766099 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.766099 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id system.cpu7.l1c.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.751953 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 337196 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 337196 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8779 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8779 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1155 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1155 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9934 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9934 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9934 # number of overall hits -system.cpu7.l1c.overall_hits::total 9934 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36327 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36327 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23913 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23913 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60240 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60240 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60240 # number of overall misses -system.cpu7.l1c.overall_misses::total 60240 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 591115609 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 591115609 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 714870765 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 714870765 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1305986374 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1305986374 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1305986374 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1305986374 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45106 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25068 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70174 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70174 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70174 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70174 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805370 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805370 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953925 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953925 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858438 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858438 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858438 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858438 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16272.073361 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 16272.073361 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 29894.649981 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 29894.649981 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21679.720684 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21679.720684 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21679.720684 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21679.720684 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 800916 # number of cycles access was blocked +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 338652 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 338652 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8912 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8912 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1186 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1186 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 10098 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 10098 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 10098 # number of overall hits +system.cpu7.l1c.overall_hits::total 10098 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36380 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36380 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23998 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23998 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60378 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60378 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60378 # number of overall misses +system.cpu7.l1c.overall_misses::total 60378 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 644409565 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 644409565 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 538142857 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 538142857 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1182552422 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1182552422 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1182552422 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1182552422 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45292 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25184 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25184 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70476 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70476 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70476 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70476 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.803232 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.803232 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952907 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952907 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.856717 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.856717 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.856717 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.856717 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 17713.292056 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 17713.292056 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 22424.487749 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 22424.487749 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 19585.816390 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 19585.816390 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 19585.816390 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 19585.816390 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 716334 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62109 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 58812 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.895329 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.180065 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9688 # number of writebacks -system.cpu7.l1c.writebacks::total 9688 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36327 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36327 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23913 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23913 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60240 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60240 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60240 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60240 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5490 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5490 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15298 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15298 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 554789609 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 554789609 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 690958765 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 690958765 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1245748374 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1245748374 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1245748374 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1245748374 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 704741576 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 704741576 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 868948151 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 868948151 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1573689727 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1573689727 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805370 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805370 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953925 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953925 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858438 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858438 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858438 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 15272.100889 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15272.100889 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 28894.691799 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 28894.691799 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20679.753884 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 71853.749592 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 71853.749592 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 158278.351730 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 158278.351730 # average WriteReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 102868.984639 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 102868.984639 # average overall mshr uncacheable latency +system.cpu7.l1c.writebacks::writebacks 9846 # number of writebacks +system.cpu7.l1c.writebacks::total 9846 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36380 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36380 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23998 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23998 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60378 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60378 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9762 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9762 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5539 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5539 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15301 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15301 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 608029565 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 608029565 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 514144857 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 514144857 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1122174422 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1122174422 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1122174422 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1122174422 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 722808914 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 722808914 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 961004780 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 961004780 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1683813694 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1683813694 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.803232 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.803232 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952907 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952907 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856717 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.856717 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856717 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.856717 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 16713.292056 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 16713.292056 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 21424.487749 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 21424.487749 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 18585.816390 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 74043.117599 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74043.117599 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 173497.884095 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 173497.884095 # average WriteReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 110045.990066 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 110045.990066 # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13995 # number of replacements -system.l2c.tags.tagsinuse 787.283340 # Cycle average of tags in use -system.l2c.tags.total_refs 163090 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14802 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.018106 # Average number of references to valid blocks. +system.l2c.tags.replacements 13767 # number of replacements +system.l2c.tags.tagsinuse 787.442113 # Cycle average of tags in use +system.l2c.tags.total_refs 164717 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14568 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 11.306768 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 729.204744 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.276243 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.685702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.303189 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.305571 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.947966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.333904 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.314281 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.911739 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712114 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.007106 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.007506 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007132 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.007134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006785 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768831 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 807 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 673 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.788086 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2092027 # Number of tag accesses -system.l2c.tags.data_accesses 2092027 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 76994 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 76994 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 275 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 271 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 273 # number of UpgradeReq hits +system.l2c.tags.occ_blocks::writebacks 730.095360 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.568517 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.047502 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.052359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.453742 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.826765 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.175771 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.149899 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 8.072198 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.712984 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006882 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006887 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007279 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006667 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007008 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006982 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768986 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 661 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.782227 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2101238 # Number of tag accesses +system.l2c.tags.data_accesses 2101238 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 77585 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77585 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 280 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 286 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 296 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 265 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 264 # number of UpgradeReq hits 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accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11753 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11624 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11332 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 92567 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17989 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18040 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17880 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17857 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18168 # number of demand (read+write) accesses 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0.057725 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.066096 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.062441 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.299572 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.295288 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.299146 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.294855 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.295850 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.294370 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.296951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.303001 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.297365 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.299572 # miss rate for overall accesses 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-system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.886402 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.883681 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.883433 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.881612 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726527 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.713794 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.725039 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.734118 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.728843 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.729299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721715 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.724662 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.063363 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.067407 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062630 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.063476 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061017 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065821 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.061401 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.063430 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063565 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.298202 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.295868 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.298030 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.299811 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.295692 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.301007 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.300516 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.295190 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.299495 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.298202 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 51820.502247 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 51833.867780 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 51855.473994 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 51884.746725 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 51804.842637 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 51837.290138 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 51859.671649 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 51753.155631 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 51831.174608 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 52384.680018 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 52396.991893 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 52295.447876 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 52396.372296 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 52463.649145 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 52537.045445 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 52349.646070 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 52328.300236 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 52393.925931 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58581.380822 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 57851.861004 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 58264.415512 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58523.644022 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58044.042735 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 57528.255937 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58513.831006 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 58347.084584 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58201.100783 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 53246.480663 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 53190.557386 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 53095.892645 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 53245.171843 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 53191.526570 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 53243.287288 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 53183.021526 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 53145.900111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53192.449857 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51355.455046 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51346.619343 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51401.831965 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51276.397218 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51338.964862 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51319.320994 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51335.275480 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51301.669657 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51334.431525 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53016.913643 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53236.156088 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 53328.894925 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53198.964928 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53109.600294 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53001.749394 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53310.127841 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53104.918200 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53163.089516 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 51953.584482 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52015.486302 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52082.483601 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 51968.753092 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 51969.730583 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 51918.408937 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52047.761580 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 51948.726678 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 51988.024595 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.878683 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.876830 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.877178 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.883282 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.886558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.869204 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.872900 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880454 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.878139 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.726085 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.708571 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.727244 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.721145 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717549 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720280 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.721271 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.725980 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.720996 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060727 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062949 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063005 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062554 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.062125 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.059985 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.057467 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065743 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.061804 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.296690 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.298516 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.294678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.298591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.294239 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.295122 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.293600 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.296565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.302322 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.296690 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19237.777613 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19269.184185 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19290.727058 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19303.659712 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19276.070014 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19248.586311 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19230.378578 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19251.534192 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19263.681397 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22354.528063 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22422.961857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22275.815054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22547.604718 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22884.830516 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22625.916073 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22633.139407 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22492.943404 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 22529.055513 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59120.613960 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58754.313187 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59471.547067 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 58655.411034 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 58813.765035 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 58747.060993 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 58985.702096 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59138.512752 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 58962.207481 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 27160.820857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 27398.361362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 27340.736392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 27523.495153 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 27759.439279 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 27394.718914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 27140.101522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 27606.438284 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 27414.190686 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51836.922617 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51834.520021 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51837.208150 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51831.934617 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51793.861967 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51846.302571 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51891.205644 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51793.501639 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51833.236869 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 53272.199599 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 53730.930556 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 54048.480716 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 53785.831524 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 53636.094044 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 53581.986259 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 53652.224285 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 53756.660347 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 53682.780686 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 52355.251201 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 52512.033543 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 52626.282695 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 52528.620274 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 52451.299750 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 52468.690165 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 52513.652579 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 52504.088105 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 52495.065513 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 78245 # Transaction distribution -system.membus.trans_dist::ReadResp 84100 # Transaction distribution -system.membus.trans_dist::WriteReq 43522 # Transaction distribution -system.membus.trans_dist::WriteResp 43520 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6537 # Transaction distribution -system.membus.trans_dist::CleanEvict 1268 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61107 # Transaction distribution -system.membus.trans_dist::UpgradeResp 50201 # Transaction distribution -system.membus.trans_dist::ReadExReq 48942 # Transaction distribution -system.membus.trans_dist::ReadExResp 3181 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5862 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426485 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 426485 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1118817 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1118817 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56662 # Total snoops (count) -system.membus.snoop_fanout::samples 253744 # Request fanout histogram +system.membus.trans_dist::ReadReq 78306 # Transaction distribution +system.membus.trans_dist::ReadResp 84006 # Transaction distribution +system.membus.trans_dist::WriteReq 43633 # Transaction distribution +system.membus.trans_dist::WriteResp 43633 # Transaction distribution +system.membus.trans_dist::WritebackDirty 6315 # Transaction distribution +system.membus.trans_dist::CleanEvict 1254 # Transaction distribution +system.membus.trans_dist::UpgradeReq 60980 # Transaction distribution +system.membus.trans_dist::ReadExReq 48711 # Transaction distribution +system.membus.trans_dist::ReadExResp 3097 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 5709 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 375644 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 375644 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1089674 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1089674 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56426 # Total snoops (count) +system.membus.snoop_fanout::samples 252331 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253744 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 252331 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253744 # Request fanout histogram -system.membus.reqLayer0.occupancy 292620525 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 54.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 295409000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 55.3 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663684 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 282033 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335738 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12570 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5835 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6735 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 78248 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 369469 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43523 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43520 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83531 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 20342 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29636 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29633 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 160854 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 160848 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 291239 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121995 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122071 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122139 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122334 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 121723 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122513 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122322 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 977110 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766349 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778610 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781270 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1785072 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1775296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1771667 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1779976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778751 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14216991 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 333737 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 624990 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.150519 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.991140 # Request fanout histogram +system.membus.snoop_fanout::total 252331 # Request fanout histogram +system.membus.reqLayer0.occupancy 290210873 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 54.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 244257000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 46.1 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 663692 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283641 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 333885 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 12353 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 5692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 6661 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 78309 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370176 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43636 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43632 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 83900 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 105566 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29367 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29367 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161854 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161852 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291888 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133128 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133276 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133136 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 132901 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 132788 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1065036 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1790740 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1793737 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783183 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1779785 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1777562 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1801715 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1799686 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1764480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14290888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 334512 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 624442 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.148246 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.987708 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 174852 27.98% 27.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 256379 41.02% 69.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133497 21.36% 90.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 47307 7.57% 97.93% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 11157 1.79% 99.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1650 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 145 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 174331 27.92% 27.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 257461 41.23% 69.15% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 132941 21.29% 90.44% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 47060 7.54% 97.97% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 10899 1.75% 99.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1610 0.26% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 136 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 4 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 624990 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 497290718 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 93.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 100872915 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 100601006 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 18.8 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 101141480 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 100780789 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 100568051 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 18.8 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 100691951 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 18.9 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 101210192 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 100872512 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 18.9 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 624442 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 496537925 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 93.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 101982318 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102105458 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101942894 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101777352 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101724075 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101820787 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102063169 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101980781 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 564642e9d..7f5c6bd39 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.128077 # Nu sim_ticks 128076812500 # Number of ticks simulated final_tick 128076812500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 329011 # Simulator instruction rate (inst/s) -host_op_rate 420055 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 598785355 # Simulator tick rate (ticks/s) -host_mem_usage 256952 # Number of bytes of host memory used -host_seconds 213.89 # Real time elapsed on the host +host_inst_rate 887065 # Simulator instruction rate (inst/s) +host_op_rate 1132533 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1614418321 # Simulator tick rate (ticks/s) +host_mem_usage 277452 # Number of bytes of host memory used +host_seconds 79.33 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -612,18 +612,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3089 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 214325 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 15790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 34314 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 16890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36910 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2220672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54706 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 475898 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 530604 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2291072 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 20663744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 95333 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index c506601b8..d6835fc82 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.203116 # Nu sim_ticks 203115876500 # Number of ticks simulated final_tick 203115876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 563415 # Simulator instruction rate (inst/s) -host_op_rate 570710 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 851483432 # Simulator tick rate (ticks/s) -host_mem_usage 239344 # Number of bytes of host memory used -host_seconds 238.54 # Real time elapsed on the host +host_inst_rate 1130669 # Simulator instruction rate (inst/s) +host_op_rate 1145309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1708768878 # Simulator tick rate (ticks/s) +host_mem_usage 305928 # Number of bytes of host memory used +host_seconds 118.87 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -485,18 +485,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3547 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 209135 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 184923 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 36455 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 184976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 36468 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23804608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559024 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23808000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 41375360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 41378752 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 99021 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 436723 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt index dac1409b7..5cadbdde3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000043 # Nu sim_ticks 43191 # Number of ticks simulated final_tick 43191 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 247811 # Simulator tick rate (ticks/s) -host_mem_usage 388428 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_tick_rate 428274 # Simulator tick rate (ticks/s) +host_mem_usage 410016 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 57728 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index a72f38554..1db6620aa 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000054 # Nu sim_ticks 54211 # Number of ticks simulated final_tick 54211 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 192824 # Simulator tick rate (ticks/s) -host_mem_usage 389940 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host +host_tick_rate 316777 # Simulator tick rate (ticks/s) +host_mem_usage 410608 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 54016 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index 016399c56..5a3d40466 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000030 # Nu sim_ticks 29561 # Number of ticks simulated final_tick 29561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 198957 # Simulator tick rate (ticks/s) -host_mem_usage 389156 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 334780 # Simulator tick rate (ticks/s) +host_mem_usage 410240 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56000 # Number of bytes read from this memory diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt index 122a8ae41..d1da3d54a 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.000038 # Nu sim_ticks 37741 # Number of ticks simulated final_tick 37741 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 330031 # Simulator tick rate (ticks/s) -host_mem_usage 387076 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_tick_rate 544029 # Simulator tick rate (ticks/s) +host_mem_usage 408776 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60992 # Number of bytes read from this memory diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index d7fd446da..9f34f3699 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 435347 # Simulator instruction rate (inst/s) -host_op_rate 458966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 583184688 # Simulator tick rate (ticks/s) -host_mem_usage 252480 # Number of bytes of host memory used -host_seconds 394.73 # Real time elapsed on the host +host_inst_rate 1151849 # Simulator instruction rate (inst/s) +host_op_rate 1214340 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1543000471 # Simulator tick rate (ticks/s) +host_mem_usage 272972 # Number of bytes of host memory used +host_seconds 149.19 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -596,18 +596,18 @@ system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1448 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 287936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11226 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 291648 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 403456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 407168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4840 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.033471 # Request fanout histogram -- 2.30.2