From c6d6d407fcf54d65290dab68578265d55ce70b1f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 05:49:13 +0100 Subject: [PATCH] add implementation of CSR SV CFG regs 0-7 this is a CAM table of key-value entries, 5-bits key (from instruction) 6-bits value (actual register table, now 64 entries) TODO: obviously RV32E that would be reduced. TODO: make it optional to have 32-32 --- riscv/processor.cc | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 7d95c49..f353c8b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -368,9 +368,29 @@ void processor_t::set_csr(int which, reg_t val) } // okaaay and now "unpack" the CAM to make it easier to use. this // approach is not designed to be efficient right now. optimise later + // first clear the old tables + memset(state.sv_int_tb, 0, sizeof(state.sv_int_tb)); + memset(state.sv_fp_tb, 0, sizeof(state.sv_fp_tb)); + // now walk the CAM and unpack it for (int i = 0; i < SV_CSR_SZ; i++) { - // TODO + union sv_reg_csr_entry *c = &state.sv_csrs[i]; + uint64_t idx = c->b.regidx; + sv_reg_entry *r; + // XXX damn. this basically duplicates sv_insn_t::get_regentry. + if (c->b.type == 1) + { + r = &state.sv_int_tb[idx]; + } + else + { + r = &state.sv_int_tb[idx]; + } + r->elwidth = c->b.elwidth; + r->regidx = c->b.regidx; + r->isvec = c->b.isvec; + r->packed = c->b.packed; + r->active = true; } break; } -- 2.30.2