From c6f371ad7b115cd0b3261d750ce48ebca4360b9f Mon Sep 17 00:00:00 2001
From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Mon, 25 Sep 2023 18:29:29 +0100
Subject: [PATCH] Added english language description, spaces and brackets for
 lhzux instruction

---
 openpower/isa/fixedload.mdwn | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 94d59dd0..036ac57c 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -186,6 +186,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    The halfword in storage addressed by EA is loaded into
+    RT[48:63]. RT[0:47] are set to 0.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None
-- 
2.30.2