From c6fdfe18075f011288f35c18a7d267408838b08d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 6 Jul 2022 18:54:07 +0100 Subject: [PATCH] add first stub of svindex pseudocode https://bugs.libre-soc.org/show_bug.cgi?id=885 --- openpower/isa/simplev.mdwn | 35 ++++++++ .../decoder/isa/test_caller_svindex.py | 88 +++++++++++++++++++ 2 files changed, 123 insertions(+) create mode 100644 src/openpower/decoder/isa/test_caller_svindex.py diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index f407851e..eb791092 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -265,3 +265,38 @@ Special Registers Altered: None +# svindex + +SVI-Form + +* svindex RS,rmm,SVd,ew,yz,mr,sk + +Pseudo-code: + + # VL in Matrix Multiply is xd*yd*zd + n <- (0b00 || SVxd) * (0b00 || SVyd) * (0b00 || SVzd) + # set up template, then copy once location identified + shape = [0]*32 + shape[30:31] <- 0b00 # mode + if yz = 1 then shape[18:20] = 0b110 # indexed xd/yd + else shape[18:20] = 0b111 # indexed yd/xd + shape[0:5] <- (0b0 || SVxd) # xdim + shape[6:11] <- (0b0 || SVyd) # ydim + shape[12:17] <- (0b0 || SVzd || 0b0) # SVGPR + shape[28:29] <- ew # element-width override + if sk = 1 then shape[28:29] <- 0b01 # skip 1st dimension + else shape[28:29] <- 0b00 # no skipping + # select the mode for updating SVSHAPEs + if mm = 0 then + # clear out all SVSHAPEs first + SVSHAPE0[0:31] <- [0] * 32 + SVSHAPE1[0:31] <- [0] * 32 + SVSHAPE2[0:31] <- [0] * 32 + SVSHAPE3[0:31] <- [0] * 32 + SVSTATE[42:46] <- rmm # rmm exactly REMAP.SVme + SVSTATE[62] <- 0 # persistence bit cleared + +Special Registers Altered: + + None + diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py new file mode 100644 index 00000000..39ea23ed --- /dev/null +++ b/src/openpower/decoder/isa/test_caller_svindex.py @@ -0,0 +1,88 @@ +"""SVP64 unit test for doing strange things to SVSTATE, manually. +""" +from nmigen import Module, Signal +from nmigen.back.pysim import Simulator, Delay, Settle +from nmutil.formaltest import FHDLTestCase +import unittest +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.sv.trans.svp64 import SVP64Asm +from openpower.consts import SVP64CROffs +from copy import deepcopy + + +class SVSTATETestCase(FHDLTestCase): + + def _check_regs(self, sim, expected): + print ("GPR") + sim.gpr.dump() + for i in range(32): + self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) + + def test_sv_index(self): + """sets VL=2 (via SVSTATE) with a manual srcstep/dststep, + then does a scalar-result add. the result should be: + + add 1, 6, 10 + + because whilst the Vector instruction was moved on by srcstep, + the Scalar one is NOT moved on. + """ + isa = SVP64Asm(['svindex 1, 31, 5, 0, 0, 0, 0' + ]) + lst = list(isa) + print ("listing", lst) + + # initial values in GPR regfile + initial_regs = [0] * 32 + initial_regs[9] = 0x1234 + initial_regs[10] = 0x1111 + initial_regs[5] = 0x4321 + initial_regs[6] = 0x2223 + + # SVSTATE vl=10 + svstate = SVP64State() + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + + # copy before running + expected_regs = deepcopy(initial_regs) + #expected_regs[1] = 0x3334 + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, initial_regs, svstate=svstate) + self._check_regs(sim, expected_regs) + + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + print (" srcstep", bin(sim.svstate.srcstep)) + print (" dststep", bin(sim.svstate.dststep)) + print (" RMpst", bin(sim.svstate.RMpst)) + print (" SVme", bin(sim.svstate.SVme)) + print (" mo0", bin(sim.svstate.mo0)) + print (" mo1", bin(sim.svstate.mo1)) + print (" mi0", bin(sim.svstate.mi0)) + print (" mi1", bin(sim.svstate.mi1)) + print (" mi2", bin(sim.svstate.mi2)) + + def run_tst_program(self, prog, initial_regs=None, + svstate=None): + if initial_regs is None: + initial_regs = [0] * 32 + simulator = run_tst(prog, initial_regs, svstate=svstate) + simulator.gpr.dump() + return simulator + + +if __name__ == "__main__": + unittest.main() + -- 2.30.2